MOS High Performance Arithmetic

Transcription

1 MOS High Performance Arithmetic Mark Horowitz Stanford University

2 Arithmetic Is Important Then Now (TegraK1) 2

3 What Is Hard?

4 Proof: 1 st Gen 2 nd Gen 4

5 And Getting The Data You Need But we didn t notice this until much later To notice this problem We need many advances in technology 5

6 3 rd Gen Relays (Z3 1940) A few adds/sec 6

7 4 th Gen Tubes (Eniac 1945) 5000 Adds/sec 7

8 5 th Gen Transistors (TX-0, Transistor ) TX-0 8

9 Modern Era IC, 1961 Image from State of the Art Stan Augarten 9

10 Moore s Law From Electronics, Volume 38, Number 8, April 19, 1965 Number of components on IC doubles every year Later modified to doubling every 18 to 24 months 10

11 ECL Computers 11

12 Microprocessor MOS Processor (1974)

13 nmos

14 CMOS 1985 To Present

15 CMOS (Arithmetic) Design What makes a good design? 15

16 Try to Balance 4 Parameters Area Performance Power Design Time 16

17 The Good News By the time CMOS came along There had been a lot of work on arithmetic Booth coding Wallace trees Ling coding Tree adders Manchester carry chains SRT division 17

18 The Bad News The best logical design depends on technology Remember the carry dependency? For relays a Manchester carry chain is the best All the delay is in changing the relay state P0_pv1 P1_pv1 P2_pv1 G0_pv1 G1_pv1 G2_pv1 18

19 More Bad News The metrics you are optimizing work in opposition Energy Performance 19

20 Just to Make Life More Complicated Your metrics change w/ technology scaling 20

21 Must Use Technology Independent Metrics Performance In terms of a FO4 delay FO4 Fanout=4 inverter delay at TT, 90% Vdd, 125C * Ldrawn Gate delay (ps) Technology Ldrawn (um) 21

22 Area and Energy Area Measure linear dimensions in features Energy CMOS energy is Normalize by 22

23 Dennard s Scaling The triple play: Get more gates, 1/L 2 1/ 2 Gates get faster, CV/i Energy per switch CV 2 3 Dennard, JSSC, pp , Oct

24 Three Era s of CMOS Arithmetic Design Getting Going Area constrained Party time! Performance Constrained The hangover Power Constrained 24

25 GETTING STARTED 25

26 Life in the 80 s Just learning how to design complex chips Chips had 100K transistors Almost no CAD tools Worried about it getting the design done And getting all the functions to fit on chip Getting the design to fit was job one Getting it to go fast was job two 26

27 Main Effects on Arithmetic Circuits Merged Function Blocks ALU A B Lookup Table P F 27

28 Precharge Logic static current W Dual pmos Network W precharge A non-overlapping (good, but not always possible) 2W B precharge precharge 2W evaluate evaluate evaluate Psuedo-nMOS CMOS Pre-Charge 28

29 Carry Chains, and Carry Skip Adders P0*P1*P2*P3 Cin Carry Carry Carry Carry Cout C0 C1 C2 C3 PG Cin =0 XOR Cin=1 XOR Mux 29

30 Iterating Structures Main processor Just use instructions (micro-code) and ALU Co-processor Also used iterating structures But built these structures for multiple or division Often asynchronous 30

31 MIPS R3010 Multiplier Clocked by internal oscillator, not external clock CSA CSA 31

32 A Self-Timed Pipeline C C C C prech prech prech prech clk clk clk clk out+ outout+ out- out+ out- out+ out- in+ inin+ inin+ inin+ in- 32

33 A Self-Timed Pipeline Data enters at the far left and the NOR gate flips This activates the C-element C C C C prech prech prech prech clk clk clk clk out+ outout+ out- out+ out- out+ out- in+ inin+ inin+ inin+ in- 33

34 A Self-Timed Pipeline First logic block goes into evaluate C C C C eval prech prech prech clk clk clk clk out+ outout+ out- out+ out- out+ out- in+ inin+ inin+ inin+ in- 34

35 A Self-Timed Pipeline C C C C eval prech prech prech clk clk clk clk out+ outout+ out- out+ out- out+ out- in+ inin+ inin+ inin+ in- 35

36 A Self-Timed Pipeline Second block goes into evaluate Primary inputs are deasserted, flipping the first NOR gate C C C C eval eval prech prech clk clk clk clk out+ outout+ out- out+ out- out+ out- in+ inin+ inin+ inin+ in- 36

37 Division - SRT Ted Williams Completely self-timed 37

38 PARTY TIME! 38

39 Performance, Performance, Performance Scaling provided Enough transistors Low energy, and fast gates Goal was to find the fastest structures Lots of dual rail domino logic Started to build full array/trees Many of the trees were regular (4:2 adder) for designer sanity 39

40 Ling Adder Implementation Sam Naffziger (HP, 1996) presented a 64b adder 7 FO4 delay (< 1nS): pretty darn fast 0.5 m CMOS From VLSI lecture notes in early 2000 s 40

41 Kogge Stone Adders H 64 0 H H64 H16/I16 H4/I4 cin (g 0, t 0 ) (g 62, t 62 ) 41

42 Alignment Shifter Build full shifter 42

43 Even Fuse Multiplier and Adder Together IBM Power 6 FMA 5 GHz 7-stage in 65nm Dependent unrounded results forwarded making dependent latency 6 cycles instead of 7 (6,6,7) design 43

44 Life Was Good, For a While 44

45 THE HANGOVER 45

46 But You Have to Pay Eventually 46

47 The Power Limit Watts/mm

48 Clever Power Increased Because We Were Greedy 10x too large 48

49 This Power Problem Is Not Going Away: P = C * Vdd 2 * f L

50 Think About It 50

51 32 bit CMOS Adder Design Space domino Sklansky Ling w/ 2bit sum select static Sklansky 10 Energy in pj dual rail Sklansky Ling Delay in 100ps 51

52 Performance Metrics Normally think of delay of unit But that only matter if there is a dependent op Many applications have many non-dependent ops These are throughput based systems Adding units improves performance 52

53 The Rise of Multi-Core Processors 53

54 The Stagnation of Multi-Core Processors 54

55 Throughput Based Designs For applications with abundant parallelism Leveraging parallelism helps energy efficiency But when do you stop Lower performance is almost always lower energy Minimum energy designs, Sea of very slow processors Meters of silicon area What to optimize? 55

56 56 Optimize Energy/Op vs. Area/Throughput

57 Floating Point Optimization 180nm ITRS 10nm 57

58 In This Space the Details Matter Implementation of Booth Mux More important then whether Booth 2, or Booth 3 How you wire the CSA array Is more important than the type of counter Most fancy adder tricks Produce worse designs 58

59 Built an FP Generator in

60 FMA Output 60

61 CMA vs. FMA For Latency For Throughput 61

62 Have A Shiny Ball, Now What? 62

63 Today FP Units are Not the Problem 8 cores L1/reg/TLB L2 L3 63

64 Rough Energy Numbers (45nm) Integer FP Memory Add FAdd Cache (64bit) 8 bit 0.03pJ 16 bit 0.4pJ 8KB 10pJ 32 bit 0.1pJ 32 bit 0.9pJ 32KB 20pJ Mult FMult 1MB 100pJ 8 bit 0.2pJ 16 bit 1pJ DRAM nJ 32 bit 3 pj 32 bit 4pJ Instruction Energy Breakdown 25pJ 6pJ Control 70 pj I-Cache Access Register File Access Add 64

65 What Is Going On Here? Dedicated 1000 Energy Efficiency (MOPS/mW) CPUs CPUs+GPUs GP DSPs ~1000x

66 The Truth: It s More About the Algorithm then the Hardware All Algorithms GPU Alg 66

67 Highly Local Computation Model 67

68 Highly Local Computation Model 68

69 Highly Local Computation Model 69

70 Compose These Cores into a Pipeline Program in space, not time Makes building programmable hardware more difficult 70

71 Great, But Can A User Program It? Frankencamera 4 User code Cool images 71 71

72 Goals Have user code in a image friendly language Language should facilitate writing image/vision processing Analyze/compile the language for different targets CPU / GPU / FPGA Create not just the hardware bit file But also the hardware drivers and application level API 72

73 How: Constructors to Encode Domain Knowledge Encapsulate domain knowledge in the system Build constructor from lower level constructors Clean interfaces are critical Reuse both constructor and most of the configuration file 73

74 Halide Language Language for creating fast image processing apps Separate algorithm from schedule Target CPU and GPU 74

75 What Halide Does For You Tiled Fused Vectorized Multithreaded 11x faster And not readable 75

76 Architecture Template: Stencil Functions and Line Buffers Stencil functions consume sliding windows of data Huge locality To capture this locality need to buffer a few lines Line buffer is the hardware buffer block. 76

77 Design Flow 77

78 Performance Results Performance compared to Nvidia TK1 78

79 Energy Results 79

80 Conclusions Designing the best arithmetic unit depends on: Technology and constraints Finding the right metrics is critical Details matter Must assess performance/area/energy of your idea Generators (procedural knowledge) is a good approach to do this Key to performance scaling in the future is the memory Need applications with high locality 80