POWER PERFORMANCE OPTIMIZATION METHODS FOR DIGITAL CIRCUITS
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1 POWER PERFORMANCE OPTIMIZATION METHODS FOR DIGITAL CIRCUITS Radu Zlatanovici Department of Electrical Engineering and Computer Sciences University of California, Berkeley
2 Power and Performance with Scaling If we continue doing business as usual, both dynamic and leakage power will be a problem chips are getting hot and phones leaky! Need to deliver maximum performance under power constraints From S. Borkar, Intel 2
3 A Common Problem Logic Logic Logic Need to reduce power by 30%, while willing to give up 3% of performance What to do: Decrease supply? Increase thresholds? Downsize? Downsize latches or logic? Use dual supplies? Re-pipeline? Parallelize? 3
4 Outline Design as a power performance optimization problem Fundamentals of circuit optimization Design examples Dealing with variations Conclusions Collaborative effort: Students: R. Zlatanovici, D. Markovic, L.-T. Pang, J. Garrett, S. Kao Faculty: B. Nikolic, R. Brodersen 4
5 Power Performance Optimization Power Initial design Power-optimal design Design within power budget Cycle time OPTIMAL POWER PERFORMANCE TRADEOFF CURVE 5
6 Power Limited Operation Power Unoptimized design P max P min D min D max Delay Achieve the highest performance under the power cap 6
7 Power Limited Operation Power P max P min Unoptimized design Var1 Design optimization curves D min D max Delay Achieve the highest performance under the power cap 7
8 Power Limited Operation Power P max P min Unoptimized design Var2 Var1 Design optimization curves D min D max Delay Achieve the highest performance under the power cap 8
9 Power Limited Operation Power P max P min Unoptimized design Var2 Var1 Var1 + Var2 Design optimization curves D min D max Delay How far away are we from the optimal solution? 9
10 Power Limited Operation Power P max P min Global Unoptimized design Var2 Var1 Var1 + Var2 Design optimization curves D min D max Delay Global optimum best performance 10
11 Design Optimization There are many sets of parameters to adjust: Circuit (sizing, supply, threshold Logic style (domino, static, pass-gate, Block topology (adder: CLA, CSA, RCA, Micro-architecture (parallel, pipelined Power topology A topology B Delay 11
12 Design Optimization There are many sets of parameters to adjust: Circuit (sizing, supply, threshold Logic style (domino, static, pass-gate, Block topology (adder: CLA, CSA, RCA, Micro-architecture (parallel, pipelined Power topology A topology B Delay Globally optimal boundary curve: pieces of E-D curves for different topologies 12
13 Outline Design as a power performance optimization problem Fundamentals of circuit optimization Design examples Dealing with variations Conclusions 13
14 Optimization Problem min x R g h i j n ( x ( x f ( x subject to 0 i = 1.. m = 0 j = 1.. p f(x αx 1 +(1- αx 2 Very difficult in the general case Optimality not guaranteed Convex Optimization f, g i convex, h j linear Key property: every local minimum is a global minimum Optimality guaranteed x 1 Y x 2 x 14
15 Circuit Optimization Plug-ins Models Netlist Optimization Goal Variables Optimization Core Static timer (C++ Cycle time, Power Optimizer (Matlab Design Variables Results Optimal Design 15
16 Power Constrained Optimization Problem Minimize DELAY subject to Maximum POWER Basic Result: Power - Performance tradeoff curve Constraints: Maximum output slew Maximum internal slew Maximum input capacitance Minimum sizes Power Delay 16
17 PD, PD 2, P 2 D : Obsolete Power P 0 D 1 P a D b P 1 D 0 Delay ALL P-D METRICS ARE INCLUDED IN THE TRADEOFF CURVE 17
18 Choice of Models ANALYTICAL - Limited accuracy + Fast parameter extraction + Provide insight in the operation of the circuit + Can exploit their mathematical properties to help optimization Target: convex optimization TABULATED + Very accurate - Slow to generate - No insight in the operation of the circuit - Can t guarantee convexity - Optimization is blind If convex models are any good, the optimization problem is not very nonconvex 18
19 W 1 W 2 W 3 W 4 C L Logical Effort: Delay of a Logic Path t D C in = p + = g C C g C inv L in W b = C on path + C C off on path path g 1, p 1 g 2, p 2 g 3, p 3 g 4, p 4 D = N N N Cload, i p + = + i gi pi C i= 1 in, i i= 1 i= 1 g i bi g g i+ 1 i W W i i+ 1 19
20 Posynomial Functions Definition of a posynomial: p( x γ j i= 1 A posynomial can be converted to a convex function using a simple change of variables: x i = e Z i for x i 0 Logical effort delay is posynomial Fishburn, ICCAD 85: Elmore delay formula can be written as a posynomial Switching energy is linear in W i = j n posynomial Convex optimization with posynomials is called geometric programming x α i ij α ij R γ j R + 20
21 V DD - Dependent Analytical Delay Model d Gate equivalent resistance can be computed from analytical saturation current models (a reduced form of the BSIM3v3 equation R EQ V 1 = V / 2 DD V DS ( β1v DD + β W K( V Include supply and threshold dependency in the delay model: CL = c2 REQ ( W, VDD, VTH + c1req ( W, VDD, VTH + ( η 0 + η1v DD t Cin Accurate over a reasonable yet limited range of fanouts (2.5-6, supplies and threshold (+/- 30% Most datapath blocks are within this range Compatible with convex optimization Captures dependencies on V DD and V TH Work by Joshua Garrett DD DD V I dv DS = 3 4 V DD 0 + V V V 2 (1 7V 9V / 2 DSAT DD TH A DD TH DD they can be optimization variables s, in 21
22 Vdd and W Optimization 22
23 Vth,Vdd and W Optimization 23
24 Outline Design as a power performance optimization problem Fundamentals of circuit optimization Design examples Dealing with variations Conclusions 24
25 Dual V DD ALU in Domino Logic clock gen. INV2 9:1 MUX 9:1 MUX ain0 5:1 MUX 2:1 MUX : V DDH circuit : V DDL circuit ain bin clk gp gen. R4 SP4 carry tree partial sum logical unit carry sum sel. s0/s1 sum INV1 0.5pF Y. Shimazaki, R. Zlatanovici, B. Nikolic: A Shared Well Dual Supply Voltage 64-bit ALU ISSCC 03, JSSC 03/
![Extending the Space: Dual Supply Energy [pj] 1000 900 800 700 600 500 400 300 200 V DDL decreases.](/docs-images/85/91871975/images/26-0.jpg "Room temp. V DDH =V DDL V DDH =2.0 V DDH =1.8 V DDH =1.6 0.6 0.8 1.0 1.2 1.4 1.6 T CYCLE [ns] 26")
26 Extending the Space: Dual Supply Energy [pj] V DDL decreases. Room temp. V DDH =V DDL V DDH =2.0 V DDH =1.8 V DDH = T CYCLE [ns] 26
27 CLA Adders in E-D Space Adders are common in critical paths CLA adders: Many designs, commonly used in practice Recent interest in sparse adders No fair comparison in energy delay space This work: Optimization of representative 64-bit adders in energy delay space Optimal 64-bit adder design R. Zlatanovici, B. Nikolic: Power Performance Optimal 64-Bit Carry-Lookahead Adders, ESSCIRC
28 64-Bit CLA Adders Generic 64-bit adder block diagram a [ 0:63 ] b [ 0:63 ] Carry Tree Sum Precompute Carry[...] S0[0:63] S1[0:63] Sum Select Sum [ 0:63 ] Classical CLA, Ling equations Static, single-rail domino, compound domino logic Radix-2 and radix-4 carry trees Full and sparse trees (sparseness of 2 and 4 Use tabulated delay and analytical energy models (switching, leakage 28
29 Equation Set Comparison Energy [pj] R2 Ling R2 CLA R4 Ling R4 CLA Delay [FO4] Ling adders achieve shorter delays Radix-4 are faster than radix-2 29
30 Chosing a Logic Style Energy [pj] Static R2 Domino R4 Domino R2 Compound Domino R Delay [FO4] Static adders are low power but slow Domino logic is the choice for short cycle times 30
31 Full vs. Sparse Trees (a 0, b 0 (a 1, b 1 R2 Full S 0 S 1 (a 0, b 0 (a 1, b 1 R2 SP2 S 0 S 1 Sparse trees: (a 2, b 2 (a 3, b 3 (a 4, b 4 S 2 S 3 S 4 (a 2, b 2 (a 3, b 3 (a 4, b 4 S 2 S 3 S 4 Heavier load on the carry tree (a 5, b 5 (a 6, b 6 (a 7, b 7 S 5 S 6 S 7 (a 5, b 5 (a 6, b 6 (a 7, b 7 S 5 S 6 S 7 Reduced input loading (a 8, b 8 (a 9, b 9 (a 10, b 10 (a 11, b 11 S 8 S 9 S 10 S 11 (a 8, b 8 (a 9, b 9 (a 10, b 10 (a 11, b 11 S 8 S 9 S 10 S 11 More complex sum precompute gates (a 12, b 12 S 12 (a 12, b 12 S 12 (a 13, b 13 S 13 (a 13, b 13 S 13 (a 14, b 14 S 14 (a 14, b 14 S 14 (a 15, b 15 S 15 (a 15, b 15 S 15 31
32 Proof of Existence: Fastest Adder Radix-4 sparse-2 domino Ling adder Technology: 90 nm 1P 7M V DD = 1 V Performance: Delay: 210 ps (post layout simulation Energy: 9.1 pj / cycle (optimization tool Core dimensions: mm x 75.3 mm Chip to be taped out 11/1/04 *with Sean Kao 32
33 Micro-Architecture Optimization: Power4 FPU Exponent Path (non-critical B A C Pad & Align Multiplier FA bit adder cycles 2-phase clocking Static CMOS Normalize 53 33
34 Optimizing Pipelined Circuits Models: Posynomials Block Level Netlist Minimize T CYCLE Subject to Maximum ENERGY Gate Sizes Latch Positions Cycle boundaries: transparent latches COMBINATIONAL LOGIC Static timer Optimizer Optimal Pipeline Configuration Fix pipeline depth Find shortest cycle time for fixed cutset Search for optimum cutset Work in progress 34
35 Outline Design as a power performance optimization problem Fundamentals of circuit optimization Design examples Dealing with variations Conclusions 35
36 Robust Optimization Parameters are within an ellipsoid centered on the nominal values Optimize the worst case Compatible with convex optimization for the presented analytical models Problem: computing the ellipsoid 36
37 Stochastic Optimization for Yield Parameters are random variables centered on the nominal values Optimize for a desired yield min x R subject to g i n f ( x ( x 0 i = 1.. m Compatible with convex optimization under certain conditions Convex analytical models Jointly Gaussian parameters min subject to P( g ( x Problem: finding the distributions of the parameters, especially the correlations x R n i f ( x 0, i = 1.. m η 37
38 Impact of Layout on Variations Stacked gates vs. non-stacked gates (e.g. gates vs. buffers Proximity effects, orientation of gates, metal layer above gate (annealing PolySi gates Dummy gates M1 M1 Stacked gates Work by Liang Teck Pang Non-stacked gates 38
39 Test Chip 90nm 1P 7M V DD = 1 V 1.55 x 1.17 mm 2 Taped out 9/04 To be packaged and tested Measurements will provide statistical data for the stochastic optimizer 39
40 Conclusions Power and performance are the two sides of the same coin. The connection: the power performance tradeoff curve. Built a suite of stackable tools to design power performance optimal circuits Design space explorations: Different optimization variables Various levels of abstraction Impact of variations Experimented the tool suite on various designs Dual-supply ALU CLA Adders in the E-D space 40
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