Computer Architecture Ι Fall 2003 Lec.03-1

Transcription

1 Computer Architecture Ι Fall 2003 Lec.03-1

2 Intro Instructor: StefanosKaxiras Few things about me: Just moved in Uppsala Professor Computer Architetcure 2003 Prof. Univ. of Patras, Greece Bell Labs (Unix& C group), Ph.D. Univ. of Wisconsin, 1998 Don t speak Swedish Course taught in English with your participation! Fall 2003 Lec.03-2

3 What the course is about: Computer organization + Digital Design Transistors digital circuits arithmetic logic units (adders) processors & memory computers Interface to the bare H/W Basic operations microprogramming / microarchitecture instruction set architecture (ISA) Assembly Finishing this course you should be able to: Understand the functionality and operation of the basic elements of a computer system, including processor, memory, input/output Reason about first-order performance of a computer system Understand the hardware/software interface Understand and write programs in assembly language Fall 2003 Lec.03-3

4 Books Computer Organization & Design. The Hardware/Software Interfaceby Patterson & Hennessy, 4thedition Morgan Kaufmann Publ Note that the 3rd edition is not significantly different and it can substitute for the 4th edition Fall 2003 Lec.03-4

5 Assignements Assembly Fall 2003 Lec.03-5

6 Assignments (cont.) LogicSIM Publicly available for download Easy digital design Goal: to build a processor to execute instructions Fall 2003 Lec.03-6

7 Overview of the Course The hardware/software interface Introduction + history Computer Arithmetic Performance Instruction Set Architecture Assembly programming Processors(After basicdigital Design) Processor structure & operation ALUs, control, datapath Singlecycleimplementation Multicycleimplementation Pipelining Advanced architecture Memory Memory system and caches Virtual memory IO Fall 2003 Lec.03-7 I/O

8 Schedule (The hardware/software interface) Vecka12 Tis 22 mar 13:15-15:00 Introduction Tor 24 mar 10:15-12:00 Arithmetic Vecka13, 2011 Mån 28 mar 10:15-12:00 More Arithmetic Ons 30 mar 10:15-12:00 Performance Fre 1 apr 13:15-15:00 ISA 1 Vecka14, 2011 Mån 4 apr 13:15-15:00 ISA 2 Tis 5 apr 10:15-12:00 Assembly Tutorial Ons 6 apr 13:15-15:00 Assembly Tutorial Fre 8 apr 08:15-12:00 Laboration Fall 2003 Lec.03-8

9 Credits Slides and material ADAPTED from: KarlMarklund sslides,uppsalauniversity JustinPearson sslides,uppsalauniversity Slides originally developed by Profs. Hill, Falsafi, Marculescu, Patterson, Rutenbarand Vijaykumarof CMU, Purdue, UCB, UW, Copyright 2003 StefanosKaxiras slides, University of Patras& Uppsala Univeristy Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc Fall 2003 Lec.03-9

10 Introduction Some historical background and anecdotes Fall 2003 Lec.03-10

11 Contemporary Multilevel Machines A six-level computer(tanenbaum). The support method for each level is indicated below it Fall 2003 Lec.03-11

12 Milestones in Computer Architecture PRE-HISTORY Fall 2003 Lec.03-12

13 Milestones in Computer Architecture EARLY-HISTORY The birth of the Modern-era Computer Fall 2003 Lec.03-13

14 A Historical Perspective In the beginning...eniac 5,000 additions in one second Fall 2003 Lec.03-14

15 ENIAC Built at the University of Pennsylvania Lt Gillon, Eckert and Mauchley Initial contract for $61,700, June 1943 eventually cost $486,804.22, in 1946 Accumulator deployed in Jun 1944 Accumulator, multiplier, divide and square root and 3 portable function tables completed in Fall µsecond cycle time for 1 add Internals 19K vacuum tubes, 1.5K relays, 100K s of resistors, and inductors; 30 separate units; forced air cooling; Multiply s in base 10; just like a human Originally, no internal memory --> programmed w/cables and switches Designed to compute firing tables Differential equations of motion to compute trajectory in 15 seconds (same amount of computation took a human 20 hours) Power = 200K Watts Fall 2003 Lec.03-15

16 ENIAC: programming in hardware Fall 2003 Lec.03-16

17 Von Neumann Machine: The concept of the Stored- Program Computer The original Von Neumann machine: DATA and PROGRAM are BOTH in the SAME MEMORY Fall 2003 Lec.03-17

18 Computer Generations Zeroth Generation Mechanical Computers ( ) First Generation Vacuum Tubes ( ) Second Generation Transistors ( ) Third Generation Integrated Circuits ( ) Fourth Generation Very Large Scale Integration (1980?) Fall 2003 Lec.03-18

19 Milestones in Computer Architecture The beginning of the Computer Age Fall 2003 Lec.03-19

20 Milestones in Computer Architecture (2) Evolution of the Computer: Mainframes, Minis, Supercomputers, Workstations, and PCs (the Killer Micros) Fall 2003 Lec.03-20

21 Some Important Computers DEC PDP-8 PDP-11 VAX-11 the king of the minis IBM 360 the Mainframe The supercomputers: CDC 6600, CRAY-1 The microprocessors: Intel 8086 The RISCs: MIPS, SPARC, ALPHA, Pentium 4, Core-2, EXCELLENT resources on the Web for the history of these computers, especially wikipediahas great articles for all these Fall 2003 Lec.03-21

22 PDP-8 Innovation Single Bus The PDP-8 omnibus Primitive machine: 8 basic instructions! 4K to 32K word memory (12-bit words) Fall 2003 Lec.03-22

23 VAX-11 VAX-11: Virtual Address extensionto to pdp11 Extremely popular university computer Modern computer science developed on it One of the most complex machine instruction sets ever! An Instruction could be a whole loop! Studies showed that compilers could not use all these instructions The nominal 1-MIPS machine BSD Unix, TCP/IP,, took off on this machine Fall 2003 Lec.03-23

24 IBM 360 Before 360: architecture == implementation 360 (Gene Amdahl): architecture independent of implementation! One ISA, multiple instantiations SAME Software runs on ALL! (Radical development) Backwards compatibility: crucial for an architecture Intel Apple!!!! Motorola PowerPC Intel and ALWAYS maintained software compatibility. IBM 360 also run (emulated) IBM 1401 and Fall 2003 Lec.03-24

25 Supercomputers 1 st st Supercomputer: CDC 6600 (Seymour Cray) Could perform more than one instruction at the same time! (Superscalar-- Scoreboard) Pipelined Very fast cycle time 10 Peripheral processors for I/O No ECC or parity in memory Correct answer? Fall 2003 Lec.03-25

26 CRAY CRAY-1 First VECTOR supercomputer Instructions could operate directly on vectors: A[i] = B[i] + C[i], i=0, Fall 2003 Lec.03-26

27 The dawn of the micros (mid 70 s) Intel: 8051, 8080 Motorola 6800 ZilogZ80 MOS bit micros, 8-bit words, 64K memory Invariably microprogrammedarchitectures running at about 1 2 MHz 80 s: 16-bit micros: Intel 8086/8088, Motorola Up to 1 MB memory in 8086 via Segmentation 16 MB in MC Precursors of the CISCs: 80386,486,Pentium,Pro,II,III,4,Core Fall 2003 Lec.03-27

28 RISCs Introduced the concept of smaller (ISA) is better RISC: Reduced Instruction Set Computers No microcore, all hardware, pipelined, many registers, very simple instructions Pioneered by: Berkeley (Patterson) SPARC (SUN) Stanford (Hennessy) MIPS (MIPS) First RISC IBM 801, First commercial RISC: ARM Others: HP PA-RISC, DEC ALPHA, IBM/Motorola PowerPC, IBM Power, Fall 2003 Lec.03-28

29 Intel Computer Family (1) The Intel CPU family. Clock speeds are measured in MHz (megahertz) where 1 MHZ is 1 million cycles/sec Fall 2003 Lec.03-29

30 Intel Computer Family (2) The Pentium 4 chip. The photograph is copyrighted by the Intel Corporation, 2003 and is used by permission Fall 2003 Lec.03-30

31 Personal Computer 1. Pentium 4 socket P Support chip 3. Memory sockets 4. AGP connector 5. Disk interface 6. Gigabit Ethernet 7. Five PCI slots 8. USB 2.0 ports 9. Cooling technology 10. BIOS A printed circuit board is at the heart of every personal computer. This figure is a photograph of the Intel D875PBZ board. The photograph is copyrighted by the Intel Corporation, 2003 and is used by permission Fall 2003 Lec.03-31

32 Four Decades of Microprocessor The Decade of the 1970 s Microprocessors - Programmable Controller / Single-Chip Microprocessors - Personal Computers (PC) The Decade of the 1980 s Quantitative Architecture - Instruction Pipelining - Fast Cache Memories - Workstations The Decade of the 1990 s Instruction-Level Parallelism - Superscalar Processors - Speculative Microarchitectures - Aggressive Code Scheduling - Low-Cost Desktop Supercomputing The Decade of the 2000 s Power & memory wall Multicore - Multiprocessor on a Chip (CMP), Multicore - Massively parallel GP-GPUs - Manycores? Fall 2003 Lec.03-32

33 Moore s LAW Moore said: every chip generation (3 years) # transistors double Law: transistor # doubles every 18 months! Fall 2003 Lec.03-33

34 More on Moore s Law Corollary 1: speed of circuits (clock frequency, MHz or GHz) doubles every 18 months. Smaller transistors are also faster! Corollary 2: Performance doubles every 18 months! BUT: ARCHITECTURE translates the increase in transistors to an increase in performance Examples: add vs. memory access Instructions per cycle: MAJOR ARCH. Contribution to Perf. Exponential increase in performance with every generation: What does it mean? Fall 2003 Lec.03-34

35 Computing power as area: what part of a 2005 processor corresponds to a 1995 processor? 12/2005 6/ /2002 6/ /1999 6/ /1996 6/ Fall 2003 Lec.03-35

36 Technology => dramatic change Processor logic capacity: about 30% per year clock rate: about 20% per year Memory DRAM capacity: about 60% per year (4x every 3 years) Memory speed: about 10% per year Cost per bit: improves about 25% per year Disk capacity: about 60% per year Fall 2003 Lec.03-36

37 Processor Performance Microprocessor performance growth in perspective: Unmatched by any other industry [John Crawford, Intel Fellow, 1993] Doubling every 18 months ( ): total of 800X - Cars travel at 44,000 MPH; get 16,000 miles/gal. -Air travel: L.A. to N.Y. in 22 seconds (MACH 800) - Wheat yield: 80,000 bushels per acre Doubling every 24 months ( ): total of 9,000X - Cars travel at 600,000 MPH; get 150,000 miles/gal. -Air travel: L.A. to N.Y. in 2 seconds (MACH 9,000) - Wheat yield: 900,000 bushels per acre Exponential effect Fall 2003 Lec.03-37

38 Is Moore s Law Still Alive? YES! Transistors will double for the next few generations: 65nano, 45, 32, 22, 16~12nano Beyond that (10nano): transistors as we know them now don t work need new devices!! But FREQUENCY (speed) has stalled ~4GHz Power Consumption: Power Density in chips would reach the surface of the sun if we continued Single-core (processor) performance also stalled Architectural implication: shift to MULTICORES use all these transistors for parallel performance Fall 2003 Lec.03-38

39 Fundamental Equation for Processor Design The Iron Law of processor performance: Time Processor Performance = Program Instructions Cycles Time = X X Program Instruction Cycle (code size) (CPI) (cycle time) Architecture --> Implementation --> Realization Compiler Designer Processor Designer Chip Designer Fall 2003 Lec.03-39

40 Computer Architecture: Design Abstraction Application Compiler Operating System Microarchitecture I/O System Digital Design Circuit Design Instruction Set Architecture (ISA): Interface between software & hardware Fall 2003 Lec.03-40

41 Instruction Set Architecture (ISA) The HW/SW interface Software-visible hardware Specifies Program control flow Program data flow Loop: ldr R5, R3 add R2, R5 inc R3 dec R6 brz done bra loop Fall 2003 Lec.03-41

42 Microarchitecture Hardware organization or implementation The guts of the machine Implements the ISA Software-invisible Block-level grouping of transistors You are looking at a 100 million transistor chip Fall 2003 Lec.03-42

43 High-level View of a Computer Processor Memory Peripherals Processor Memory Peripherals SCSI (Disk) Control Ethernet Datapath KBD/Mouse Video Fall 2003 Lec.03-43

44 What s Inside a Computer Processor or CPU Memory subsystem Processor/device interface (I/O) How the processor talks to devices such as the network, disk drives, keyboard, etc. CPU Memory (DRAM and caches) Shared Bus Network Video Network (Ethernet) Fall 2003 Lec.03-44

45 What s Inside the Processor? CPU is partitioned into: Control Logic (control path) Datapath Datapath includes Register File ALU PC Memory Register Control path uses instructions to manage the datapath Register File ALU Program Counter (to fetch instructions) Current instruction Control Logic Memory Address Register (to fetch data) from memory Fall 2003 Lec.03-45

46 Whatis the ALU? Fall 2003 Lec.03-46

47 ALU What makes digital computers possible: BINARY NUMBERS + BINARY LOGIC need only a SWITCH to be implemented Fall 2003 Lec.03-47

48 Switches LOGIC Fall 2003 Lec.03-48

49 BASIC LOGIC Functions (GATES): AND & OR Fall 2003 Lec.03-49

50 XOR LOGIC Function Fall 2003 Lec.03-50

51 ARITHMETIC Fall 2003 Lec.03-51

52 BINARY ARITHMETIC Fall 2003 Lec.03-52

53 BINARY ARITHMETIC (cont.) Fall 2003 Lec.03-53

54 BINARY ARITHMETIC (cont.) Fall 2003 Lec.03-54

55 In Practice Fall 2003 Lec.03-55