Building and Programming complete MPSoCs in reconfigurable systems. Kees Vissers MPsoC 2007
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1 Building and Programming complete MPSoCs in reconfigurable systems Kees Vissers MPSoC 2007
2 Outline Control Processors and Operating Systems in FPGAs XUP, HDTV processing UC Berkeley Bee2 and programming Bee3 sneak peak Kees Vissers, slide 2
3 Control Processors Everywhere IBM/Sony Cell Processor (Media + computing) Nexperia PNX8526 (Digital TV) Intel IXP2800 (Network Processing) TI OMAP2430 (Cell Phone Handsets) Kees Vissers, slide 3
4 Control Processors in FPGAs Control Plane Processing User Interaction FPGA Configuration BIST Power Management Legacy Code Serial Console TCP/IP Memory Management Operating System DMA Libraries Flash Storage IIC 75% of processor users also use an Operating System Kees Vissers, slide 4
5 Key OS Properties An OS is more than hardware APIs. Basic properties: No user code can ever crash the operating system Framework for modularity and extensibility Fair sharing of resources for independent users Includes anything from simple locking to QOS guarantees These properties are crucial for debugging, and design-in-the-large. Kees Vissers, slide 5
6 ASSP Software Platform ASSP entry point Tools Application Software Application APIs Device Drivers OS ASSP Architecture Most processor/assp vendors implement new architectures relatively rarely. maybe every 1-3 years. New architectures typically require some porting and verification. Kees Vissers, slide 6
7 FPGA Software Platform Hardware FPGA entry point Tools Application Software Application APIs Device Drivers OS FPGA Design FPGA hardware Extra FPGA Work Domain and board specific additional System Architectures Challenge: Building a generic software platform for user-specified hardware Kees Vissers, slide 7
8 Demonstration Architecture DDR Memory plb_ethernet plb_ddr PPC405 opb_intc Filter Bus Macros Video Decoder Video Encoder Video Input Video Output plb_tft plb_opb_bridge Bus Macros opb_gpio Bus Macros IIC Control Compact FLASH opb_sysace opb_hwicap 2VP30 opb_uart16550 opb_socket Kees Vissers, slide 8
9 Achieving Decoupling Existing Libs (.o,.so) Existing Device Drivers Reference FPGA Design (.bit) Kees Vissers, slide Linux Kernel (.elf) Platform Xilinx Libs (.o,.so) Device Driver Interface Xilinx Device Drivers Board Patches Device Tree Booting (future) Build dependencies Dynamic Linking Loadable Modules FPGA Tools User Application (a.out) Device Driver Interface User Device Drivers (.ko) User FPGA Devices (.bit) User Design Interface dependencies Device Discovery + Linux Device Model
10 Demonstration Design Static Processor Subsystem Interfaces Video Filter + IIC LUTs (unoptimized) 24% of 2VP30 8% of 4VFX100 Kees Vissers, slide 10
11 Demonstration Boot generic processor subsystem with empty socket. Load static configuration from SystemACE. Load Linux Bootloader + Kernel from SystemACE. Decompress Linux Kernel and start executing. Load Root Filesystem over NFS. Load Kernel modules from Root Filesystem Load application-specific partial bitstream stored on NFS. Load meta-information Kernel loads appropriate device drivers. Enable Bus Macros HDTV video signal processing, in this demo a simple filter Kees Vissers, slide 11
12 Demonstration system Kees Vissers, slide 12
13 The FPGA system HDTV Split-screen Signal processing demo Connection to VGA monitor XUP board, with V2Pro 30, Linux software Ethernet with NFS file system, HDTV filter HDTV A/D and D/A Component video Connection to keyboard Kees Vissers, slide 13
14 UC Berkeley, Xilinx and Microsoft Research: BEE Special thanks to Chen Chang (UC Berkeley) and Chuck Thacker (Microsoft Research). Research of many excellent people. MPSoC 2007
15 Signal Processing Systems clock:sample 500MHz clock Memories Applications 1000:1 100:1 10:1 1:1 500Ks/s 5Ms/s 50Ms/s 500Ms/s 4-256KByte 4-256KByte 10KByte 1KByte control audio mobile video HDTV comms radar Control Processor Specialized Processors Direct Synthesis Tools Kees Vissers, slide 15
16 History of BEE Technology at UC Berkeley Kees Vissers, slide 16
17 14X17 inch 22 layer PCB BEE2 Compute Module BEE2 compute module Kees Vissers, slide 17
18 BEE2 IP Break-Out Board 2 Dual 1Gsps ADC board (ibob) IP Break-Out Board (ibob) Kees Vissers, slide 18
19 Compute Module Diagram 4GB DDR2 12.8GB/s (400DDR) IB4X/CX4 40Gbps Memory Controller 100BT Ethernet IB4X/CX4 20Gbps Memory Controller IB4X/CX4 40Gbps MGT FPGA Fabric FPGA Fabric MGT MGT DDR 5 FPGAs 2VP70FF1704 FPGA Fabric Memory Controller IB4X/CX4 40Gbps IB4X/CX4 40Gbps MGT FPGA Fabric 138 bits 300MHz DDR 41.4Gb/s FPGA Fabric MGT Memory Controller Memory Controller Kees Vissers, slide 19
20 The Programming Challenge Hardware complexity Lots of FPGA resources DDR G Ethernet GHz Analog I/O Embedded Processor Cores Software integrations OS: Linux, TinySH Device drivers User applications Multi-disciplined user base Signal processing MP emulation Compute acceleration Kees Vissers, slide 20
21 BEE Platform Studio (BPS) BEE Platform Studio v1.1 Simulink library support for system devices Full software integration with Linux OS support Simple GUI in Matlab/Simulink Require no knowledge of backend tool flow from end users Kees Vissers, slide 21
22 Case Study MPSoC 2007
23 JPL/SETI Galactic Plane Sky Survey Kees Vissers, slide 23
24 16-Antenna Correlator at Allen Telescope Array Artist s conception Hat Creek, California 350 Antenna Kees Vissers, slide 24
25 RAMP/ BEE3 Preview MPSoC 2007
26 Research Accelerator for Multiple Processors David Patterson (Berkeley, CO-PI), Arvind (MIT), Krste Asanovíc (MIT), Derek Chiou (Texas), James Hoe(CMU), Christos Kozyrakis(Stanford), Shih-Lien Lu (Intel), Mark Oskin (Washington), Jan Rabaey (Berkeley), and John Wawrzynek (Berkeley-PI) Kees Vissers, slide 26
27 RAMP Blue Prototype (1/07) 8 MicroBlaze cores / FPGA 8 BEE2 modules (32 user FPGAs) x 4 FPGAs/module = MHz Full star-connection between modules It works; runs NAS benchmarks CPUs are softcore MicroBlazes (32-bit Xilinx RISC architecture) Kees Vissers, slide 27
28 BEE3 Conceptual Overview 4 FPGA: Virtex-5 LX110T (FF1136) 16 DIMMs DDR2-667/800 Up to 16GB each 8 10GBase-CX4 interfaces EATX formfactor 2U chassis Kees Vissers, slide 28
29 JTAG 50 pin 2mm Header 12V 4-pin 12V 8-pin 24 pin ATX PWR 1.8V 4 GB DDR GB DDR GB DDR GB DDR2-667 BEE3 board and chassis PCI-Express 8x PCI-Express 8x PCI-Express 8x PCI-Express 8x 4 GB DDR GB DDR GB DDR GB DDR GB DDR GB DDR V 1.8V 2.5V 1.0V 1.8V 1.8V 4 GB DDR GB DDR2-667 QSH-DP-040 QSH-DP GB DDR GB DDR GB DDR GB DDR2-667 QSH-DP-040 QSH-DP-040 Kees Vissers, slide 29
30 Conclusion Several layers of technology are used in signal processing systems. Control processors and Operating Systems are essential integration technology. Modern FPGAs support implementations with several processing subsystems, including several processors. Strategic University cooperation with multiple independent partners is a modern research community. The Xilinx University Program is here for you: Kees Vissers, slide 30
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