Simulink-Hardware Flow

Transcription

1 5/2/22 EE26B: VLSI Signal Processing Simulink-Hardware Flow Prof. Dejan Marković Development Multiple design descriptions Algorithm (MATLAB or C) Fixed point description RTL (behavioral, structural) Test vectors for logic analysis Multiple engineering teams involved Unified MATLAB/Simulink description Path to hardware emulation / FPGA Path to optimized Closed-loop I/O verification 4.2

2 5/2/22 Simulink Design Framework Algorithm/flexibility evaluation Digital delay, area and energy estimates & effect of analog impairments Initial System Description (Floating point MATLAB/Simulink) Determine Flexibility Requirements Description with Hardware Constraints (Fixed point Simulink, FSM Control in Stateflow) Common test vectors, and hardware description of netlist and modules Real-time Emulation (FPGA Array) Automated Generation (Chip-in-a-day Flow) 4.3 Simulink Based Chip Design: Direct Mapping Directly map diagram into hardware since there is a one-for-one relationship for each of the blocks [] S reg Mult Mac X reg Mac2 Add, Sub, Shift Mult2 Result: An architecture that can be implemented rapidly [] W. R. Davis, et al., "A Design Environment for High Throughput, Low Power Dedicated Signal Processing Systems," IEEE J. Solid-State Circuits, vol. 37, no. 3, pp , Mar

3 5/2/22 Simulink Based Optimization and Verification Flow Custom tool : design optimization (WL, architecture) Custom tool 2: I/O components for logic verification Simulink [2] I/O lib Custom tool 2 RTL Hw lib Custom tool Speed Power Area [2] K. Kuusilinna, et al., "Real Time System-on-a-Chip Emulation," in Winning the SoC Revolution, by H. Chang, G. Martin, Kluwer Academic Publishers, 23. FPGA backend backend FPGA implements logic analysis 4.5 Energy-Area-Delay Optimization Energy-Area-Delay space for architecture comparison Time-mux, parallelism, pipelining, V DD scaling, sizing Energy [3] Block-level Datapath Optimal design Area intl, fold Optimal design V DD scaling Delay [3] D. Marković, A Power/Area Optimal Approach to VLSI Signal Processing, Ph.D. Thesis, University of California, Berkeley,

4 5/2/22 Automating the Design Process Improve design productivity Automate architecture generation to obtain multiple architectures for a given algorithm User determines solution for target application Convenient-to-use optimization framework Embedded in MATLAB/Simulink Result in synthesizable RTL form No extra tool to learn Drag-drop, push-button flow Faster turnaround time 4.7 Design Optimization Flow Based on reference E-D curve and system specs, fix degree of Pipelining (R), Time-multiplexing (N) or Parallelism (P) Generate synthesizable architectures/rtl in Simulink [4] Algorithm Simulink lib MATLAB Test vectors activity (α) Simulink Ref.Arch MDL Simulink Arch.Opt RTL Opt.arch Synthesis Final.GDS RTL α N, P, R Tech lib Synthesis Energy, Area, T clk Arch.Opt Parameters System specs Energy-T clk (V DD ) Datapath simulation [4] R. Nanda, DSP Architecture Optimization in MATLAB/Simulink Environment, M.S. Thesis, University of California, Los Angeles,

5 Hardware Cost Reference Direct-mapping Functional Architecture Folding N = 2 Equivalence Architecture 2 Folding N = 4 5/2/22 Simulink & Data-Flow Graphs Algorithm Transformed Design Data-Flow Graph Simulink Architectural Transforms Integer Linear Programming Verification RTL Synthesis Data-Flow Graph Reference Design GUI Interface 4.9 From Simulink to Optimized Hardware Direct mapped DFG Scheduler Architecture Solutions Hardware (Simulink) (C++ / MOSEK) (Simulink/SynDSP) (FPGA/) + D + Initial DFG D D a 2D 2D b + + c d Resulting Simulink/SynDSP Architectures ILP Scheduling & Bellman-Ford Retiming: optimal + reduced CPU time 4. 5

6 5/2/22 Tool Demo (Source Code Available) [5] [5] See the book website for tool download. GUI based demo of filter structures Software tested using MATLAB 27b and SynDSP 3.6 The tool works only for the following Simulink models SynDSP models Single input, single output models Models that use adders and multipliers, no control structures Usage instructions Unzip the the.rar files all into a single directory (e.g. E:\Tool) Start MATLAB Make E:\Tool your home directory The folder E:\Tool\models has all the relevant SynDSP models On the command line type: ArchTran_GUI Check the readme file in E:\Tool\docs for instructions Examples shown in the next few slides 4. Using GUI for Transformation Direct mapped DFG (Simulink/SynDSP model) Use GUI to open Simulink model from drop down menu 2 nd order IIR 4.2 6

7 5/2/22 Data-Flow Graph Extraction Select design components (adds, mults etc.), set pipeline depth Extract model, outputs hardware and connectivity info Extract Model 4.3 Model Extraction Output v 2 v 4 v v 3 v 5 v 7 v 6 v 8 A = e e 2 e 3 e 4 e 5 e 6 e 7 e 8 e 9 e e v v 2 v 3 v 4 v 5 v 6 v 7 v 8 w = [2 2 ] T du = [ ] T Loop bound =

8 5/2/22 Time Multiplexing from GUI Set architecture optimization parameter (e.g. N = 2) Schedule design Time-multiplex option (N = 2) Generate Time-mux arch. N = Transformed Simulink Architecture Automatically generated scheduled architecture pops up Control Muxes Multiplier Coefficients Down-sample by N (=2) Output latched every N cycles Pipelined Multiplier Controller generates select signals for muxes Pipelined Adder 4.6 8

9 5/2/22 Scheduled Model Output Scheduling generated results Transformed architecture in Simulink Schedule table with information on operation execution time Normalized area report Schedule Table A A 2 M M 2 M 3 M 4 Cycle v v 3 v 5 v 6 v 7 v 8 Cycle 2 v 2 v 4 x x x x Scheduled Model Area Report Adders (A i ) : 9 Multipliers (M i ) : 8 Pipeline registers : 383 Registers : 383 Control muxes : Parallel Designs from GUI Set architecture optimization parameter (e.g. P = 2) Parallel design Parallel option (P = 2) Generate Parallel arch. P =

10 5/2/22 Transformed Simulink Architecture Automatically generated scheduled architecture pops up P = 2 parallel Input streams P = 2 parallel Output streams Parallel Adder core Parallel Multiplier core 4.9 Range of Architecture Tuning Parameters Energy V DD scaling Latency max fixed V DD V DD max P, R N V DD * P, R Pipeline: R Parallel: P Time mux: N N Throughput max V DD min [6] T clk [6] R. Nanda, C.-H. Yang, and D. Marković, "DSP Architecture Optimization in MATLAB/Simulink Environment," in Proc. Int. Symp. VLSI Circuits, June 28, pp

11 Area Area 5/2/22 Energy-Area-Performance Map Each point on the surface is an optimal architecture automatically generated in Simulink after modified ILP scheduling and retiming Valid architectures Direct-mapping (reference) Constraints System designer can choose from many feasible (optimal) solutions It is not just about functionality, but how good a solution is, and how many alternatives exist 4.2 An Optimization Result RTL, switching activity Simulink Valid architectures Direct-mapping (reference) Synthesis Time-mux Constraints Gate sizing Retiming.8.6 Carry save Pipelining Parallelism Fine pipe IP cores E-A-P Space Energy-area-performance estimate 4.22

12 5/2/22 Architecture Tuning Result: MDL Lower Area N = 2 Time-multiplex input mux N = 2 multiplier core In N = 2 adder core controller out D D D Reference Out input de-mux 4-way adder core Higher Throughput or Lower Energy P = 4 Parallel 4-way multiplier core output mux 4.23 Pipelining Strategy Library blocks / macros V DD ref Cycle Time Pipeline logic scaling FO4 inv simulation Speed Power Area mult V DD scaling gate sizing T V DD opt [7] T V DD ref add V DD ref Latency Energy [7] D. Marković, B. Nikolić, and R.W. Brodersen, "Power and Area Efficient VLSI Architectures for Communication Signal Processing," in Proc. Int. Conf. on Communications, June 26, vol. 7, pp

13 Energy (pj) [log scale] Energy Efficiency (GOPS/mW) 5/2/22 Optimization Results: 6-tap FIR Filter Design variables: CSA, fine R (f-r), V DD (.32 V to V), pipelining (9 nm CMOS) 395 M 56 M 623 M 35 M 3 M 395 M V DD Ref. no CSA Ref. CSA 66 M Ref. CSA f-r Pip + R Pip + R + f-r M = MS/s Area (μm 2 ) x tap FIR: Architecture Parallelism (Unfolding) Parallelism improves throughput or energy efficiency About x range in efficiency from V DD scaling (.32 V V) (9 nm CMOS).47V.39V.36V.5V 3 Ref. 2 P = 2.7V.5V P = 4.57V V P = 5.73V P = 8.9V P = x 5 Area (μm 2 )

14 5/2/22 Example #2: UWB Digital Baseband Starting point: direct-mapped architecture Optimization focused on the 64-tap GS/s filter 8% of power 4.27 Architecture Exploration: MDL Description Use MATLAB add_line >> add_line('connecting', command for Counter/', block connectivity 'Register/') functional block >> add_line( connecting, Counter/, Register/ ) 4 levels of Parallelism >> add_line('connecting', 'Register/', basic block connectivity 2 levels of Parallelism 6 levels of Parallelism 6 levels of parallelism 4 levels of parallelism 4 levels of Parallelism >> add_line('connecting', 2 levels of 'Constant/', Parallelism 6 levels of

15 Voltage (V) Power (mw) 5/2/22 Minimizing Overall Power and Area V P P2 P4 P8 P V DD >.4 V mm 2.4mm P P2 P4 P6 P8 P8 versus P4 P8 has 5% lower power but also 38% larger area Throughput (GS/s) = 333 MHz (.6 = 2 MHz) Solution: parallel-4 architecture (V DD opt =.43 V) 64-tap filter design: Effective GS/s 2 43 V Parallel-4 filter 4.29 FPGA Based Chip Verification MATLAB Simulink model emulation FPGA board board Real-time hardware verification 4.3 5

16 5/2/22 Hardware Test Bench Support Approach: use Simulink test bench (TB) for verification Develop custom interface blocks (I/O) Place I/O and RTL into TB model [8] + + = I/O Simulink implicitly provides the test bench TB I/O TB Additional requirements from the FPGA test platform As general purpose as possible (large memories, fast I/O) Use embedded CPU to provide high-level interface to FPGA [8] D. Marković et al., " Design and Verification in an FPGA Environment," in Proc. Custom Integrated Circuits Conf., Sep. 27, pp Design Environment: Xilinx System Generator Custom interface blocks Regs, FIFOs, BRAMs GPIO ports Analog subsystems Debugging [9] -click compile [9] C. Chang, Design and Applications of a Reconfigurable Computing System for High Performance Digital Signal Processing, Ph.D. Thesis, University of California, Berkeley,

17 5/2/22 Simulink Test Model -c- -c- ADDR IN OUT WE BRAM_IN in rst Simulink hardware model out ADDR IN OUT WE BRAM_FPGA logic -c- gpio gpio gpio in rst clk board out gpio ADDR IN OUT WE BRAM_ -c- reset sim_rst reg software_reg logic 4.33 Example: SVD Test Model Emulation-based I/O test

18 5/2/22 FPGA Based Test Setup Test bench model on the FPGA board Block read / write operation Custom read_xps, write_xps commands Client PC FPGA board board PC to FPGA interface UART RS232 (slow, limited applicability) Ethernet (with an FPGA operating system support) FPGA- interface GPIO (electrically limited to ~3 Mbps) High-speed ZDOK+ differential-line link (~5 Gbps, f clk limited) 4.35 Low Data-Rate Test Setup board GPIO IBOB FPGA board IBOB: Interconnect Break-Out Board FPGA board features Virtex-II Pro (FPGA, PowerPC45) 2x 8Mb (36b) SRAMs (~25MHz) 2x CX4 Gb high-speed serial 2x Z-DOK+ high-speed differential GPIO (8 diff pairs) 8x LCMOS/LVTTL GPIO PC interface RS232 UART to PPC Custom scripts read_xps/write_xps Client PC RS232 ~kb/s FPGA board GPIO ~3 Mb/s board Limitations: Speed of RS232 (~kb/s) & GPIO interface (~3 MHz)

19 5/2/22 Medium Data-Rate Test Setup IBOB v.3 FPGA board Virtex-II based FPGA board IBOB v.3 [ FPGA- interface ZDOK+ high-speed differential interface Allows testing up to ~25MHz (limited by the FPGA clock) PC interface RS232 UART Client PC RS232 ~Kb/s FPGA board ZDOK+ ~5 Mb/s board Limitations: Speed of RS232 interface (~kb/s) & FPGA BRAM capacity 4.37 High Data-Rate Test Setup ROACH FPGA board ZDOK+ ROACH: Reconfigurable Open Architecture Compute Hardware FPGA board features Virtex 5 FPGA, External PPC44 x DDR2 DIMM 2x 72Mbit (8b) QDR SRAMs (~35MHz) 4x CX4, 2x ZDOK+ (8 diff pairs) External PPC provides much faster interface to FPGA resources (GbE) PC to FPGA interface OS (BORPH) hosted on the FPGA BORPH: Berkeley Operating system for ReProgrammable Hardware Client PC Ethernet BORPH FPGA board ZDOK+ ~5 Mb/s board

20 LVDS I/O 5/2/22 BORPH Operating System [] About BORPH Linux kernel modification for hardware abstraction It runs on embedded CPU connected to FPGA Hardware process Programming an FPGA running Linux executable Some FPGA resources are accessible in Linux process memory space BORPH makes FPGA board look like a Linux workstation It is used on BEE2, ROACH Limited version on IBOB w/ expansion board [] H. So, A. Tkachenko, and R.W. Brodersen, "A Unified Hardware/Software Runtime Environment for FPGA-Based Reconfigurable Computers using BORPH," in Proc. Int. Conf. Hardware/Software Codesign and System Synthesis, 28, pp Example: Multi-Rate Digital Filter Testing Requirements High Tx clock rate (45 MHz target) Beyond practical limits of IBOB s V2P Long test vectors (~4 Mb) Asynchronous clock domains for Tx and Rx Client PC GbE PowerPC ROACH based test setup BORPH FPGA Test Board BRAM Test Board QDR SRAM FPGA 4.4 2

21 5/2/22 Asynchronous Clock Domains Merged separate designs for test vector and readback datapaths XSG has very limited capability for expressing multiple clocks CE toggling to express multiple clocks Further restricted by bee_xps tool automation Assumes single clock design (though many different clocks available) Fixed 6 MHz Rx MHz Tx 4.4 Results and Limitations Results Test up to 35 MHz w/ loadable vectors in QDR; up to 34 MHz with pre-compiled vectors in ROMs 55 db 2 MHz bandwidth Limitations DDR output FF critical 34 MHz (clock out) QDR SRAM bus interface critical 35 MHz Output clock jitter? LVDS receivers usually only 4-5 Mbps OK for data, not good for faster clocks Get LVDS I/O cells?

22 5/2/22 FPGA Based Verification: Summary The trend is towards fully embedding logic analysis on FPGA, including OS support for remote access Simulation Emulation I/O Test I/O TB Simulink Simulink Simulink Pure SW Simulation HDL Simulink Simulink FPGA HIL tools Simulink Simulink ModelSim co-simulation Hardware-in-the-loop simulation FPGA FPGA FPGA Pure FPGA emulation FPGA & FPGA & FPGA FPGA Custom SW FPGA I/O TB Test vectors outside FPGA Test vectors inside FPGA 4.43 Further Extensions Design recommendations Send source-synchronous clock with returned data Send synchronization information with returned data Vector warning or frame start, data valid KATCP: communication protocol interfacing to BORPH Can be implemented over TCP telnet connection Libraries and clients for C, Python KATCP MATLAB client (replaces read_xps, write_xps) Can program FPGA from directly from MATLAB no more JTAG cable! Provides byte-level read/write granularity Increases speed from ~Kb/s to ~Mb/s (Room for improvement; currently high protocol overhead) Towards streaming Transition to TCP/IP-based protocols facilitates streaming Ethernet streaming w/o going through shared memory

23 5/2/22 Summary MATLAB/Simulink is an environment for algorithm modeling and optimized hardware implementation Bit-true cycle-accurate model can be used for functional verification and mapping to FPGA/ hardware The environment is suited for automated architecture exploration using high-level scheduling and retiming Test vectors used in algorithm development can also be used for functional verification of fabricated Enhancements to traditional FPGA-based verification Operating system can be hosted on an FPGA for remote access and software-like execution of hardware processes Test vectors can be hosted on FPGA for real-time data streaming (for data-limited or high-performance applications) 4.45 ILP Models for Scheduling and Retiming 23

24 Integer Linear Programming Bellman-Ford 5/2/22 Basic ILP Model for Scheduling and Retiming Minimize Subject to p c M p V xij u N x ij j w f = N w d + A p + N A r p M p M p : # of PEs of type p Resource constraint Each node is scheduled once Precedence constraints Scheduling Retiming Case : r = (scheduling only, no retiming): sub optimal Case 2: r (scheduling with retiming): exponential run time 4.47 Time-Efficient ILP Model for Scheduling & Retiming Minimize Subject to p c M p V xij u N x ij j Simulink Arch.Opt B ( w + ( A p d ) / N ) p M p M p : # of PEs of type p Resource constraint Each node is scheduled once Each node is scheduled once Loop constraints to ensure feasibility of retiming w f = N w d + A p + N A r A r ( w + ( A p d ) / N ) Precedence constraints Retiming inequalities solved by Bellman-Ford (B-F) Algorithm Feasible CPU runtime (polynomial complexity of B-F algorithm)

25 5/2/22 Example: Wave Digital Filter Area (Norm.) Power (Norm.) Goal: architecture optimization in area-power-performance space..8 scheduling scheduling + retiming Folding Factor..8.6 scheduling.4.2 scheduling + retiming Folding Factor Architecture ILP scheduling: Method : Scheduling Method 2: Scheduling + retiming Method 3: Sched. + Bellman Ford Method 3 (Sch. + B-F retiming): Power & Area optimal Reduced CPU runtime Method 3 yields optimal solution with feasible CPU runtime CPU Runtime (sec) Optimal Suboptimal No solution Method 2 (*) Method 3 Method Folding Factor (*) reported CPU runtime for Method 2 is very optimistic (bounded retiming variables) 4.49 References (/2) W.R. Davis et al., "A Design Environment for High Throughput, Low Power Dedicated Signal Processing Systems," IEEE J. Solid-State Circuits, vol. 37, no. 3, pp , Mar. 22. K. Kuusilinna, et al., "Real Time System-on-a-Chip Emulation," in Winning the SoC Revolution, by H. Chang, G. Martin, Kluwer Academic Publishers, 23. D. Marković, A Power/Area Optimal Approach to VLSI Signal Processing, Ph.D. Thesis, University of California, Berkeley, 26. R. Nanda, DSP Architecture Optimization in Matlab/Simulink Environment, M.S. Thesis, University of California, Los Angeles, 28. R. Nanda, C.-H. Yang, and D. Marković, "DSP Architecture Optimization in Matlab/Simulink Environment," in Proc. Int. Symp. VLSI Circuits, June 28, pp

26 5/2/22 References (2/2) D. Marković, B. Nikolić, and R.W. Brodersen, "Power and Area Efficient VLSI Architectures for Communication Signal Processing," in Proc. Int. Conf. Communications, June 26, vol. 7, pp D. Marković, et al., " Design and Verification in an FPGA Environment," in Proc. Custom Integrated Circuits Conf., Sept. 27, pp C. Chang, Design and Applications of a Reconfigurable Computing System for High Performance Digital Signal Processing, Ph.D. Thesis, University of California, Berkeley, 25. H. So, A. Tkachenko, and R.W. Brodersen, "A Unified Hardware/Software Runtime Environment for FPGA-Based Reconfigurable Computers using BORPH," in Proc. Int. Conf. Hardware/Software Codesign and System Synthesis, 28, pp