A Software Development Toolset for Multi-Core Processors. Yuichi Nakamura System IP Core Research Labs. NEC Corp.

Transcription

1 A Software Development Toolset for Multi-Core Processors Yuichi Nakamura System IP Core Research Labs. NEC Corp.

2 Motivations Embedded Systems: Performance enhancement by multi-core systems CPU0 CPU1 Multi-core Systems need the parallelization of software How to develop parallelized software on multi-core Mobile Communication Consumer Car Picochip Tilera ClearSpeed Niagara Power, etc. Realistic parallelization Keeping hard real time constraints Detail verification and debug # of Cores Frequency increasing # of cores increasing Challenges: Enhancement of the productivity of software development for multi-core systems with high performance and high reliability.

3 Our Approaches From an industry s view, 3 approaches/tools are proposed 1.Parallelization from models Support parallelization from Simulink models Simulink Model analysis Simulink Task Parallelization in short time Sequen ceal C C-code analysis Flattening, loop unrolling Optimization, grain control Palallel code generation Task Code Generation Comm 2.Task placement with constraints Dependency Analysis Placement Result Core #0 Core #1 Hard deadline Task Placement with hard deadline Hard Deadline Original task set Task Placement Core #0 Core #1 3.Debugging SW by using FPGA CPU CPU CPU Multi-core real model Modeling FPGA Emulator C Programming Environment And Debugger Page 3

4 1-1.Parallel C Code Generation from Simulink Models A tool to generate parallel C code from Simulink models The tool enables users to develop parallel software without using parallel APIs explicitly. Parallelization Method 1. treat each of leaf blocks in models as a task. 2. signal completion of processing of tasks to descendant tasks with synchronized messages. Simulink models Preliminary experimental result (audio equalizer, 100% before parallelization) 2-core PC 60% 4-core PC 38% * Number of tasks in parallelized software 57 task communication To extract structural parallelism expressed in models through removing block hierarchy and loop structures. To optimize task granularity for small communication overhead. Simulink models Model analysis Simulink Optimization Sequential C code Code analysis Building internal models Code generation Parallelized C code Parallel code generation tool

5 1-2. How to Introduce Parallelization from Simulink Models Sound effect process: Modification of frequency and amplitude 1024sample/frame/channel Task Task dependency graph # of tasks = 57 Pipeline parallelization Sound effect processing model # of blocks = 252

6 1-3. Case Studies Parallelization from Simulink Model Lane departure warning Audio: Sound Effect MATLAB :Video and Image processing toolbox : vipldw_all.mdl professional-simulink-audio-equalizer Model # of blocks # of tasks Execution time compared with sequential implementation Windows Xeon Audio % 26% Lane % 39% esol et-kernel NaviEngine Page 6

7 2-1.Multi-Core Task Mapping for Hard Real- Systems Multi-Core Task Mapping Tool: STF (Smart Task Fitter) Generates static mapping of embedded software on multi-core CPUs Satisfying deadlines, execution order and other real-time restrictions Can generate mapping of hundreds of tasks within few seconds UseCase1: Easy migration of multi UseCase2: Integration of task systems from single-core to discrete systems onto multi-core multi-core STF generates task mapping automatically that satisfies execution order and real-time restrictions. Original Task Set Task Mapping Core 0 Deadline Core 1 Core 0 Core 1 Dependency Analysis Result Deadline Deadline Deadline Deadline Core 0 Core 1 Deadline Integration example: Three discrete real-time systems are integrated onto a dual-core CPU by using automatically mapping function of STF. Each task keeps execution order and deadline. Mapping Algorithm: 1) Task allocation with minimum response time 2) Reallocation by min-cut based placement

8 2-2. Flow of Task Allocation with Minimum Response Idol time Idol time is generated by dependency Core #0 Core #1 A B C D E F Response time based allocation Core #0 A D E Idol time reduction Core #1 B C F Minimize total response time of all tasks Core #0 A Short period task D E F Each task can be terminated in a short time Core #1 B C Efficiency

9 2-3. Min-cut based Re-allocation Minimize total dependency Core #0 Core #1 Cut = Dependency Target: Minimize the dependency = Minimum cut of graph Introducing LSI placement method Exchange Task 2 and Task 3 Score Task Table Scheduling Results Tool GUI Mincut

10 3-1. Software debugging environment by FPGA emulator Conventional software development environments 1. Instruction set simulator Advantage: Rich observability and controllability Disadvantage: Slow and less accuracy 2. Real Chip Advantage: Fast and accurate Disadvantage: Less observability and controllability Our proposed system Multi-core System CPU CPU CPU CPU Modeling Clock accurate communication TCP/IP Remote Debugging Page 10 C language based with various break point setting (clock/instruction), rich observability and rich controllability

11 3-2. Clock Accurate FPGA Emulator Debugging System FPGA: Processors models, bus, IROM, RAM, break and step control PC: RAM view, ROM view, program scroll, bus monitor, and control terminal Debugging fabric: Instruction step, clock step, break point setting on register, memory view and C code Clock Processor Processor Break and Step Clock Control IROM RAM IROM RAM PCI or PCIe Control Observe Simultaneous This system can handle clock and instruction level break setting. >> 20MHz

12 3-3. Case Study: Environment for Multi-core System with Shared Memory CPU#0 C value view CPU#1 Registers view Current Status C Program Scroll Assembler Scroll Update sign Shared memory view Page 12 Step and clock control Control View

13 Demo Videos Parallelization from Simulink Models Lane departure warning Compare with before parallelization and after parallelization Software debugging environment by FPGA emulator Dual core(2 OpenRISC Processor) model Each processor has local memory Shared memory C language interface Break points and step running DMA from memory for CPU1 to memory for CPU2

14 Conclusion Complicated software development for embedded multi-core systems Proposed 3 method 1. Parallel C Code Generation from Simulink Models 2. Multi-Core Task Mapping for Hard Real- Systems 3. Software development environment by FPGA emulator Case Studies indicates the effectiveness of the proposed tools They help efficient development for software design for multi-core systems Next target Analysis the performance and quality of software on multi-core processor