The Design and Applications of BEE2: A High End Reconfigurable Computing system
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1 The Design and Applications of BEE2: A High End Reconfigurable Computing system Chen Chang, John Wawrzynek, Bob Brodersen, EECS, University of California at Berkeley
2 High-End Reconfigurable Computer (HERC) A computer with supercomputer-like performance, based solely on FPGAs and/or other reconfigurable devices as the processing elements. The inherent fine-grain flexibility of the FPGAs allow all datapaths, control, memory ports, and communication channels to be customized on a per-application basis and parallelism to be exploited at all levels. BEE2 development is underway: demonstrate of the concept; It will motivate engagement of application domain experts; Motivate creative thinking in software/programming tools; Be the first in a series of machines; It is a joint project with Xilinx using their 130nm devices. Based on concepts demonstrated in BEE2 prototype, 1 petaops (10 15 ) in 1 cubic meter attainable within 3 years. August 16th, 2005 EECS, UC Berkeley 2
3 Applications Areas of Interest High-performance DSP SETI Spectroscopy, ATA / SKA Image Formation Hyper-spectral Image Processing (DARPA) Scientific computation and simulation E & M simulation for antenna design (BWRC) Fusion simulation (UW) Communication systems development Platform Algorithms for SDR and Cognitive radio Large wireless Ad-Hoc sensor networks In-the-loop emulation of SOCs and Reconfigurable Architectures Bioinformatics BLAST (Basic Local Alignment Search Tool) biosequence alignment Molecular Dynamics (Drug discovery) System design acceleration Full Chip Transistor-Level Circuit Simulation (Xilinx) RAMP (Research Accelerator for MultiProcessing) August 16th, 2005 EECS, UC Berkeley 3
4 Radio Astronomy (1MHz~500GHz) Radio jets Image courtesy of NRAO/AUI Colliding black holes August 16th, 2005 EECS, UC Berkeley 4
5 Allen Telescope Array (CA, USA) Artist s conception Hat Creek, California 350 Antenna August 16th, 2005 EECS, UC Berkeley 5
6 Allen Telescope Array (cont.) 0.5~11GHz RF August 16th, 2005 EECS, UC Berkeley 6
7 Large-N, Small-D Concept Use lots of small diameter antennas to achieve large aggregate collecting area Benefits Extremely high quality coverage Very wide range of baseline lengths Flexible usage model, multi-user, multi-subarrays Reliability through redundancy Economy of scale August 16th, 2005 EECS, UC Berkeley 7
8 Telescope cost for fixed collect area Cost ($) Compute Hardware Cost Dominate Antenna Steel Cost Dominate Moore s Law Antenna diameter August 16th, 2005 EECS, UC Berkeley 8
9 Problems with existing approach All specialized instrument design Separate PCB for each subsystem, dedicated functionality Custom interconnect, backplane, and memory interface Fully global synchronous I/O and processing Clock distribution, power consumption, and voltage regulation Each instrument design cycle is 5 years!!! Instrument upgrade takes the similar effort as designing a new product August 16th, 2005 EECS, UC Berkeley 9
10 Why not use Microprocessor/DSP clusters? Multi-processor programming is extremely hard, especially for real-time applications Limited I/O capability, high power consumption, low computational density ASIC? Lack of flexibility Long design cycles FPGA? Sure! August 16th, 2005 EECS, UC Berkeley 10
11 Moore s Law in FPGA world MOPS Xilinx FPGA Intel Xeon Processor 100X higher performance 100X more efficient than microprocessors! /15/ /28/1995 3/11/1997 7/24/ /6/1999 4/19/2001 9/1/2002 1/14/2004 5/28/ /10/2006 Release Date FPGA performance doubles every 12 month! MOPS/MHz/Million Transistors /15/ /28/1995 3/11/1997 7/24/ /6/1999 4/19/2001 9/1/2002 1/14/2004 5/28/ /10/ Xilinx FPGA Intel Xeon Processor Release Date August 16th, 2005 EECS, UC Berkeley 11
12 Energy Efficiency (MOPS/mW) Based published results at ISSCC conferences and our measured results (FPGA). Energy (Power) Efficiency MOPS/mW Microprocessors ASIC FPGA General Purpose DSP 2 orders of Magnitude! Chip Number Specialized circuits use less energy per operation. Inherent computation density means devices can run at lower speed consuming less power. Reduced power consumption is a priority for FPGA vendors. August 16th, 2005 EECS, UC Berkeley 12
13 BEE2 system design philosophy Compute-by-the-yard Modular computing resource Flexible interconnect architecture On-demand reconfiguration of computing resources Economy-of-scale Ride the semiconductor industry Moore s Law curve All COTS components, no specialized hardware Survival of application software using technology independent design flow August 16th, 2005 EECS, UC Berkeley 13
14 BEE2 Compute Module 14X17 inch 22 layer PCB August 16th, 2005 EECS, UC Berkeley 14
15 Basic Computing Element Single Xilinx Virtex 2 Pro 70 FPGA ~70K logic cells (35K slices) 2 PowerPC405 cores 324 dedicated multipliers (18-bit) 5.7 Mbit SRAM on-chip 20X Gbit/s duplex serial communication links (MGTs) DDR2-400 DDR FPGA DDR2-400 DDR physical DDR2-400 banks Each banks has 72 data bits with ECC Independently addressed with 32 banks total Up to 12.8 GBps memory bandwidth, with maximum 4 GB capacity August 16th, 2005 EECS, UC Berkeley 15
16 Compute Module Diagram 4GB DDR2 12.8GB/s (400DDR) IB4X/CX4 40Gbps Memory Controller 100BT Ethernet IB4X/CX4 20Gbps Memory Controller IB4X/CX4 40Gbps MGT FPGA Fabric FPGA Fabric MGT MGT DDR 5 FPGAs 2VP70FF1704 FPGA Fabric Memory Controller IB4X/CX4 40Gbps IB4X/CX4 40Gbps MGT FPGA Fabric 138 bits 300MHz DDR 41.4Gb/s FPGA Fabric MGT Memory Controller Memory Controller August 16th, 2005 EECS, UC Berkeley 16
17 Inter-Module Connections Global Communication Tree 4X Compute Module As Tree node 4X Compute module N-modules Compute module NAS 4X 4X Stream Packets 10G Ethernet Switch Admin, UI, NFS 100 Base-T Ethernet Switch August 16th, 2005 EECS, UC Berkeley 17
18 19 Rack Cabin Capacity 40 compute nodes in 5 chassis (8U) per rack ~40TeraOPS, ~1.5TeraFLOPS 150 Watt AC/DC power supply to each blade ~6 Kwatt power consumption Hardware cost: ~ $500K August 16th, 2005 EECS, UC Berkeley 18
19 Programming Model : Discrete Time Block Diagram with FSM Block Diagrams: Control Data Path User Macros S1 S2 DI DO A R/W Matlab/Simulink: Functional simulation, Hardware Emulation StateFlow, Matlab HDL CoreGen Module Compiler Black Boxes Xilinx system generator library with BEE2 hardware specific hardware abstractions User assisted portioning with automatic system level routing August 16th, 2005 EECS, UC Berkeley 19
20 BEE2 hardware abstractions Data flow operators Data type: fix-point Math operators: +/-, *, /, &,, xor, ~, >, =, <, srl, sll, sra Control operators: demux/switch, mux/merge Memory On-chip SRAM/Registers: shift register, RAM, ROM Off-chip : stream RAM Communication and I/O Static links: stream I/O Dynamic links: Remote DMA Synchronization Time stamp August 16th, 2005 EECS, UC Berkeley 20
21 Tool flow Xilinx ISE 6.3i SP3 System Generator 6.3i Synplify Pro Matlab 7 / Simulink 6 BEE_ISE Tool flow wrapper in Matlab GUI Automate CAD flow parameter optimizations and hardware system specific parameters Require minimal knowledge of the tools flow from the end users August 16th, 2005 EECS, UC Berkeley 21
22 Radio Astronomy Applications Focused here first, because 8 Gbps Experienced with DSP-like problems App works well with our existing programming tools PFB 8K ch 64K tap CT 8K,32K FFT 32K Power Spectrum Threshold PFB Power CT FFT 8K ch Spectrum 8K,32K 32K BPF 64K tap Threshold 16 Gbps 4 ch Report 128 tap PFB 8K ch 64K tap PFB 8K ch 64K tap CT 8K,32K CT 8K,32K FFT 32K FFT 32K Power Spectrum Threshold Power Spectrum Threshold SETI Spectrometer Target: 0.7Hz channels over 800MHz 1 billion Channel realtime spectrometer Results: One BEE2 module meets target and yields 333GOPS (16-bit mults, 32-bit adds), at 150Watts (similar to desk-top computer) >100x peak throughput of current Pentium-4 system on integer performance, & >100x better throughput per energy. August 16th, 2005 EECS, UC Berkeley 22
23 Unified Radio Astronomy DSP processing architecture Antenna array size Notes: 100MHz band from each antenna Baselines (# correlations) BEE2 modules (PFB) Dual polarization BEE2 modules (XMAC) BEE2 modules (Imager) x512 pixels image Digitizers frequency channels per pixel Ethernet switches estimated $ total(k) $ $ 2, $ 5, image dump / second August 16th, 2005 EECS, UC Berkeley 23
24 4 antenna correlator designs August 16th, 2005 EECS, UC Berkeley 24
25 Benchmark applications 1024 channel dual polarization Polyphase Filter Bank (PFB) with 8K tap filter coefficients 1024 channel 2 input dual polarization cross correlator (XMAC) 256 million channel PFB based spectrometer All optimizations were performed on the Simulink level, and tool flow options set from BEE_ISE2, no HDL tweaking August 16th, 2005 EECS, UC Berkeley 25
26 PFB1K (4 instances in 1 FPGA) Resource Utilization: Flip Flops: 45,856 (69%) LUTs: 14,816 (22%) Slices: 25,380 (76%) Block RAMs: 216 (65%) MULT18X18s: 256 (78%) Max clock rate: 252.8MHz (2VP70-7) 72GMAC/s per Power consumption: 26.5W Tool Flow run-time/mem Matlab/XSG: 10min/303MB Synth: ~2 min/250mb XFLOW: 84 min/1gb August 16th, 2005 EECS, UC Berkeley 26
27 XMAC (5 instances in 1 FPGA) Resource Utilization: Flip Flops: 45,765 (69%) LUTs: 33,420 (50%) Slices: 24,915 (75%) Block RAMs: 0 (0%) MULT18X18s: 0 (0%) Max clock rate: 227.8MHz (2VP70-7) 200 GMAC/s per 200MHz Power consumption: 6.65W Tool Flow run-time/mem Matlab/XSG: 2min/212MB Synth: 2 min/178mb XFLOW: 137 min/1.2gb August 16th, 2005 EECS, UC Berkeley 27
28 256M channel spectrometer 8K PFB (64K tap) + 32K pt FFT Resource Utilization: Flip Flops: 30,964 (46%) LUTs: 13,326 (20%) Slices: 18,958 (57%) Block RAMs: 328 (100%) MULT18X18s: 128 (39%) Max Clock Rate: MHz (2VP70-7) 28.8 GMAC/s per Power Consumption: 13W Tool Flow run-time/mem Matlab/XSG: 32min/1.2GB Synth: ~2 min/380mb XFLOW: 64 min/890mb August 16th, 2005 EECS, UC Berkeley 28
29 Xilinx FPGA vs. TI DSPs Xilinx Virtex 2 Pro FPGA 2VP70 Technology: 130nm CMOS Clock rate: 200~250MHz Unit Cost: $1500~2400 2VP20 Technology: 130nm CMOS Clock rate: 200~250MHz Unit Cost: $366 TI C640 DSP C6415T-1G Technology: 90nm CMOS Clock rate: 1GHz Unit Cost: $270 C6415-7E Technology: 130nm CMOS Clock rate: 720MHz Unit Cost: $135 August 16th, 2005 EECS, UC Berkeley 29
30 Comparison with DSP Chips Spectrometer & polyphase filter bank (PFB): 16 mult, 32bit acc, Correllator: 4bit mult, 24bit acc. Cost based on street price. Assume peak numbers for DSPs, mapped for FPGAs. TI DSPs: C6415-7E, 130nm (720MHz) C6415T-1G, 90nm (1GHz) FPGAs 130nm, freq MHz. Metrics include chips only (not system) Performance Energy Efficiency Cost-Performance August 16th, 2005 EECS, UC Berkeley 30
31 Cost Effective Solutions for PFB XC2VP20-7 C6415-7E 2X X 10 3X 0 GMAC/s GMAC/s/watt MMAC/s/$ August 16th, 2005 EECS, UC Berkeley 31
32 Project status 10 node system manufacturing (8/2005) Demonstration applications: NASA DSN 128M channel spectrometer (7/2005) VLBI 1GHz spectrum data recorder (9/2005) 8 antenna 200MHz dual polarization correlator (9/2005) August 16th, 2005 EECS, UC Berkeley 32
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