DRAM with Boosted 3T Gain Cell, PVT-tracking Read Reference Bias

Transcription

1 ASub-0 Sub-0.9V Logic-compatible Embedded DRAM with Boosted 3T Gain Cell, Regulated Bit-line Write Scheme and PVT-tracking Read Reference Bias Ki Chul Chun, Pulkit Jain, Jung Hwa Lee*, Chris H. Kim University of Minnesota, Minneapolis, MN *Samsung Electronics, Hwasung, Republic of Korea

2 Outline Cache Scaling Trends 6T SRAM vs. Gain Cell EDRAM Proposed Techniques for Extending EDRAM Retention Time Boosted 3T EDRAM Cell Regulated Bit-Line Write Scheme PVT-Tracking Tracking Read Reference Bias 65nm EDRAM Chip Measurements Conclusion 2

3 On-Die Cache Memory Trends TAG TAG S. Rusu et al., JSSC07, Intel Cache size has doubled every process generation to obtain higher performance Multi-thread thread and multi-core processors have large appetite for on-die caches 3

4 6T SRAM vs. 3T Gain Cell EDRAM Large size ~130F 2 Large cell leakage High speed Ratioed operation: Poor low voltage margin Compact size ~65F 2 Small cell leakage Logic compatible Decoupled read and write paths: Good low voltage margin Retention time constraints (10~100µs [1][2]) [1] D. Somasekhar, ISSCC08, Intel [2] W. Luk, VLSI Symp., 2006, IBM 4

5 Cell Retention Time Issue WWL (VDD) RWL (VDD) WBL (GND) I GOVIGATE I JUNC RBL (GND) Pull up leakages for data 0 Gain cells have very small storage capacitance Retention time varies exponentially with PVT Longer retention time improves read performance and lowers refresh power consumption This work focuses on extending retention time 5

6 Previous 3T1D Cell for Preferential Boosting Data 1 Data 0 W. Luk et al., VLSI Symp., 2006 RWL coupling enhances retention time and read speed with an additional gated-diode Partial storage node amplification effect Limitations: larger cell size and increased gate leakage from gated-diode 6

7 Proposed 3T Cell for Preferential Boosting Δ=0.3V ( 0 ) Δ=0.16V ( 1 ) Before boosting After boosting Full storage node amplification using only 3 devices provides ~2X higher cell read current No sub-threshold leakage through read path RBL should be kept near VDD to maintain a large boosted current adopt current sensing 7

8 Hybrid Current/Voltage Sensing Scheme RBLL Current Voltage RBLR I IN I INB Read SA 0 bias 0V RWL SAB VDD Dummy RWL PMOS latch (-R) and NMOS resistor (+R) Current S/A detects cell signals with RBL levels held near VDD (<50mV swing) PMOS latch in current S/A and NMOS latch amplify analog signals to CMOS full swing 8

9 Data 1 Write Disturbance Problem RBL(VDD) WBL(VDD) I SUB 0 VDD nm, 0.9V, 85ºC Data 1 Steady-state cell node voltage Data 0 0 1E-3 2E-3 3E-3 4E-3 5E-3 Large sub-threshold leakage in unselected cells on the same WBL Boosted supply for WWL is common but requires large and power-hungry charge pump circuits Steady-state cell node voltage can be used as the data 1 write voltage to eliminate boosted supply 9

10 Regulated Bit-Line Write Scheme Volts Time - + WBAC CK PRECH HB L L SA Regulated voltage (VWR) for data 1 write Write-back speed improvement Uses the negative supply VBB for the WBL pre-charge control signal VBB already present on the chip for WWL under-drive 10

11 PVT-Tracking Read Reference Bias Scan DATA Scan CLK SCAN CHAIN I REF I REF 3T gain cell read path replica Die-to-die adjustable I REF - + VDUM Feedback circuit tracks desired cell read current D2D adjustable using a binary-weighted read path replica 51% read speed gain over previous technique [1] at 0.8V, with the consideration of both high and low leakage corners [1] D. Somasekhar, ISSCC08, Intel 11

12 32kb EDRAM Array Structure VDUM VBB DRWLL WWLL0 RWLL0 WWLL127 RWLL127 RIO WIO VWR VBB VDUM RWLR127 WWLR127 RWLR0 WWLR0 DRWLR 128 cells per WL, 128 cells per split BL which share common BLSA 12

13 Read and Write-back Timing nm, 0.9V, 85ºC Cell 1 ISAE RWL Cell 0 PEQ VSAE SA@ Current S/A out WBACK WBL 1 WBLPRECH WWL WBL n 2n 3n 4n 13

14 Read Speed Simulation Results Under Variation Proposed cell and S/A achieves 41% speed gain Current S/A is 13% slower than voltage S/A for CONV 3T with 128 cells per BL 14

15 Cell Layout Comparisons 65nm LP CMOS logic process rule Layout optimized for leakage, storage cap, area, variation, etc Boosted 3T cell is 47% smaller than a 6T SRAM and 17% smaller than a 3T1D cell 15

16 EDRAM Test Chip Microphotograph Scan Bias 32Kb Array Conv. COLDEC 32Kb Array Proposed ROWDEC-1 ROWDEC-2 Peripheral Circuits Combination of different cells and reference schemes Achieves 10X longer retention ti time than a conv. 3T gain cell measured from the same silicon die 16

17 Regulated Bit-Line Write Scheme Measurements CONV D1 disturb D0 hold mode 0.5 This work V, 85ºC 0 1E+0 1E+2 1E+4 1E+1 1E+3 Negative V GS effect verified in write path of unselected cells Cell voltage measured using external read bias D1 write disturbance solved w/o a boosted supply 17

18 (µsec) Reten ntion time Measured Retention Time, Cell Voltage This work CONV 3T 0.9V, 85ºC 0 1E+0 1E+1 1E+2 1E+3 1E+4 10X retention time improvement over conv. 3T cell measured from the same silicon die Preferential boosting effect of cell node voltage measured 0.27V signal amplification at 1.0 msec 18

19 Static Power Comparisons Refresh (WBL & RBL current) Refresh (Peripheral current) Cell leakage % Refresh period: 100μsec for CONV 3T 1msec for Boosted 3T % % 0 CONV CONV Proposed SRAM SRAM 3T edram 3T edram 3T edram 53% static power saving compared with a powergated SRAM with half the number of cells 19

20 Conclusions Gain cell edram as an alternative for SRAM 2X higher bit cell density, logic compatible Potential for good low voltage margin Proposed circuit techniques for extending edram retention time Boosted 3T gain cell Regulated bit-line write scheme PVT-tracking read reference bias A 0.9V, 65nm 64kb edram chip demonstrated >1.0msec data retention time (10X improvement) 2.0ns cycle time 91.3µW per Mbit static power dissipation at 1.0V 20