A Generation Ahead Designing Advanced Embedded Systems with Xilinx Zynq All Programmable SoCs

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1 A Generation Ahead Designing Advanced Embedded Systems with Xilinx Zynq All Programmable SoCs 김혁 Embedded Processor Specialist, Xilinx 1 st - Oct, 2013

2 Market Challenges for Embedded Solutions Integrating audio codecs in next-generation SoCs for smartphones and tablets Diverse Markets and Applications with Variety of Needs Economies of Scale Leveraging the development of one chip architecture is key Cost of Next Generation Products Process Technology, Packaging, etc Many Embedded Product Lifetimes >10 years Consumer and Handheld Lifecycle <36 months Security More Important and Relevant Driven by Connectivity and the Internet of Things (IoT) wwwgo-gulfcom/blog/cyber-crime/

3 What Next for ASSPs and Processors Gartner Competitive Landscape Study Five electronic equipment types will account for 50% of total ASSP revenue in 2015 Mobile Phones, Media Tablets, LCD TVs, Laptops and Desktops Not optimized for Industrial, Automotive or Consumer use The ASSP market is splitting into two distinct categories Process leaders that design their products in leading edge nodes All others that use older processes Gartner Competitive Landscape: Application-Specific Standard Product Semiconductors (2011)

4 Growing Importance of Programmable Logic Gartner ASIC and ASSP Trend Study Key Drivers ASIC and ASSP design costs continue to rise FPGAs are increasingly embedding more IP (processor cores) Gartner ASIC and ASSP Design Starts Continue Declining Trend Study (2012)

5 The First All Programmable SoC NOW in Production 500+ Unique Customers Actively Designing 100+ AP SoC Specific Partners All Major OSs Supported and In Use 20+ Different Development Boards Multiple Industry Awards

6 A Generation Ahead Zynq-7000 All Programmable SoC Integration Power Performance BOM Cost Productivity Zynq-7000 Unmatched Performance and Power Dual 1GHz ARM Cortex A9 Processor Largest and highest performance memory system Lowest power and fastest logic fabric Proven Productivity Industry leading High Level Synthesis Widest selection of SW environments & tools Largest portfolio of IP, design kits and reference designs Enabling Smarter Systems Smart IP targets key focus areas Most efficient ARM + FPGA for analytics and control Most extensive OS, middleware and stack ecosystem Highest level of security and reliability

7 Zynq-7000 All Programmable SoC A Mature Solution Now in Production ARM Partnership (AXI-4) First Public Announcement Open Source Linux Development Boards Available 1 GHz Parts Shipped Full Production First Linux Boot First Customer Shipment 1 st Zynq Product Delivered by Customer

8 Zynq-7000 All Programmable SoC Portfolio

9 Select I/O Processor Subsystem USB(2) GigE(2) GPIO SDIO CAN(2) I2C(2) UART(2) SPI(2) NAND QSPI Peripheral Interfaces Shared Memory (OCM) Dual Core Cortex-A9 32K I/D Cache 512K L2 Cache Switch Network DDR CTRL DDR2 DDR3 LPDDR Key Features ARM Dual Core Cortex -A9 Processor 256KB On Chip Memory Acceleration Coherency Port Enables Hardware Accelerators CPU Frequency 667MHz 1GHz Memory Frequency 533MHz 667MHz DSP Performance 100GMACs 2,622 GMACs Encryption, Authentication, Anti-Tamper AXI Interfaces Debug Programmable Logic ADC 2x12bMSPS with up to 17 Differential Inputs Transceivers PCIe High Performance I/O Devices scale by Programmable Logic Performance, Size & I/O

10 Complete ARM-based Processing System Processor Core Complex Dual ARM Cortex-A9 MPCore with NEON extensions Single / Double Precision Floating Point support Up to 1 GHz operation High BW Memory Internal L1 Cache 32KB/32KB (per Core) L2 Cache 512KB Unified On-Chip Memory of 256KB Integrated Memory Controllers (DDR3, DDR2, LPDDR2, 2xQSPI, NOR, NAND Flash) Integrated Memory Mapped Peripherals 2x USB 20 (OTG) w/dma 2x Tri-mode Gigabit Ethernet w/dma 2x SD/SDIO w/dma 2x UART, 2x CAN 20B, 2x I2C, 2x SPI, 32b GPIO AMBA Open Standard Interconnect High bandwidth interconnect between Processing System and Programmable Logic ACP port for enhanced hardware acceleration and cache coherency for additional soft processors Processing System Ready to Program Page 10

11 Powerful Application Processor at Heart The Application Processor Unit (APU) Dual ARM Cortex-A9 MPCore with NEON extensions Up to 1 GHz operation (7030 & 7045) 25 DMIPS/MHz per core Multi-issue (up to 4), Out-of-order, Speculative Separate 32KB Instruction and Data Caches with Parity Snoop Control Unit L1 Cache Snoop Control Snoop filtering monitors cache traffic Accelerator Coherency Port Level 2 Cache and Controller Shared 512 KB Cache with parity Lockable NEON / FPU Engine MI Cortex -A9 MPCore O 32/32 KB I/D Caches 512KB L2 Cache Snoop Control Unit On-Chip Memory (OCM) Dual-ported 256KB Low-latency CPU access NEON / FPU Engine Cortex -A9 MPCore 32/32 KB I/D Caches 256 KB OCM Interrupt Controller, Timers, DMA, Debug, etc Accessible by DMAs, Programmable Logic, etc Page 11

12 Processing System External Memories Built-in Controllers and dedicated DDR Pins DDR controller DDR3, DDR2, and LPDDR2 16 bit or 32 bit wide; ECC on 16 bit up to DDR1333 up to DDR800 up to DDR dedicated DDR pins NAND Controller ECC 8 bit or 16 bit data widths NOR/SRAM Controller 8 bit data width Quad SPI (QSPI) Controller To MIO Up to 2 QSPI parallel memories for highspeed boot and configuration NAND CTRL From Central Interconnect 2 Chip Selects NOR /SRAM CTRL APU QSPI CTRL DDR Controller From L2 Cache Controller 32 bit 16 bit 4 x 8 bit 2 x 8 bit 2 x 16 bit 1 x 16 bit 1x 32bit Legend Arrow direction shows control, Data flows both directions AXI3 64 bit / APB 32 bit NA 2 Dedicated to Programmable Logic Page 12

13 Comprehensive set of Built-in Peripherals Enabling a wide set of IO functions Two USB 20 OTG/Device/Host Static Memory Controllers Two Tri- Mode GigE (10/100/1000) 2x SPI Two SD/SDIO interfaces 2x I2C Two CAN 20B, SPI, I2C, UART 2x CAN Four GPIO 32bit Blocks Multiplexed Input/Output (MIO) Multiplexed output of peripheral and static memories 54 I/O MUX 2x UART GPIO 2x SD/SDIO with DMA Two I/O Banks: each selectable - 18V, 25V or 33V Configured using new feature in XPS 2x USB with DMA Extended MIO Enables use of Select IO with PS peripherals 2x GigE with DMA Extended MIO Page 13

14 Peripherals Programmable Logic to Memory Primary System Interconnects Maximizing Data Transfers Programmable Logic to Memory 2 Ports to DDR Controller 1 Port to OCM SRAM Central Interconnect Crossbar switches for high bandwidth communications Processing System Master Ports 2x 32b AXI Ports from Processing System to Programmable Logic Connects CPU Block to Common Peripherals, through the Central Interconnect Processing System Slave Ports 2x 32b AXI Ports from Programmable Logic to Processing System ACP (Accelerator Coherence Port) Low-latency cache-coherent port for programmable logic Enables application-specific customizations with a standard programming model Page 14 NAND, NOR/SRAM, QSPI Controllers Legend Configurable AXI3 32 bit/64 bit AXI3 64 bit / AXI3 32 bit / AHB 32 bit / APB 32 bit DMA L2 Cache APU OCM Central Interconnect DDR Controller OCM Master/Slave AXI Interfaces to Programmable Logic ACP Arrow direction shows control, Data flows both directions

15 Tightly Integrated Programmable Logic Built with State-of-the-art 7 Series Programmable Logic Artix-7 & Kintex-7 FPGA Fabric 28K-350K logic cells Over 3000 Internal Interconnects Up to ~100Gb of BW Memory-mapped interfaces Integrated Analog Capability Dual multi channel 12-bit A/D converter Up to 1Msps Enables Massive Parallel Processing Up to 900 DSP blocks delivering over 1334 GMACs Scalable Density and Performance Page 15

16 Flexible External I/O 54 Dedicated Peripheral I/Os Supports integrated peripherals Static memory (NAND, NOR, QSPI) More I/Os available though the Programmable Logic 73 Dedicated Memory I/Os DDR3 / DDR2 / LPDDR2 Memory Interfaces Configurable as 16bit or 32bit Over 350 Multi-Standard and High Performance I/O Up to V capable multi-standard I/O Up to 150 high performance I/O Up to differential 17 ADC inputs High Performance Integrated Serial Tranceivers (Two largest devices only) Up to 16 transceivers Operates up to 125Gbs Supports popular protocols Integrated PCIe Gen2 block Flexibility Beyond Any Standard Processing Offering Page 16

17 BOM Cost BOM Cost Reduction Reduced Devices per Board Processors, PLDs, DSPs A/D converters Power supplies, fans, etc FPGA Up to 40% BOM Cost Reduction vs Multi- Chip Solutions Reduced PCB Complexity Fewer traces/interconnect/layers Fewer power supplies Smaller overall PCB DSP Processor PCB / Other Components AP SoC Multi-chip In-System Reconfiguration Combines Multiple Device Functions Reconfigureable programmable logic to provide specific functionality at a given time Zynq-7000 PS Aggregates Numerous IP Royalties for Net Cost Benefit ASIC or full FPGA solutions would require purchase of these IPs from 3 rd parties Platform approach enables higher volumes and lower prices

18 Total Power Reduction Flexible/Tunable Power Envelope Adjustable processor speed Adjustable ARM AMBA - AXI & memory speeds ARM low power states Programmable logic can be turned off Programmable logic clock gating Partial reconfiguration to reduce Programmable logic requirement Integration Power Reduction Reduced interconnections between devices Fewer system devices Lower programmable logic power (28nm HPL process) FPGA DSP Processor Up to 50% Lower Power Vs Multi-Chip Solutions AP SoC Multi-chip Zynq-7000 Significant Power Reduction at the System Level

19 Accelerated Design Productivity Reduced Time To Market Fixed processor system with large set of built in peripherals Xilinx standardizing on AMBA-4 AXI enhances portability of IPs Scalable optimized architecture for IP re-use; AXI interfaces for plug & play IP Accelerate development with targeted design platforms Increased Time In Market Software and hardware re-programmability ASIC / ASSP / 2 Chip Dev Design #1 Dev Design #2 Dev Design #3 Field upgradable Address Processor/ASSPs short shelf life AP SoC Dev Platform #1 Dev Dev Extended Product life Platform Approach Enables Horizontal and Vertical Scalability

20 PetaLinux Enabling Linux for Zynq-7000 AP SoC Xilinx Acquired PetaLogix, August 2012 Enables You to Generate Linux BSP s and Tools Eliminates hardware flow for the software developer Provides all programmable specific runtime tools PetaLinux is the Xilinx Linux Distribution Xilinx also support an open source git tree PetaLinux Includes QEMU Software Prototyping Solution PetaLinux Will Be Released through Yocto Twice Yearly Releases and (yearmonth model from open source) PetaLinux SDK Available at wwwxilinxcom/tools/petalinux-sdkhtm

21 Xilinx SDK: Software Development and Debug Standard Eclipse Based IDE Develop Linux and Bare-Metal Applications Project Templates: Board Support Package (BSP), Boot Loader, C & C++, Memory & Peripheral tests Xilinx SDK Build, Deploy, Debug Build with integrated compiler(s) Automatically deploys to target, connects debugger, and begins program execution Performance System Debugger Xilinx Focus on Key Differentiation Processor & Logic HW-SW design with cross tool awareness Performance visualization Heterogeneous and multicore debug Turn-Key Application Development Environment Free for Download Today

22 Zynq In Use Today Smarter Broadcast - Ultra HDTV and Projection - TelePresence - Studio/Professional Cameras Smarter Wireless - Radio & microwave backhaul - Baseband processing - Timing, switching & synchronization Smarter Industrial & Medical - Intelligent Surveillance - Machine Vision - Medical Displays Smarter Wired Networks - OTN Switching - Backhaul, timing & synchronization - Metro/Core/Enterprise Ethernet Smarter Automotive - Advanced Driver Assistance - In Vehicle Infotainment - Driver Information Smarter Data Center - Top-of-Rack switching - Storage - Network security appliances Smarter Aerospace & Defense - Night Vision - Cockpit Display - UAVs

23 Use Model: Control & Data Flow Control & Data Flow Model Processors used for Control & Resource Management Custom Hardware Used for Complex Functions & Data Flows (usually fixed function) Usually an Symmetric Multiprocessing (SMP) Type System Typical Applications Next Generation OTN Switch Integration Needs Extreme Bandwidth Ubiquitous Computing Security Datacenter App Delivery Control Integration Needs Extreme Bandwidth Ubiquitous Computing Security The introduction of these speeds (100 Gbps) is causing a fundamental change in the way optical networks are built Cloud-based mobile applications will grow 88% to nearly $95B in % of this market are enterprise customers Juniper Research Infonetics Research Next Gen Industrial Automation Integration Needs Extreme Bandwidth Smart Vision Ubiquitous Computing Security/Safety Production methods must be optimized with urgency in view of a growing world population with relatively limited resources Jim Chrzan, Publisher, Automation World Source: EETimes LTE Wireless Active Antenna Integration Needs Extreme Bandwidth Ubiquitous Computing Security LTE capital spending projected to boom reaching $243B in operators worldwide already trialing, deploying 4G LTE networks Jagdish Rebello, IHS isuppli

24 Xilinx Zynq-7000 AP SoC Customer Application Mobilicom The outstanding combination of digital signal processing (DSP) capabilities, ARM processor-based performance and reprogrammable logic made Xilinx's Zynq-7030 All Programmable SoC the obvious choice as the core of our new MCU-30 SDR Not only does it meet the programmable systems integration requirements of the MCU-30 SDR, but it has also helped us to speed product development and achieve a lower bill-ofmaterials (BOM) compared to a multichip ASIC or ASSP design In addition, the exceptionally low power requirements of the Zynq-7030 All Programmable SoC enabled us to maximize battery life, which is especially critical for public safety and other mobile applications Solution Mobilicom's design engineers used the Zynq-7030 All Programmable SoC as the heart of its MCU-30 SDR platform to develop a custom advanced wireless networking protocol without the major expense and risk of custom ASIC development Results New Zynq-based ECU provides lower power consumption, yet delivers more than twice the performance in a small footprint Business Value Mobilicom speeds product development and achieves lower bill-ofmaterial (BOM) costs compared to multi-chip ASIC and ASSP designs in public safety end user terminals ~ Yossi Segal VP of R&D Mobilicom

25 Use Model: Acceleration and Performance Acceleration & Performance Model Processors used as the Primary Compute Platform System Balances Software & Hardware Partitioning Hardware is used for Acceleration or Preprocessing Communication between Processor & Hardware is Critical Usually an Asymmetric Multiprocessing (AMP) Type System Typical Applications Unmanned Air Vehicle Integration Needs Extreme Bandwidth Smart Vision Ubiquitous Computing Security Military police utility companies farmers It s going to happen Dan Elwell, VP Civil Aviation at the Aerospace Industries Association 4k Digital Cinema & Distribution Integration Needs Extreme Bandwidth Smart Vision Ubiquitous Computing Security Robotic Surgery Platform Integration Needs Extreme Bandwidth Smart Vision Ubiquitous Computing Page 17 In early 2012, digital cinema will overtake celluloid globally Avatar was the catalyst for the change It drove screens to 3D David Hancock, Analyst, IHS Screen Digest Source: Mail Online recovery from conventional open-heart surgery typically took more than 3 months I returned to work in only 4 weeks I felt great! Charles Brickwell, DaVinci Patient Intuitive Surgical

26 Zynq-7000 All Programmable SoC Solution Ready and Now Available Unmatched Performance and Power, Proven Productivity & Enabling Smarter Systems Learn More Zynq: wwwxilinxcom/zynq