80386 Segmentation unit allows segments of size at maximum. If input pin of if activated, allows address pipelining during bus cycles.

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1 Id Segmentation unit allows segments of size at maximum. 4Gbytes 6Mbytes 4Mbytes 1 Mbytes Id 2 If input pin of if activated, allows address pipelining during bus cycles. S16# N# PEREQ S# Unit 1 Id 3 Virtual Mode Flag bit can be set using instruction or any task switch operation only in the mode IRET, Virtual POPF, Real IRET, protected POPF, protected

2 Id 4 The interrupt vector table in real mode of has been allocated space starting from to. 1Kbyte, 00000H, 003FFH 2Kbyte, 10000H, 004FFH 3Kbyte, 01000H, 007FFH 4Kbyte, 01000H, 009FFH Id 5 The bit decides whether it is a system descriptor or code/data segment descriptor P S G Id support which type of descriptor table from the following? TT T GT MT

3 Id support overall addressing modes to facilitate efficient execution of higher level language programs Marks 2 Id 8 The is a bit Microprocessor Id 9 The LU of is bit

4 Id 10 The 80386X can address up to virtual memory 1 T 8T 16T 64T Marks 2 Id 11 rchitecture of allows simultaneous instruction fetching, decoding and execution of instruction. Pipelined Harward Princeton Von Neuman Marks 2 Id 12 Which of the following function unit supported by 80386? entral Processing Unit Memory Management Unit us ontrol Unit ll of these

5 Unit 1 Id 13 Unit reads the instruction from instruction queue Execution Paging Instruction predecode Segmentation Unit 1 Id 14 The Execution unit of consist of ontrol Unit ata Unit Protection test unit ll of these Id 15 unit takes instruction bytes from the code prefetch queue and translates them into microcode ontrol Unit ata Unit Instruction decode Segmentation

6 Id 16 ecoded instructions are stored in PU register Memory ecoded Instruction queue None of these Id 17 Which unit Translate logical address into linear address? Instuction ecode Paging Segmentation ontrol Id 18 address and are added to generate linear address. Effective, Segment ase offset, instruction register Effective, Instruction register None of these

7 Id 19 unit translate the linear address into physical address Segmentation Instruction ecode Instruction predecode Paging Id 20 Page size in is 1 Kbytes 2 Kbytes 4 kbytes 8 kbytes Id 21 In 80386, which of the following signal is used to identify machine cycle? M / IO# /# W/R# ll of these

8 Id 22 The data us of consist of how many pins Marks 2 Id 23 What is the size of GTR in 80386? 16 bits 32 bits 48 bits 64 bits Id 24 What is the size of LTR in 80386? 16 bits 32 bits 48 bits 64 bits

9 Id 25 What is the size of ITR in 80386? 16 bits 32 bits 48 bits 64 bits Id 26 What is the size of TR in 80386? 16 bits 32 bits 48 bits 64 bits Id 27 How many maximum entries are possible in GT?

10 Id 28 How many maximum entries are possible in LT? Id 29 How many maximum descriptors are possible in IT? Id 30 Which of the following are known as protected mode register? LTR GTR ITR ll of these

11 Id 31 Which of the following is not a bus control signal? S# INTR E0#-E3# ll of these Id 32 Signal activate the 16-bit data bus operation. N# HOL REY# S16# Id 33 How many Special flags are available in 80386?

12 Id 34 Following flags are available in VM IOPL RF ll of these Id 35 What is the size of EFLGs in 80386? Id 36 Which control register holds the machine status word? R0 R2 R3 R1

13 Id 37 Page directory base address (PR) is available in. R0 R2 R3 R1 Id 38 Which of the following not a system address register? GTR LTR ITR None of these Id 39 What is the size of Physical address in 80386?

14 Id 40 The TL is a -way set associative -entry page table cache. Four, 64 Four, 32 Six, 32 Two, 32 Marks 2 Id 41 The upper linear address bits are compared with all entries in the TL to determine if there is a match. 32, 20 32, 32 20, 32 None of these Id 42 What is the size of segment selector in 80386?

15 Id 43 Which Test Register/s is/are available in TR6 TR7 oth a and b None of these Id 44 How many 8 bit ports, the IO space of consists of? 32K 64K 128K 48K Id 45 What is the memory space of in real mode? 64 Kbytes 1 Mbytes 4 Gbytes 64 Terabytes

16 Id 46 Locations FFFFFFF0H through FFFFFFFFH are reserved for. interrupt table area GT system initialization area None of these Id 47 Length of quadword is 16 bits 32 bits 8 bits 64 bits Marks 2 Id 48 Where the LT descriptors are present in 80386? In GT In LT In IT None of these

17 Id 49 How many hardware interrupts are available in 80386? None of these Id 50 If S = 0 and TYPE = 2 defines. b LT descriptor TSS escriptor Gate escriptor ll of these Id 51 How many priviledge levels are avilable in 80386?

18 Id 52 What is the advantage of virtual 86 mode? Execution of 8086 applications with protection Multitasking Multiuser ll of above Id 53 In virtual 86 mode of 80386, what is the size of address bus? 20 bit 21 bit 24 bit 32 bit Id 54 How can switch to virtual 86 mode? Through a task switch n IRET instruction from a procedure both (a) and (b) after reset

19 Id 55 Which descriptor table should be maintained for switching to virtual 86 mode Interrupt escriptor Table Global escriptor Table Local escriptor Table None of above Id 56 Which control register is used when a virtual mode is invoked? R0 R1 R2 R3 Marks 2 Id 57 In virtual 8086 mode paging can be enabled paging can be disable (a) or (b) None of these

20 Marks 2 Id 60 If S = F000H and IP = FFF0H, what is the linear address generated in virtual FFFF0H FFFFFH 000FFFFH None of these Marks 2 Id 61 In a virtual memory system, the addresses used by the programmer belongs to memory space physical addresses address space main memory address Marks 2 Id 62 To enter in protected mode, bit should be at logic 1. PG ET PE NT

21 Marks 2 Id 63 To return from a task, instruction is used. RET IRET JMP LL Id 64 What is the size of visible part present in TR of 80386? 16 bit 20 bit 24 bit 32 bit Id 65 What is the minimum size of TSS in 80386? 64 bytes 104 byte 4 K 64 K

22 Id 66 One Page Table Entry is used to access of memory. 4 K 4 M 1 M 1 byte to 4 G Id 67 One Page irectory Entry is used to access of memory. 4 K 4 M 1 M 1 byte to 4 G Id 68 If page fault generates then address is stored in register. physical, R2 physical, R3 linear, R2 linear, R3

23 Id 69 What is the size of page table entry and page directory entry? 16 bit 24 bit 32 bit 64 bit Id 70 If present (P) bit in Page irectory Entry is 0, then of memory is not present. 4 K 8 K 4 M 4 G Id 71 In page table entry, bits are used to store address of a page frame. 12 bits 20 bits 24 bits 32 bits

24 Id 72 The TL holds the recent entries of page tables none of these Id 73 What is the size of page directory? 4 K 8 K 64 K hangeable Id 74 If paging is disabled then, logical address is same as physical address linear address is same as physical address all three addresses are same all three addresses are different

25 Id 75 In 80386, privilege levels are defined by PL PL RPL ll of above Id 76 Since each task on Intel386 X has a maximum of selectors, and offsets can be this gives a total of terabytes of logical address space per task. 6, 4G, 64 64, 4G, 64 16K, 4G, 64 None of these Marks 4 Prepared and ompiled by: Prof.M..Salunke & Prof.R.S.Vairagde of SITS, Narhe.

MICROPROCESSOR ALL IN ONE. Prof. P. C. Patil UOP S.E.COMP (SEM-II)

MICROPROCESSOR ALL IN ONE. Prof. P. C. Patil UOP S.E.COMP (SEM-II) MICROPROCESSOR UOP S.E.COMP (SEM-II) 80386 ALL IN ONE Prof. P. C. Patil Department of Computer Engg Sandip Institute of Engineering & Management Nashik pc.patil@siem.org.in 1 Architecture of 80386 2 ARCHITECTURE