CET4805 Component and Subsystem Design II. EXPERIMENT # 5: Adders. Name: Date:
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1 EXPERIMENT # 5: Adders Name: Date: Equipment/Parts Needed: Quartus II R Web Edition V9.1 SP2 software by Altera Corporation USB drive to save your files Objective: Design a half adder by extracting the Boolean equation from a fuction table Design a full adder by extracting the Boolean equation from a fuction table Construct the half adder and full adder circuits from a Boolean equation Construct and demonstrate adder circuits using the 7483 integrated circuit Discussion: The fundamental building block of addition is the half adder, whose function table is shown in the Table 5-1. By observation, you may recognize that the Carry output is the AND gate with respect to inputs A and B. The Sum output is the exclusive OR gate with respect to inputs A and B. A 0 B 0 Carry Sum Table 5-1 Half adder function table The full adder is a circuit with the three inputs, A, B, C IN, and two outputs, Sum and Carry. The fuction table for the full adder is shown in the Table 5-2. A 1 B 1 C IN Carry Sum Table 5-2 Full adder function table The half adder is used to add the units column bits of a multi-digit number. Full adders are used to add bits in the 2s column, 4s column, and 8s column of a nibble of data.
2 Figure 5-1 Block diagram of a 4-bit binary adder The 4-bit binary adder, 7483, contains four full adders cascaded together to perform hex nibble addition. This adder has a carry input, C IN, to the least significant adder, and a C OUT from the most significant adder, allowing one to cascade several 7483 chips to perform multi-nibble addition. Part 1 Half Adder 1. Open the Quartus II software. Select File New Project Wizard. Enter the appropriate drive letter for the designated storage area on the computer you are using followed by the working directory C:\altera\91sp2\quartus\kwon\Lab5. You need to go through the step from 1 through 8 in the Part 1 of Lab1 manual. Don t forget to create the folder Lab5 under the subfolder of your last name. Assign the project name Lab5_1, assign Cyclone II for the device family, and select the EP2C35F672C6 chip in the Family & device settings [page of 3 of 5]. 2. Create the Boolean equation from the function table that represents the Carry output with respect to inputs A 0 and B 0. Carry = 3. Write the Boolean equation from the function table that represents the Sum output with respect to inputs A 0 and B 0. Sum = 4. Open a new Block diagram/schematic file (File > New) and construct the circuits of a half adder based on your equations. Each symbol should be available in the Project Library in the Symbol diagonal box. Figure 5-2 Half adder circuit 5. Before compiling this bdf file, we need to name this bdf file and save it as part of our project under your subfolder. Choose File > Save As and enter File name as lab5_1. Place a check mark in the space labeled Add file to current
3 6. Compile the project by selecting Processing > Start Compilation, or press Ctrl-L, or use the Compilation button in 7. As you have done step 23 through 28 in the Part 1 of Lab1, you need to create a Vector Waveform File (vwf) to simulate a design(bdf) file. Add all inputs and output, specify an end time of 1 µs and a grid size of 100ns for our waveform display, and then save it as lab5_1.vwf. 8. Select Processing Start Simulation, or press Ctrl-I, or use the Simulation button in the toolbar. After a few 9. The Simulation Waveforms appear in the Simulation Report. You may have to expand the size of the Simulation Part 2 Full Adder 1. Create the Boolean equation from the function table that represents the Carry output with respect to inputs A 1 and B 1. Carry = 2. Write the Boolean equation from the function table that represents the Sum output with respect to inputs A 1 and B 1. Sum = 3. Create the project Lab5_2, assign Cyclone II for the device family, and select the EP2C35F672C6 chip in the Family & device settings [page of 3 of 5]. Do not select a different project directory, click NO. 4. Open a new Block diagram/schematic file (File > New) and construct the circuits of a full adder based on your equations. Figure 5-3 Full adder circuit 5. Before compiling this bdf file, we need to name this bdf file and save it as part of our project under your subfolder. Choose File > Save As and enter File name as lab5_2. Place a check mark in the space labeled Add file to current 6. Compile the project by selecting Processing > Start Compilation, or press Ctrl-L, or use the Compilation button in
4 7. Create a Vector Waveform File (vwf) to simulate a design(bdf) file. Add all inputs and output, specify an end time of 1 µs and a grid size of 100ns for our waveform display, and then save it as lab5_2.vwf. 8. Select Processing Start Simulation, or press Ctrl-I, or use the Simulation button in the toolbar. After a few 9. The Simulation Waveforms appear in the Simulation Report. You may have to expand the size of the Simulation Part 3 4-bit Full Adder 1. Create the project Lab5_3, assign Cyclone II for the device family, and select the EP2C35F672C6 chip in the Family & device settings [page of 3 of 5]. Do not select a different project directory, click NO. 2. Open a new Block diagram/schematic file (File > New) and construct the circuits of a 4-bit full adder shown in Figure 5-4. Figure bit Full adder circuit 3. Before compiling this bdf file, we need to name this bdf file and save it as part of our project under your subfolder. Choose File > Save As and enter File name as lab5_3. Place a check mark in the space labeled Add file to current 4. Compile the project by selecting Processing > Start Compilation, or press Ctrl-L, or use the Compilation button in 5. Create a Vector Waveform File (vwf) shown in Figure 5-5 to simulate a design(bdf) file. Add all inputs and output, specify an end time of 1 µs and a grid size of 200ns for our waveform display, and then save it as lab5_3.vwf.
5 6. Select Processing Start Simulation, or press Ctrl-I, or use the Simulation button in the toolbar. After a few 7. The Simulation Waveforms appear in the Simulation Report. You may have to expand the size of the Simulation Part 4 Practice (DE-2 board) 1. Show the simulation results on the DE-2 board. In the lab report, you need to include the Boolean equations for half adder and full adder, the copies of bdf files and vwf as well as pin assignments. Don t forget to put your conclusion.
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