ECE 565: VLSI CAD Flow + Brief Intro to HLS, Logic Optimization & Technology Mapping. Shantanu Dutt ECE Dept., UIC

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1 ECE 565: VLSI CAD Flow + Brief Intro to HLS, Logic Optimization & Technology Mapping Shantanu Dutt ECE Dept., UIC

2 (High-Level Synthesis or HLS network of interconnected modules: functional units [FUs], registers, muxes, demuxes, Logic optimization (mainly of controller fsm s and other random logic; other module dessigns such as arith. FUs, regs, muxes, etc. are well known). VLSI CAD Flow: Overview (HLS) (E.g., Using a Hardware Description Language: Verilog, VHDL, SystemC or Schematic Capture) a) Tech. Mapping (mapping small subckts to predesigned cells in library). b) Physical Synthesis (inserting buffers, upsizing gates, deciding on multiple Vdd and Vth). Can be combined w/ PD. a) Design Rule Checking b) Layout Vs. Schematic Verification c) Electrical Rule Checking d) Electrical simulation and functional (logic) + metric (delay, power) verification. Iterate if simulation identifies metric problems (hot spots, timing violation, crosstalk) Shantanu Dutt, UIC

3 System to Silicon Design System Requirements Algorithm Hardware Architecture Synthesis X[k] = Σ x[n]e -j2 πk/n x[n] = Σ X[k]e +j2 πk/n Σ System Integration Fabricate and Test Physical Design For Test Observe Cont rol [Source: MITRE] Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6

4 Iterate if simulation identifies metric problems (hot spots, timing violation, crosstalk) VLSI CAD Flow: Overview (HLS) Constrained optimization problem: Opt. metric at almost all stages: One of power, delay, chip-area, total wire length (WL) w/ constraints (upper bounds) on the others plus on temperature (approx. power density), crosstalk (routing stage), yield/ variability (lower bound), etc. Very complex processes. Shantanu Dutt, UIC Disconnect between higher (above physical design) and lower stages (PD & lower): At higher stages some metrics such as those that are fully or partly interconnect-based (delay, area, dynamic power) cannot be v. accurately estimated incorrect decisions which percolate to lower stages (e.g. after routing between an adder and mult., interconnect length is much larger than anticipated due to say congestion and mis-routing) some specs (esp. delay) may not be met iterating back to higher stages to correct the approximations and re-design

5 VLSI CAD Flow: Overview Course Coverage: with particular focus on HLS and Physical Design (HLS) Iterate if simulation identifies metric problems (hot spots, timing violation, crosstalk) Shantanu Dutt, UIC

6 VLSI CAD Flow: Overview Partitioning cuts up the system into multiple subsystems to min. some metric (generally number of wires/nets cut min-cut part.) either for multi-chip impl. or for recursive invokeation for placement on a single chip. (HLS) Shantanu Dutt, UIC Iterate if simulation identifies problems (hot spots, timing violation, crosstalk) Floorplanning places major/large ploygonshaped modules on a chip to minimize chip area, wirelength (WL), delay or dynamic power with constraints on the others. Placement places smaller rectangular cells whose size/shape are well defined in sub-chip regions for the same goals as FP. Routing interconnects cells/modules via hor/vert or 45 deg. wires for similar goals as above.

7 Advanced VLSI Design ASIC Design Flow CMPE 641 Standard Cell Place and Route Flow Adapted from: CMOS VLSI Design, A Circuits and Systems Perspective, 3rd Edition, Neil Weste et al Pearson Addison-Wesley 7

8 A complete chip showing floorplanned modules Some modules are custom designed & layed-out (e.g., RAMs), while others are automated using, say, standard cells Modules Routing Shantanu Dutt, UIC

9 Another complete chip showing RAMs (custom design) + standard-cell layout RAMs Standardcell based layout (most of the chip) Shantanu Dutt, UIC

10 What HLS Produces by Examples Shantanu Dutt UIC

11 Hardware Synthesis Example 1 Computer Code Generation Programming language statement a := b + c; Hardware Synthesis Execution in a CPU Load r5 b Load r7 c ADD r2 r5 r7 (r2 <- r5 + r7) Store r2 a Mux_select CPU Mux1_select ldb Mux b Mux2_select ldc Mux c Reg_r/w Reg_addr r2 Register File r5 Mux ADDER r7 Alu_oper_select 32 Read Bus A ADD 32 Read Bus B ALU 32 Conrtol signals Control Unit (FSM) Conrtol signals Mux a Mux3_select lda Write Bus Shantanu Dutt UIC 17 17

12 Hardware Synthesis Example 2 Computer Code Generation Programming language construct if (a <= b) then begin Block A of code; end else begin Block B of code; end Hardware Synthesis B: A: C: Load r2 a Load r3 b SUB r2 r2 r3 BZ A BNEG A Block B assmb code JMP C Block A assmb code Block C assmb code Execution in a computer Computer lda a ldb Adder (Adder may be reused for other operations) Conrtol signals Control Unit (FSM) b Conrtol signals 2 s compl sign ovfl zero Recursively Synthesized Mux1_select I/Ps to code block Demux1_select Demux Hardware for Block A Mux 1 Hardware for Block B O/Ps of code block Shantanu Dutt UIC 18 18

13 Brief Intro to Logic Optimization & Technology Mapping Extracted from Notes by: Srinivas Devdas, MIT

14 Two-Level Logic Minimization Can realize an arbitrary logic function in sum-of-products or two-level form F1 = A B + A B D + A B C D + A B C D + A B + A B D F1 = B + D + A C + A C Of great interest to find a minimum sumof-products representation Solved problem even for functions with 100 s of inputs (variants of Quine-McCluskey) 3

15 Two-Level versus Multilevel 2-Level: f 1 = AB + AC + AD = AB + AC + AE f 2 6 product terms which cannot be shared. 24 transistors in static CMOS Multi-level: Note that B + C is a common term in f 1 and f 2 K = B + C f 1 =ΑΚ+AD f 2 = AK + AE 3 Levels 20 transistors in static CMOS not counting inverters 4

16 Technologies Closed book : Open book : gate-array standard-cell CMOS Domino, complex gate static CMOS LOGIC EQUATIONS TECHNOLOGY-INDEPENDENT OPTIMIZATION Factoring Commonality Extraction TECH-DEPENDENT OPTIMIZATION (MAPPING, TIMING) LIBRARY OPTIMIZED LOGIC NETWORK 5

17 Tech.-Independent Optimization Involves: Minimizing two-level logic functions. Finding common subexpressions. Substituting one expression into another. Factoring single functions. Factored versus Disjunctive forms f = ac + ad + bc + bd + ae sum-of-products or disjunctive form f = ( a + b )( c + d ) + ae factored form multi-level or complex gate 6

18 Optimizations F = f 1 f 2 = AB + AC + AD + AE + A BC D E = AB + AC + AD + AF + A BC D F Factor F F = f 1 = AB+ ( C + D + E)+ABC DE f 2 = A( B + C + D + F)+ABC DF Extract common expression G = g 1 = B + C + D f 1 = A( g 1 + E ) + A E g 1 f 2 = A( g 1 + F )+ A F g 1 7

19 What Does Best Mean? Transistor count Number of circuits Number of levels AREA POWER DELAY (Speed) Need quick estimators of area, delay and power which are also accurate 8

20 Tech.-Dependent Optimization OPTIMIZED LOGIC EQUATIONS LIBRARY TIMING CONSTRAINTS TECHNOLOGY MAPPING GATE NETLIST Area, delay and power dissipation cost functions 17

21 Closed Book Technologies A standard cell technology or library is typically restricted to a few tens of gates e.g., MSU library: 31 cells Gates may be NAND, NOR, NOT, AOIs. A B A A C A A C AB+C B 18

22 Mapping via DAG Covering Represent network in canonical form subject DAG Represent each library gate with canonical forms for the logic function primitive DAGs Each primitive DAG has a cost Goal: Find a minimum cost covering of the subject DAG by the primitive DAGs Canonical form: 2-input NAND gates and inverters 19

23 Sample Library INVERTER 2 NAND2 3 NAND3 4 NAND4 5 20

24 Sample Library - 2 AOI21 4 AOI

25 Standard cell library For each cell (e.g., NANDs, NORs, Invs, AOIs) Functional information Timing information Output slew Intrinsic delay Input capacitance Physical footprint Power characteristics (leakage power)

26 Trivial Covering Reduce netlist into ND2 gates subject DAG 7 NAND2 = 21 (# pins) = 28 (# transistors) 5 INV = 10 (# pins) = 10 (# transistors 31 = 38 (pin cost) (area cost)

27 Covering #1 2 INV = 4 (# pins) = 4 (# trans s) 2 NAND2 = 6 = 8 1 NAND3 = 4 = 6 1 NAND4 = 5 = (pin cost) (area cost)

28 Covering #2 1 INV = 2 (# pins) = 2 (# trans s) 1 NAND2 = 3 = 4 2 NAND3 = 8 = 12 1 AOI21 = 4 =? 17? (pin cost) (area cost)

29 DAG Covering Sound Algorithmic approach NP-hard optimization problem multiple fanout Tree covering heuristic: If subject and primitive DAGs are trees, efficient algorithm can find optimum cover in linear time dynamic programming formulation 25

30 Multiple fan-out

31 Partitioning a Graph Partition input netlist into a forest of trees Solve each tree optimally Stitch trees back together Any issues to take care of when doing TM for each individual tree so that the stitching back can be done (this is really a bookkeeping issue rather than intrinsically algorithmic)?

32 Resulting Trees Break at multiple fanout points 27

33 Dynamic Programming Principle of optimality: Optimal cover for a tree consists of a match at the root of the tree plus the optimal cover for the sub-trees starting at each input of the match y x p Best cover for this match uses best covers for x, y, z z Best cover for this match uses best covers for p, z 28

34 Optimum Tree Covering INV = 13 AOI = 7 NAND = 11 INV 2 NAND = 6 NAND2 3 NAND2 3 Is it a good idea to use the largest possible cover or cut going top-down or bottom-up (this may not be visible in this small example)?

35 DP Algorithm for Tech. Mapping of Tree Circuits Procedure DP_TM(p: gate output, G: circuit); /* G is a tree circuit */ if DP_TM(p, G) is stored then return(its cost, corresp. solution); Going backward from p to its fanins, produce all possible cuts (that separate the sub-ckt w/ p as o/p from the rest of the circuit) so that the # of wires cut <= max # of i/ps available for cells/gates in the library; cost = infinity; For each such cut Ci do if the subckt containing p is mappable to some gate gi in the library AND does not include any forbidden interconnects then begin cost(ci) = cost(gi) + S qj in Ci (DP_TM(qj, G)[1]); /* if DP_TM(qj, G) has already been investigated, it will be stored, and there is no need to execute this procedure again */ if cost(ci) < cost then { cost = cost(ci); solution = corresponding soln. } end if. End for; return(cost, solution); end DP_TM; Shantanu Dutt, UIC

36 Example Cuts in DP_TM C3 Recursive Calls for DP_TM C2 C1 C3 Ci is the set of gate o/ps that are in the complement (remainder) subckt. of G generated by cut Ci C4 C4 C2 C1 Shantanu Dutt, UIC

37 Analysis: Optimality? Runtime analysis: DP Algorithm for Tech. Mapping of Tree Circuits # of subsets (cuts) that can be generated from a gate g o/p q that includes g and includes fanins only up to a fan-in size of m (= max. number of i/ps among all cells in the library: if k is the # of all gate i/ps that can be enclosed by a cut across all valid cuts w/o/p at q, then # of valid cuts = O(2 k ), and k itself is O(2 m ), and thus # of valid cuts is O(2**(2 m )). However, since m is a constant like 6, the # of valid cuts per gate o/p turns out to be a medium-size constant in the range # of 1 st time calls of DP_TM for each gate o/p Total # of DP_TM calls What if the circuit is not a tree: how to process, optimal or non-optimal? How to obtain optimality for a general DAG and at the cost of how much increased runtime? Shantanu Dutt, UIC

38 What about delay optimization? d(g(c1)) C1 C in (g(c1)) Each cell g has an o/p resistance R out (g), input capacitance C in (g) and intrinsic delay d(g). R out (g(c2)) d(g(c2)) C2 R out (g(c3)) C3 R out (g(c4)) C4 d(g(c4)) Delay till root cut C2 i/p: D1 D2 D3 D1 Shantanu Dutt, UIC

39 What about delay optimization? d(g(c1)) R out (g(c2)) d(g(c2)) C2 C1 C in (g(c1)) R out (g(c3)) C3 R out (g(c4)) C4 d(g(c4)) Each cell g has an o/p resistance R out (g), input capacitance C in (g) and intrinsic delay d(g). Delay at the C1 input = max[d1 + R out (g(c2))*c in (g(c1)), D2 + R out (g(c3))*c in (g(c1)), D1 + R out (g(c2))*c in (g(c1)) ] Delay till root cut C2 i/p: D1 D2 D3 D1 Shantanu Dutt, UIC

40 Extension to DAGs: What is the problem? Ci Cr Ck u Cj Ci Cr Ck u Cj 3 different calls, one for each fanout, to TM of DAG rooted at u (TM(u)). Will the solution for TM(u) that leads to the best overall solution for the entire problem be affected by which cut/cover TM(u) is called for when the optimization metric is: a) Area or pin cost? b) Delay? Fig. 1 Fig. 2 TM(u) Shantanu Dutt, UIC

41 Appendix (not necessary to consider): Tackling fanouts in DAGs Black arcs represent parent-child relationship among cuts in a D&C context Ck Ck Ck Ci Cr Cj Ci Cj Ci Cj Cr u u u Fig. 1 Fig. 2 Two cuts Cr and Cr that change subckt(u) The only way a sibling cut can change the subcircuit rooted at u is if it enclosed a predecessor of u as by the cut Cr in Fig. 2. But such a cut can only be valid if it cuts only one gate o/p, which has to be the one for its root node, which is not the case here (Cr is invalid as cuts two node o/ps). Such a changing cut is valid only if its root node also is a predecessor of u as in Fig. 3. In such cases we will need to do as many TM calls of the subcircuit subckt(u) rooted at u as there are changes to it made by other cuts, and this can potentially be exponential over all such combinations of TMs of similar nodes as u. Practically there may be very few such changing cuts of subckt(u), but even if there are 2, we need to consider the combination of all such changed subckt(u) s for all u s w/ fanouts leading to an exponential combination if nodes w/ fanouts are Q(n), where n is the total # of nodes. If such nodes are a constant then we get a linear complexity TM algorithm as in the tree case. Cr Cr Fig. 3