Packaging avancé pour les modules photoniques

Transcription

1 I N S T I T U T D E R E C H E R C H E T E C H N O L O G I Q U E Packaging avancé pour les modules photoniques S. Bernabé, CEA-Leti Marc Epitaux, SAMTEC Workshop «Photonique sur Silicium, une rupture attendue»

2 Outline Silicon Photonics for SR interconnects Module Integration Mid-Board Optical Modules DragonFly Packaging Platform Laser Integration Optical Packaging Module Integration Outlook Self alignment On-board modules 28/11/2017 2

3 Interconnect Challenges Data Centers are evolving Increasing DataRate per switch Increasing overall distances Increasing total power Interconnect Challenges Raw speed Distance Size Cooling and thermals Various environmental constraints Source: Intel /11/2017 3

4 Silicon Photonics : building blocks Laser source Photodetector up to 40Gb/s Vertical Fiber Couplers Optical modulator up to 40Gb/s SiO2 Si SiO2 Waveguides WDM filters B. Szelag et al., SPIE Proceedings, Photonics Europe, April 2016 T. Ferrotti et al., SPIE Proceedings, February 2016 C. Sciancalepore et al., Opt. Express, October 2015 L. Virot et al., Nature Communications, September 2014 F. Boeuf et al. JLT, vol. 34, no. 2, 2016 F. Bœuf et al. IEDM, /11/2017 4

5 Complexity Silicon photonics : pushing the boundaries Main driver : Performance Integrated Photonics Metrics : Gbps/cm², mw/gbps, $/Gbps Main driver : Power Consumption Microoptics Main driver : Cost & Form Factor Manufacturing volume J.M. Verdiell, Advances in Onboard Optical Interconnects: A new generation of miniature Optical Engines, DesignCon, /11/2017 5

6 From chip to module Photonic Integrated Circuit Board Level Optical Engine Module Level Electronic IC Si Photonic IC RF access Source : Luxtera System level 28/11/2017 6

7 Silicon Photonics modules Low power 25Gbps photoreceiver 50µm pitch microbump 170 fj/bit -15 dbm sensitivity TIA design : Caltech Saaedi et al.. J. Lightwave Tech., 2015 EIC 0.8 x 1.3 mm² Reflective Tx for FTTH (EU FABULOUS project) QAM16 transmission on a single fiber Dedicated MZM segmented CMOS driver Straullu et al., ECOC PDP, 2016 Menezo et al., JLT, 34,10, Gbps receiver module WDM and SDM versions < -12dBm sensitivity at 10-9 BER EIC with 4pJ/bit consumption TIA design : ST microelectronics Bernabé et al., OIC 2016, Paper MB3 Castany et al., ESTC /11/2017 7

8 Mid Board Optical Modules Roadmap IO project (Leti+IMEC, 2006) MTP/MPO 4.6 mm between holes Bring optics on board, closer to the chipset (opposed to the front-pluggable approach) Shorter RF path between chipset and optical module Optical flies over to backplane or front panel Highest density Novel cooling options Qualified to Telcordia, sometimes MIL standards On-going standardization (COBO) Source : Bert Offrein, IBM (2011) Form factor comparison between MBOM & Front Pluggables Source : Cisco 28/11/2017 8

9 DragonFLY Packaging Platform Architectural Features MBOM packaging Semiconductor manufacturing SiPho Engine (BGA ed) Single mode optics Flip-chipped PMDs Backside illumination 4x 56G bandwidth M. Epitaux, Semicon Europe, 2017 Development carried out in the IRT Nanoelec program 28/11/2017 9

10 Challenges for Mid Board Module Integration Circuit integration Platform and CAD tool homogenization Limited generic component offering Test infrastructure Light coupling Laser integration Single mode fiber coupling and alignment Packaging integration High speed signaling and interconnect Thermal management 28/11/

11 Laser Integration Micropackage Flip-chip Direct bonding III-V die or wafer Silicon wafer De Dobbelaere,OFC 2014 Shimizu et al., Photon. Res., 2,3, 2014 Ferrotti et al., SSDM 2016 B. Szelag et al., IEDM /11/

12 Optical Packaging Optical Features Single mode fiber Free space optical layout Grating Coupler 1D output (3dB IL) 2D input (6dB IL) Mode converter Alignment Strategy Passive (vison controlled) Active S. Bernabé et al., ICSJ /11/

13 Module Integration Thermal Design RF Design Power Density Multi-Gbps interconnect requires signal processing and electronic compensation (CDR, CTLE, FFE, DFE, PAM4, ) Smaller, integrated device increases drastically the power density (1.7W/cm 2 at the MBOM level) Heatsink Alternatives Convection cooling (not sufficient) Conduction cooling Immersion Features Organic substrate 0.5mm edge connector Autodesk CFD 360 Simulation BGA interconnect SiPho chip (200um) Modeling & Simulation Modeled the system in HFSS IL: db Insertion 28 GHz RL: < -18 db up to 28 GHz Nyquist. 28/11/

14 High Throughput Assembly Strategies Self alignment: Use of micropillar structures Based on capillary forces Cu Cu/Ni/(Au) D. Zonou et al., ESTC /11/

15 Self Alignment Capability <0,5 µm misalignment For 25µm copper pillar diameter self-alignment occurs while initial offset Δr < 7µm Compatible with High throughput bonding machine Δr : 5µm (ex : Datacon 8800, UPH > 7000) D. Zonou et al., ECTC /11/

16 Mid Board Optical Modules Architectures Standalone System-in-package TL ~ 20 mm TL ~ 50 mm S. Bernabé et al., IEEE Trans. Components, Pkg and Mfg Tech., /11/

17 TSV based architectures Abs(S12) TSV WB P1 WB TSV L. Fourneaud, Internal report, CEA Leti 28/11/

18 Conclusion Silicon Photonics integrated circuits enables new ultra dense modules for datacenters and HPC The combination of Mid-Board Optics packaging platform and Silicon Photonics is offering new high performance horizon for optical interconnect: Bring the fibers closer to the signal processor (ASIC, FPGA, switch) Increase the interconnect density Offer a path to 100Gbps and much beyond Extend optical link reach However the promises of photonics integration is still facing challenges: Circuit integration Light coupling Packaging integration Most of those challenges are addressed within IRT Nanoelec MBOM module leveraging the DragonFly platform Further development making use of Advanced Packaging building blocks (microbumps, TSVs) 28/11/

19 Merci pour votre attention