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1 Code No: R Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. Convert the following to Decimal and then to Binary. (a) (b) ABCD 16 (c) (d) (e) (f) [ ] 2. (a) Simplify the following Boolean expressions to minimum no. of literals. i. x y + xy + x y ii. xy + y z + x z iii. x + xy + xz + xy z iv. (x + y)(x + y ). (b) Obtain the complement of the following Boolean expressions. [8+8] i. AB + A(B + C) + B (B + D) ii. A + B + A B C iii. A B + A BC + A BCD + A BC D E iv. ABEF + ABE F + A B EF. 3. (a) If F 1 (A, B, C, D) = (1, 3, 4, 5, 9, 10, 11) + d6, 8 and F 2 (A, B, C, D) = (0, 2, 4, 7, 8, 15) + d9, 12 Obtain minimal SOP expression for F 1 F 2 using K- map and draw the circuit using NAND gates. (b) Draw the multiple -level NAND circuit for the following Boolean - expression: ( AB + CD ) E + BC (A + B) [8+8] 4. (a) Using K-map design a combinational logic circuit to obtain 2 s complement for the given 4-bit binary number. Draw the circuit using only two input exclusive-or gates and 2- input OR gates. What is the output expression for 5 inputs? (b) Design a combinational logic circuit to compare two 4-bit binary bits A 3, A 2, A 1, A 0 and B 3, B 2, B 1, B 0 and to check if they are equal. The output is equal to 1 if two numbers are equal and 0 otherwise. [8+8] 1 of 2

2 Code No: R Set No A sequential circuit with 2 D-flip-flops A and B has two inputs (X, Y) and one output Z with following relationship D A = (A+B)X, D B = AX, Z = (A+B)X Obtain logic diagram, state table and state diagram. [16] 6. Draw the sequential circuit for serial adder using shift registers, full adder and D-FF. Explain its operation with state equations and state table. [16] 7. (a) Explain the construction of a basic memory cell and also explain with diagram the construction of a 4 * 4 RAM (b) Given a 32*8 ROM chip with an enable input, show the external connections necessary to construct a 128 * 8 ROM with four chips and a decoder. [8+8] 8. (a) What do you mean by hazard? Classify and explain. (b) Draw the logic diagram of the product of sums expression: Y= (x 1 + x 2 ) ( x 2 + x 3 ). Show that there is a 0-hazard when x 1 and x 3 are equal to 0 and x 2 goes from 0 to 1. Find a way to remove the hazard by adding one or more OR gate. [8+8] 2 of 2

3 Code No: R Set No. 2 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) List the first 20 numbers in base12. Use the letters A and B to represent the last two digits. [4] (b) Convert the following numbers with the given radix to decimal. i ii iii iv [ ] 2. (a) Express the following functions in sum of minterms and product of maxterms. i. F (A,B,C,D) = B D + A D + BD ii. F(x,y,z) = (xy + z)(xz + y). (b) Obtain the complement of the following Boolean expressions. [8+8] i. (AB + AC )(BC + BC )(ABC) ii. AB C + A BC + ABC iii. (ABC) (A + B + C) iv. A + B C (A + B + C ). 3. (a) Implement the following Boolean function F using no more than two NOR - gates and draw the circuit. F (A, B, C, D) = (0, 1, 2, 9, 11) + d (8, 10, 14, 15) (b) Implement the following Boolean function using two - level forms: [6+10] i. NAND - AND ii. AND - NOR iii. OR - NAND and iv. NOR - OR and draw the circuits. F (A, B, C, D) = Π5, 7, 9, 11, 12, 13, 14, (a) Generate 2 s complement for the given 4 bit binary number using Full-adders. (Use only block diagram for Full adders) (b) Implement the following Boolean expressions with three half - adders. D = A B C E = ABC + ABC F = ABC + ( A + B ) C G = ABC where A, B, C are the inputs and D, E, F, G are the outputs. [8+8] 1 of 2

4 Code No: R Set No (a) Explain the operation of R-S master slave flip-flop. Explain its truth table. (b) Explain the operation of master slave J-K flip-flop with neat sketch. Distinguish with edge triggering. [16] 6. (a) Write the HDL behavioral description of the 4- bit up down counter. (b) Design a counter with the following repeated binary sequence: 0, 2, 4, 6, using D flip-flops. [8+8] 7. (a) Explain the construction of a basic memory cell and also explain with diagram the construction of a 4 * 4 RAM. (b) The following memory units are specified by the number of words times the number of bits per word. Give the number of bytes stored in the memories in each case. [8+8] i. 4K * 16, ii. 2G * 8, iii. 16M * 32, iv. 256M * (a) Explain static and dynamic hazards in asynchronous sequential logic with an example. (b) Find a circuit that has no static hazards and implements the Boolean function. [8+8] F = Σ( 0,2,6,7,8,10,12) 2 of 2

5 Code No: R Set No. 3 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. Convert the following to Decimal and then to Binary. (a) (b) ABCD 16 (c) (d) (e) (f) [ ] 2. (a) Reduce the following Boolean Expressions. i. AB + A(B + C) + B (B + D) ii. A +B + A B C iii. A B + A BC + A BCD + A BC D E iv. ABEF + AB(EF) + (AB) EF. (b) Obtain the Dual of the following Boolean expressions. [8+8] i. x yz + x yz + xy z + xy z ii. x yz + xy z + xyz + xyz iii. x z + x y + xy z + yz iv. x y z + x yz + xy z + xy z + xyz. 3. (a) Implement the following Boolean function F using the two level forms NAND- AND, AND-NOR. F (w, x, y, z) = Σ0, 1, 2, 3, 4, 8, 9, 12 (b) Draw NOR-logic diagram that implements the following function: [8+8] f (A, B, C, D) = Σ0, 1, 2, 3, 4, 8, 9, (a) Design a code converter to convert 8421 code to excess - 3 code. Consider all invalid combinations, as don t cares. Draw the circuit using only NAND gates. (b) A Boolean function is defined as follows. Draw schematic circuit for the given function F. Using K-map obtain its minimal SOP expression and draw the reduced diagram.f = ( A + BC ) + ( AB D ) [8+8] 5. (a) Draw the circuit diagram for J-K-flip flop using S-R-flip flop with AND gates. Explain its operation using truth table. 1 of 2

6 Code No: R Set No. 3 (b) Give the transition table for the following flip-flops. [8+8] i. R-S flip-flop ii. J-K flip-flop iii. T flip-flop iv. D flip-flop. 6. Draw the sequential circuit for serial adder using shift registers, full adder and D-FF. Explain its operation with state equations and state table. [16] 7. (a) The Hamming code is received. Correct it if any errors. There are four parity bits and odd parity is used. (b) Determine which bit, if any, is in error in the even parity. Hamming coded character is Decode the message. [8+8] 8. (a) Describe the operation of the SR Latch using NAND gate with the help of truth table, transition table and the circuit. (b) An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the functions are: Y1 = x 1 x 2 + x 1 y 2 + x 2 y 1 Y2 = x 2 + x 1 y 1y 2 +x 1y 1 z= x 2 + y 1 Implement the circuit defined above with NAND SR latches. [8+8] 2 of 2

7 Code No: R Set No. 4 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. Convert the following to Decimal and then to Octal. (a) (b) 12EF 16 (c) (d) (e) (f) [ ] 2. (a) Reduce the following Boolean expressions. i. ((AB) + A + AB) ii. AB + (AC) + AB + C(AB + C) iii. ((AB + ABC) + A(B + AB )) iv. AB + A(B + C) + B(B + C). (b) Obtain the Dual of the following Boolean expressions. [8+8] i. x y + xy + x y ii. xy + y z + x z iii. x + xy + xz + xy z iv. (x + y)(x + y ). 3. (a) Obtain minimal SOP expression for the given Boolean function, using K-map: F (A, B, C, D) = Σ (0, 1, 4, 6, 8, 9, 10, 12) + d3, 7, 11, 13, 14, 15 And draw the circuit using 2-input NAND gates. (b) Obtain minimal POS expression for the Boolean function: f (A, B, C, D) = Π (0, 1, 2, 3, 4, 6, 9, 10) + d7, 13, 15 And draw the circuit using NAND gates. [8+8] 4. (a) Generate 2 s complement for the given 4 bit binary number using Full-adders. (Use only block diagram for Full adders) (b) Implement the following Boolean expressions with three half - adders. D = A B C E = ABC + ABC F = ABC + ( A + B ) C G = ABC where A, B, C are the inputs and D, E, F, G are the outputs. [8+8] 1 of 2

8 Code No: R Set No A sequential circuit with 3 D-flip-flops A, B and C has only one input X and one output X with following relationship D A = B C X, D B = A, D C = B (a) Draw the logic diagram of the circuit. (b) Obtain logic diagram, state table and state diagram. [16] 6. (a) A digital system has a clock generator that provides pulses at a frequency of 80 MHz. Design a circuit that provides a clock with a cycle time of 50ns. (b) Design a 4-bit ring counter using D- flip flops and draw the circuit diagram and timing diagrams. [8+8] 7. (a) Draw and explain the block diagram of PAL. (b) Implement the following Boolean functions using PAL. w(a,b,c,d) = Σ m (0,2,6,7,8,9,12,13) x (A,B,C,D) = Σ m (0,2,6,7,8,9,12,13,14) y (A,B,C,D) = Σ m (2,3,8,9,10,12,13) z (A,B,C,D) = Σ m (1,3,4,6,9,12,14). [6+10] 8. (a) Explain static and dynamic hazards in asynchronous sequential logic with an example. (b) Find a circuit that has no static hazards and implements the Boolean function. [8+8] F = Σ( 0,2,6,7,8,10,12) 2 of 2

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