Code No: R Set No. 1


 Percival Walker
 3 years ago
 Views:
Transcription
1 Code No: R Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. Convert the following to Decimal and then to Binary. (a) (b) ABCD 16 (c) (d) (e) (f) [ ] 2. (a) Simplify the following Boolean expressions to minimum no. of literals. i. x y + xy + x y ii. xy + y z + x z iii. x + xy + xz + xy z iv. (x + y)(x + y ). (b) Obtain the complement of the following Boolean expressions. [8+8] i. AB + A(B + C) + B (B + D) ii. A + B + A B C iii. A B + A BC + A BCD + A BC D E iv. ABEF + ABE F + A B EF. 3. (a) If F 1 (A, B, C, D) = (1, 3, 4, 5, 9, 10, 11) + d6, 8 and F 2 (A, B, C, D) = (0, 2, 4, 7, 8, 15) + d9, 12 Obtain minimal SOP expression for F 1 F 2 using K map and draw the circuit using NAND gates. (b) Draw the multiple level NAND circuit for the following Boolean  expression: ( AB + CD ) E + BC (A + B) [8+8] 4. (a) Using Kmap design a combinational logic circuit to obtain 2 s complement for the given 4bit binary number. Draw the circuit using only two input exclusiveor gates and 2 input OR gates. What is the output expression for 5 inputs? (b) Design a combinational logic circuit to compare two 4bit binary bits A 3, A 2, A 1, A 0 and B 3, B 2, B 1, B 0 and to check if they are equal. The output is equal to 1 if two numbers are equal and 0 otherwise. [8+8] 1 of 2
2 Code No: R Set No A sequential circuit with 2 Dflipflops A and B has two inputs (X, Y) and one output Z with following relationship D A = (A+B)X, D B = AX, Z = (A+B)X Obtain logic diagram, state table and state diagram. [16] 6. Draw the sequential circuit for serial adder using shift registers, full adder and DFF. Explain its operation with state equations and state table. [16] 7. (a) Explain the construction of a basic memory cell and also explain with diagram the construction of a 4 * 4 RAM (b) Given a 32*8 ROM chip with an enable input, show the external connections necessary to construct a 128 * 8 ROM with four chips and a decoder. [8+8] 8. (a) What do you mean by hazard? Classify and explain. (b) Draw the logic diagram of the product of sums expression: Y= (x 1 + x 2 ) ( x 2 + x 3 ). Show that there is a 0hazard when x 1 and x 3 are equal to 0 and x 2 goes from 0 to 1. Find a way to remove the hazard by adding one or more OR gate. [8+8] 2 of 2
3 Code No: R Set No. 2 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) List the first 20 numbers in base12. Use the letters A and B to represent the last two digits. [4] (b) Convert the following numbers with the given radix to decimal. i ii iii iv [ ] 2. (a) Express the following functions in sum of minterms and product of maxterms. i. F (A,B,C,D) = B D + A D + BD ii. F(x,y,z) = (xy + z)(xz + y). (b) Obtain the complement of the following Boolean expressions. [8+8] i. (AB + AC )(BC + BC )(ABC) ii. AB C + A BC + ABC iii. (ABC) (A + B + C) iv. A + B C (A + B + C ). 3. (a) Implement the following Boolean function F using no more than two NOR  gates and draw the circuit. F (A, B, C, D) = (0, 1, 2, 9, 11) + d (8, 10, 14, 15) (b) Implement the following Boolean function using two  level forms: [6+10] i. NAND  AND ii. AND  NOR iii. OR  NAND and iv. NOR  OR and draw the circuits. F (A, B, C, D) = Π5, 7, 9, 11, 12, 13, 14, (a) Generate 2 s complement for the given 4 bit binary number using Fulladders. (Use only block diagram for Full adders) (b) Implement the following Boolean expressions with three half  adders. D = A B C E = ABC + ABC F = ABC + ( A + B ) C G = ABC where A, B, C are the inputs and D, E, F, G are the outputs. [8+8] 1 of 2
4 Code No: R Set No (a) Explain the operation of RS master slave flipflop. Explain its truth table. (b) Explain the operation of master slave JK flipflop with neat sketch. Distinguish with edge triggering. [16] 6. (a) Write the HDL behavioral description of the 4 bit up down counter. (b) Design a counter with the following repeated binary sequence: 0, 2, 4, 6, using D flipflops. [8+8] 7. (a) Explain the construction of a basic memory cell and also explain with diagram the construction of a 4 * 4 RAM. (b) The following memory units are specified by the number of words times the number of bits per word. Give the number of bytes stored in the memories in each case. [8+8] i. 4K * 16, ii. 2G * 8, iii. 16M * 32, iv. 256M * (a) Explain static and dynamic hazards in asynchronous sequential logic with an example. (b) Find a circuit that has no static hazards and implements the Boolean function. [8+8] F = Σ( 0,2,6,7,8,10,12) 2 of 2
5 Code No: R Set No. 3 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. Convert the following to Decimal and then to Binary. (a) (b) ABCD 16 (c) (d) (e) (f) [ ] 2. (a) Reduce the following Boolean Expressions. i. AB + A(B + C) + B (B + D) ii. A +B + A B C iii. A B + A BC + A BCD + A BC D E iv. ABEF + AB(EF) + (AB) EF. (b) Obtain the Dual of the following Boolean expressions. [8+8] i. x yz + x yz + xy z + xy z ii. x yz + xy z + xyz + xyz iii. x z + x y + xy z + yz iv. x y z + x yz + xy z + xy z + xyz. 3. (a) Implement the following Boolean function F using the two level forms NAND AND, ANDNOR. F (w, x, y, z) = Σ0, 1, 2, 3, 4, 8, 9, 12 (b) Draw NORlogic diagram that implements the following function: [8+8] f (A, B, C, D) = Σ0, 1, 2, 3, 4, 8, 9, (a) Design a code converter to convert 8421 code to excess  3 code. Consider all invalid combinations, as don t cares. Draw the circuit using only NAND gates. (b) A Boolean function is defined as follows. Draw schematic circuit for the given function F. Using Kmap obtain its minimal SOP expression and draw the reduced diagram.f = ( A + BC ) + ( AB D ) [8+8] 5. (a) Draw the circuit diagram for JKflip flop using SRflip flop with AND gates. Explain its operation using truth table. 1 of 2
6 Code No: R Set No. 3 (b) Give the transition table for the following flipflops. [8+8] i. RS flipflop ii. JK flipflop iii. T flipflop iv. D flipflop. 6. Draw the sequential circuit for serial adder using shift registers, full adder and DFF. Explain its operation with state equations and state table. [16] 7. (a) The Hamming code is received. Correct it if any errors. There are four parity bits and odd parity is used. (b) Determine which bit, if any, is in error in the even parity. Hamming coded character is Decode the message. [8+8] 8. (a) Describe the operation of the SR Latch using NAND gate with the help of truth table, transition table and the circuit. (b) An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the functions are: Y1 = x 1 x 2 + x 1 y 2 + x 2 y 1 Y2 = x 2 + x 1 y 1y 2 +x 1y 1 z= x 2 + y 1 Implement the circuit defined above with NAND SR latches. [8+8] 2 of 2
7 Code No: R Set No. 4 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. Convert the following to Decimal and then to Octal. (a) (b) 12EF 16 (c) (d) (e) (f) [ ] 2. (a) Reduce the following Boolean expressions. i. ((AB) + A + AB) ii. AB + (AC) + AB + C(AB + C) iii. ((AB + ABC) + A(B + AB )) iv. AB + A(B + C) + B(B + C). (b) Obtain the Dual of the following Boolean expressions. [8+8] i. x y + xy + x y ii. xy + y z + x z iii. x + xy + xz + xy z iv. (x + y)(x + y ). 3. (a) Obtain minimal SOP expression for the given Boolean function, using Kmap: F (A, B, C, D) = Σ (0, 1, 4, 6, 8, 9, 10, 12) + d3, 7, 11, 13, 14, 15 And draw the circuit using 2input NAND gates. (b) Obtain minimal POS expression for the Boolean function: f (A, B, C, D) = Π (0, 1, 2, 3, 4, 6, 9, 10) + d7, 13, 15 And draw the circuit using NAND gates. [8+8] 4. (a) Generate 2 s complement for the given 4 bit binary number using Fulladders. (Use only block diagram for Full adders) (b) Implement the following Boolean expressions with three half  adders. D = A B C E = ABC + ABC F = ABC + ( A + B ) C G = ABC where A, B, C are the inputs and D, E, F, G are the outputs. [8+8] 1 of 2
8 Code No: R Set No A sequential circuit with 3 Dflipflops A, B and C has only one input X and one output X with following relationship D A = B C X, D B = A, D C = B (a) Draw the logic diagram of the circuit. (b) Obtain logic diagram, state table and state diagram. [16] 6. (a) A digital system has a clock generator that provides pulses at a frequency of 80 MHz. Design a circuit that provides a clock with a cycle time of 50ns. (b) Design a 4bit ring counter using D flip flops and draw the circuit diagram and timing diagrams. [8+8] 7. (a) Draw and explain the block diagram of PAL. (b) Implement the following Boolean functions using PAL. w(a,b,c,d) = Σ m (0,2,6,7,8,9,12,13) x (A,B,C,D) = Σ m (0,2,6,7,8,9,12,13,14) y (A,B,C,D) = Σ m (2,3,8,9,10,12,13) z (A,B,C,D) = Σ m (1,3,4,6,9,12,14). [6+10] 8. (a) Explain static and dynamic hazards in asynchronous sequential logic with an example. (b) Find a circuit that has no static hazards and implements the Boolean function. [8+8] F = Σ( 0,2,6,7,8,10,12) 2 of 2
Code No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationCode No: 07A3EC03 Set No. 1
Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,
More informationR07
www..com www..com SET  1 II B. Tech I Semester Supplementary Examinations May 2013 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, EIE, BME, ECC) Time: 3 hours Max. Marks: 80 Answer any FIVE Questions
More informationwww.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012DIGITAL
More informationCOLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA
More informationVALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 20152016 (ODD
More informationSIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)
SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : STLD(16EC402) Year & Sem: IIB.Tech & ISem Course & Branch: B.Tech
More informationENDTERM EXAMINATION
(Please Write your Exam Roll No. immediately) ENDTERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA103 Subject: Digital Electronics Time: 3 Hours Maximum
More informationB.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is  Write the first 9 decimal digits in base 3. (c) What is meant by don
More informationHANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment
Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15)
More informationSUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3
UNIT  I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented
More informationR07. Code No: V0423. II B. Tech II Semester, Supplementary Examinations, April
SET  1 II B. Tech II Semester, Supplementary Examinations, April  2012 SWITCHING THEORY AND LOGIC DESIGN (Electronics and Communications Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions
More informationR10. II B. Tech I Semester, Supplementary Examinations, May
SET  1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) 48 and +31
More informationSIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN
SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: CSE 2.1.6 DIGITAL LOGIC DESIGN CLASS: 2/4 B.Tech., I SEMESTER, A.Y.201718 INSTRUCTOR: Sri A.M.K.KANNA
More informationR a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method
SET  1 1. a) Convert the decimal number 250.5 to base 3, base 4 b) Write and prove demorgan laws c) Implement two input EXOR gate from 2 to 1 multiplexer (3M) d) Write the demerits of PROM (3M) e) What
More informationDHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY
DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY Dept/Sem: II CSE/03 DEPARTMENT OF ECE CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I BOOLEAN ALGEBRA AND LOGIC GATES PART A 1. How many
More informationVALLIAMMAI ENGINEERING COLLEGE
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY & COMPUTER SCIENCE AND ENGINEERING QUESTION BANK II SEMESTER CS6201 DIGITAL PRINCIPLE AND SYSTEM DESIGN
More informationPART B. 3. Minimize the following function using Kmap and also verify through tabulation method. F (A, B, C, D) = +d (0, 3, 6, 10).
II B. Tech II Semester Regular Examinations, May/June 2015 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, ECE, ECC, EIE.) Time: 3 hours Max. Marks: 70 Note: 1. Question Paper consists of two parts (PartA
More informationInjntu.com Injntu.com Injntu.com R16
1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by Kmap? Name it advantages and disadvantages. (3M) c) Distinguish between a halfadder
More informationVALLIAMMAI ENGINEERING COLLEGE
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY QUESTION BANK Academic Year 2018 19 III SEMESTER CS8351DIGITAL PRINCIPLES AND SYSTEM DESIGN Regulation
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More informationPrinciples of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.
Assignment No. 1 1. State advantages of digital system over analog system. 2. Convert following numbers a. (138.56) 10 = (?) 2 = (?) 8 = (?) 16 b. (1110011.011) 2 = (?) 10 = (?) 8 = (?) 16 c. (3004.06)
More informationNADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni625531 Question Bank for the Units I to V SEMESTER BRANCH SUB CODE 3rd Semester B.E. / B.Tech. Electrical and Electronics Engineering
More information(ii) Simplify and implement the following SOP function using NOR gates:
DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES PART A 1. How can an OR gate be
More informationII/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.
Hall Ticket Number: 14CS IT303 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Digital Logic
More informationHours / 100 Marks Seat No.
17333 13141 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Illustrate your answers with neat sketches wherever necessary. (4)
More informationBHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS
BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS FREQUENTLY ASKED QUESTIONS UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES
More information10EC33: DIGITAL ELECTRONICS QUESTION BANK
10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function
More informationINSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad
INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad  500 043 COMPUTER SCIENCE AND ENGINEERING TUTORIAL QUESTION BANK Name : DIGITAL LOGIC DESISN Code : AEC020 Class : B Tech III Semester
More informationSwitching Theory & Logic Design/Digital Logic Design Question Bank
Switching Theory & Logic Design/Digital Logic Design Question Bank UNIT I NUMBER SYSTEMS AND CODES 1. A 12bit Hamming code word containing 8bits of data and 4 parity bits is read from memory. What was
More informationSHRI ANGALAMMAN COLLEGE OF ENGINEERING. (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI
SHRI ANGALAMMAN COLLEGE OF ENGINEERING AND TECHNOLOGY (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI 621 105 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC1201 DIGITAL
More informationCS6201DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PARTB UNITI BOOLEAN ALGEBRA AND LOGIC GATES.
CS6201DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PARTB UNITI BOOLEAN ALGEBRA AND LOGIC GATES. 1) Simplify the boolean function using tabulation method. F = (0, 1, 2, 8, 10, 11, 14, 15) List all
More informationKINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS YEAR / SEM: II / IV UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL
More informationChapter 3. GateLevel Minimization. Outlines
Chapter 3 GateLevel Minimization Introduction The Map Method FourVariable Map FiveVariable Map Outlines Product of Sums Simplification Don tcare Conditions NAND and NOR Implementation Other TwoLevel
More informationUNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PARTA (2 MARKS)
SUBJECT NAME: DIGITAL LOGIC CIRCUITS YEAR / SEM : II / III DEPARTMENT : EEE UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 1. What is variable mapping? 2. Name the two canonical forms for Boolean algebra.
More informationINSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad
INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad  500043 Course Name : DIGITAL LOGIC DESISN Course Code : AEC020 Class : B Tech III Semester Branch : CSE Academic Year : 2018 2019
More informationCS/IT DIGITAL LOGIC DESIGN
CS/IT 214 (CR) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER 2016 First Semester CS/IT DIGITAL LOGIC DESIGN Time: Three Hours 1. a) FlipFlop Answer
More informationScheme G. Sample Test PaperI
Sample Test PaperI Marks : 25 Times:1 Hour 1. All questions are compulsory. 2. Illustrate your answers with neat sketches wherever necessary. 3. Figures to the right indicate full marks. 4. Assume suitable
More information3. The high voltage level of a digital signal in positive logic is : a) 1 b) 0 c) either 1 or 0
1. The number of level in a digital signal is: a) one b) two c) four d) ten 2. A pure sine wave is : a) a digital signal b) analog signal c) can be digital or analog signal d) neither digital nor analog
More informationMULTIMEDIA COLLEGE JALAN GURNEY KIRI KUALA LUMPUR
STUDENT IDENTIFICATION NO MULTIMEDIA COLLEGE JALAN GURNEY KIRI 54100 KUALA LUMPUR SECOND SEMESTER FINAL EXAMINATION, 2013/2014 SESSION ITC2223 COMPUTER ORGANIZATION & ARCHITECTURE DSEWEF 1/13 18 FEBRUARY
More informationHours / 100 Marks Seat No.
17320 21718 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Figures to the right indicate full marks. (4) Assume suitable data,
More informationCONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)
CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics... 1 1.1.1 Introduction... 1 1.1.2 Advantages of Digital Systems...
More informationR.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai
L T P C R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai 601206 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC8392 UNIT  I 3 0 0 3 OBJECTIVES: To present the Digital fundamentals, Boolean
More informationDigital logic fundamentals. Question Bank. Unit I
Digital logic fundamentals Question Bank Subject Name : Digital Logic Fundamentals Subject code: CA102T Staff Name: R.Roseline Unit I 1. What is Number system? 2. Define binary logic. 3. Show how negative
More informationCS8803: Advanced Digital Design for Embedded Hardware
CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883
More informationENGINEERS ACADEMY. 7. Given Boolean theorem. (a) A B A C B C A B A C. (b) AB AC BC AB BC. (c) AB AC BC A B A C B C.
Digital Electronics Boolean Function QUESTION BANK. The Boolean equation Y = C + C + C can be simplified to (a) (c) A (B + C) (b) AC (d) C. The Boolean equation Y = (A + B) (A + B) can be simplified to
More information2.6 BOOLEAN FUNCTIONS
2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses
More information1. Mark the correct statement(s)
1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another
More information2008 The McGrawHill Companies, Inc. All rights reserved.
28 The McGrawHill Companies, Inc. All rights reserved. 28 The McGrawHill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28
More informationChapter 2: Combinational Systems
Uchechukwu Ofoegbu Chapter 2: Combinational Systems Temple University Adapted from Alan Marcovitz s Introduction to Logic and Computer Design Riddle Four switches can be turned on or off. One is the switch
More informationQuestion Total Possible Test Score Total 100
Computer Engineering 2210 Final Name 11 problems, 100 points. Closed books, closed notes, no calculators. You would be wise to read all problems before beginning, note point values and difficulty of problems,
More informationExperiment 3: Logic Simplification
Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed ElSaied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions
More informationPhiladelphia University Student Name: Student Number:
Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2018/2019 Dept. of Computer Engineering Course Title: Logic Circuits Date: 03/01/2019
More informationAssignment (36) Boolean Algebra and Logic Simplification  General Questions
Assignment (36) Boolean Algebra and Logic Simplification  General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make
More informationDE Solution Set QP Code : 00904
DE Solution Set QP Code : 00904 1. Attempt any three of the following: 15 a. Define digital signal. (1M) With respect to digital signal explain the terms digits and bits.(2m) Also discuss active high and
More informationFinal Examination (Open Katz, asynchronous & test notes only, Calculators OK, 3 hours)
Your Name: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO Department of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA CRUZ CS
More informationGate Level Minimization Map Method
Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically
More informationIT 201 Digital System Design Module II Notes
IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.
More informationGateLevel Minimization
MEC520 디지털공학 GateLevel Minimization JeeHwan Ryu School of Mechanical Engineering GateLevel MinimizationThe Map Method Truth table is unique Many different algebraic expression Boolean expressions may
More informationLOGIC CIRCUITS. Kirti P_Didital Design 1
LOGIC CIRCUITS Kirti P_Didital Design 1 Introduction The digital system consists of two types of circuits, namely (i) Combinational circuits and (ii) Sequential circuit A combinational circuit consists
More informationBOOLEAN ALGEBRA. 1. State & Verify Laws by using :
BOOLEAN ALGEBRA. State & Verify Laws by using :. State and algebraically verify Absorption Laws. (2) Absorption law states that (i) X + XY = X and (ii) X(X + Y) = X (i) X + XY = X LHS = X + XY = X( + Y)
More informationSECTIONA
M.Sc(CS) ( First Semester) Examination,2013 Digital Electronics Paper: Fifth  SECTIONA I) An electronics circuit/ device
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard
More informationTopics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory
More informationCMPE223/CMSE222 Digital Logic
CMPE223/CMSE222 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum ProductofSums Forms, Incompletely Specified Functions Terminology For a given term, each
More information1. Draw general diagram of computer showing different logical components (3)
Tutorial 1 1. Draw general diagram of computer showing different logical components (3) 2. List at least three input devices (1.5) 3. List any three output devices (1.5) 4. Fill the blank cells of the
More informationKING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT
KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:0011:50AM Class
More informationDigital Logic Design Exercises. Assignment 1
Assignment 1 For Exercises 15, match the following numbers with their definition A Number Natural number C Integer number D Negative number E Rational number 1 A unit of an abstract mathematical system
More informationProgrammable Logic Devices
Programmable Logic Devices Programmable Logic Devices Fig. (1) General structure of PLDs Programmable Logic Device (PLD): is an integrated circuit with internal logic gates and/or connections that can
More informationSWITCHING THEORY AND LOGIC CIRCUITS
SWITCHING THEORY AND LOGIC CIRCUITS COURSE OBJECTIVES. To understand the concepts and techniques associated with the number systems and codes 2. To understand the simplification methods (Boolean algebra
More informationDKT 122/3 DIGITAL SYSTEM 1
Company LOGO DKT 122/3 DIGITAL SYSTEM 1 BOOLEAN ALGEBRA (PART 2) Boolean Algebra Contents Boolean Operations & Expression Laws & Rules of Boolean algebra DeMorgan s Theorems Boolean analysis of logic circuits
More informationProgrammable Logic Devices (PLDs)
Programmable Logic Devices (PLDs) 212: Digital Design I, week 13 PLDs basically store binary information in a volatile/nonvolatile device. Data is specified by designer and physically inserted (Programmed)
More informationNODIA AND COMPANY. GATE SOLVED PAPER Computer Science Engineering Digital Logic. Copyright By NODIA & COMPANY
No part of this publication may be reproduced or distributed in any form or any means, electronic, mechanical, photocopying, or otherwise without the prior permission of the author. GATE SOLVED PAPER Computer
More informationGate Level Minimization
Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =
More informationGet Free notes at ModuleI One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)
More informationWritten exam for IE1204/5 Digital Design Thursday 29/
Written exam for IE1204/5 Digital Design Thursday 29/10 2015 9.0013.00 General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 087904487 Exam text does not have to be returned when
More informationFinal Exam Solution Sunday, December 15, 10:0512:05 PM
Last (family) name: First (given) name: Student I.D. #: Circle section: Kim Hu Department of Electrical and Computer Engineering University of Wisconsin  Madison ECE/CS 352 Digital System Fundamentals
More informationLSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology
LSN 4 Boolean Algebra & Logic Simplification Department of Engineering Technology LSN 4 Key Terms Variable: a symbol used to represent a logic quantity Compliment: the inverse of a variable Literal: a
More informationECE380 Digital Logic
ECE38 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum ProductofSums Forms, Incompletely Specified Functions Dr. D. J. Jackson Lecture 8 Terminology For
More informationLecture 4: Implementation AND, OR, NOT Gates and Complement
EE210: Switching Systems Lecture 4: Implementation AND, OR, NOT Gates and Complement Prof. YingLi Tian Feb. 13, 2018 Department of Electrical Engineering The City College of New York The City University
More informationChapter 2 Boolean algebra and Logic Gates
Chapter 2 Boolean algebra and Logic Gates 2. Introduction In working with logic relations in digital form, we need a set of rules for symbolic manipulation which will enable us to simplify complex expressions
More informationPhiladelphia University Faculty of Information Technology Department of Computer Science. Computer Logic Design. By Dareen Hamoudeh.
Philadelphia University Faculty of Information Technology Department of Computer Science Computer Logic Design By Dareen Hamoudeh Dareen Hamoudeh 1 Canonical Forms (Standard Forms of Expression) Minterms
More informationStandard Forms of Expression. Minterms and Maxterms
Standard Forms of Expression Minterms and Maxterms Standard forms of expressions We can write expressions in many ways, but some ways are more useful than others A sum of products (SOP) expression contains:
More informationCOPYRIGHTED MATERIAL INDEX
INDEX Absorption law, 31, 38 Acyclic graph, 35 tree, 36 Addition operators, in VHDL (VHSIC hardware description language), 192 Algebraic division, 105 AND gate, 48 49 Antisymmetric, 34 Applicable input
More informationComputer Organization
Computer Organization (Logic circuits design and minimization) KR Chowdhary Professor & Head Email: kr.chowdhary@gmail.com webpage: krchowdhary.com Department of Computer Science and Engineering MBM Engineering
More information6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )
6. Combinational Circuits George Boole (85 864) Claude Shannon (96 2) Signals and Wires Digital signals Binary (or logical ) values: or, on or off, high or low voltage Wires. Propagate digital signals
More information2. (a) Compare the characteristics of a floppy disk and a hard disk. (b) Discuss in detail memory interleaving. [8+7]
Code No: A109211202 R09 Set No. 2 1. (a) Explain the purpose of the following registers: i. IR ii. PC iii. MDR iv. MAR. (b) Explain with an example the steps in subtraction of two ndigit unsigned numbers.
More informationChapter 4. Combinational Logic. Dr. AbuArqoub
Chapter 4 Combinational Logic Introduction N Input Variables Combinational Logic Circuit M Output Variables 2 Design Procedure The problem is stated 2 The number of available input variables & required
More informationii) Do the following conversions: output is. (a) (101.10) 10 = (?) 2 i) Define XNOR gate. (b) (10101) 2 = (?) Gray (2) /030832/31034
No. of Printed Pages : 4 Roll No.... rd 3 Sem. / ECE Subject : Digital Electronics  I SECTIONA Note: Very Short Answer type questions. Attempt any 15 parts. (15x2=30) Q.1 a) Define analog signal. b)
More informationComputer Architecture: Part III. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University
Computer Architecture: Part III First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Outline Decoders Multiplexers Registers Shift Registers Binary Counters Memory
More informationAPPENDIX A SHORT QUESTIONS AND ANSWERS
APPENDIX A SHORT QUESTIONS AND ANSWERS Unit I Boolean Algebra and Logic Gates Part  A 1. Define binary logic? Binary logic consists of binary variables and logical operations. The variables are designated
More informationSimplification of Boolean Functions
Simplification of Boolean Functions Contents: Why simplification? The Map Method Two, Three, Four and Five variable Maps. Simplification of two, three, four and five variable Boolean function by Map method.
More informationPROGRAMMABLE LOGIC DEVICES
PROGRAMMABLE LOGIC DEVICES Programmable logic devices (PLDs) are used for designing logic circuits. PLDs can be configured by the user to perform specific functions. The different types of PLDs available
More informationELCT 501: Digital System Design
ELCT 501: Digital System Lecture 4: CAD tools (Continued) Dr. Mohamed Abd El Ghany, Basic VHDL Concept Via an Example Problem: write VHDL code for 1bit adder 4bit adder 2 1bit adder Inputs: A (1 bit)
More informationUPY14602DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan
UPY14602DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UNIT I  NUMBER SYSTEMS AND LOGIC GATES Introduction to decimal Binary Octal Hexadecimal number systemsinter conversionsbcd code Excess
More informationEE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE
EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE 1 Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates, and output
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationCSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map
CSCI 22: Computer Architecture I Instructor: Pranava K. Jha Simplification of Boolean Functions using a Karnaugh Map Q.. Plot the following Boolean function on a Karnaugh map: f(a, b, c, d) = m(, 2, 4,
More informationUNIT4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable.
UNIT4 BOOLEAN LOGIC Boolean algebra is an algebra that deals with Boolean values((true and FALSE). Everyday we have to make logic decisions: Should I carry the book or not?, Should I watch TV or not?
More information