Exam Computer Systems/Computer Architecture and Organisation Bachelor 2 nd year, EE and CS, EWI

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1 Exam Computer Systems/Computer Architecture and Organisation Bachelor 2 nd year, EE and CS, EWI Module/course code: Computer Systems (CS) / (EE) Date: 30 September 2016 Time: 13:45-15:30 (+25% for students who may use extra time) Module-coördinator: A.B.J. Kokkeler Instructor: E. Molenkamp / A.B.J. Kokkeler Type of test: Closed book Allowed aids during the test: Writing materials, simple calculator Attachments: ARC processor Documentation Additional remarks: 13 questions on 10 pages 13 problems, 10 pages, 4 pages with the ARC documentation Instructions for this examination: 1. Answer the questions only in the designated locations on this form. 2. Write your name and student number on each page of this exam 3. Furthermore fill in your name, educational programme and student number below on this page. 4. Hand in all pages of this exam. 5. You may only use writing material and a simple calculator. 6. The documentation refers to the ARC processor. If a problem indicates that it is about the subset ARC processor then you may only use the instructions listed in figure 5-2 (documentation page 2). Name:... Student number:... Educational programme (EE, TI,..):... Page 1 of 10

2 Question 1 (2 points) f(a, B, C, D) = m(5,6,13,14) with don t cares m(0,4,8,12) d Give a minimal Boolean equation in sum-of-products for f B.!C + B.!D Question 2 (1 points) A circuit has three 1 bit inputs A, B and C and 1 bit output P. The output is 1 when an odd number of input values are 1, else the output is 0. You may only use 2-input XOR gates. Design this circuit with a minimum number of these gates (give a schematic). P = A xor B xor C Question 3 (1 + 1 = 2 points) Important timing constraints for a D flip flop are the setup time and the hold time. Give a brief explanation of both timing constraints. Set up time Setup time is the minimum amount of time the data signal should be held steady before the active edge of clock. Hold time Hold time is the minimum amount of time the data signal should be held steady after the active edge of clock. Page 2 of 10

3 Question 4 (0,5 + 0,5 + 1 = 2 points) a) What is the 2 s complement representation of decimal -9 (use 8 bits for the representation)? b) What is the decimal value of bit pattern 0101 (1 s complement is used)? 5 c) Given is a normalized floating point representation in base 2. The bit pattern from left to right is: - Sign bit: 1 bit (1 is negative, 0 is positive), - Exponent field: 5 bits in excess 10, - Fraction field: 6 bits (not included is the hidden bit). Point is left of hidden bit. When the exponent field is filled with all zeros, the representation is not normalized. In that case the decimal number 0 is represented, independent of the sign and fraction field. What is the decimal value of the bit pattern: (spaces are added for readability) -2^5 x 0,75= - 24 Page 3 of 10

4 Question 5 (1 points) What is the machine code (in hexadecimal format) of the ARC instruction: andcc %r1, 2, %r Question 6 (2 + 1 = 3 points) Given is a program in assembly with an array series that contains signed numbers. Each number is 32 bits. The end of the array is indicated with the integer value 0..begin.org 0 sethi series,%r1 srl %r1,10,%r1! %r1 contains address of label series. addcc %r0, 0, %r11! %r11 bevat %r11 lp: ld [%r1], %r10 addcc %r10,%r0,%r0! check zero be rdy addcc %r10,%r10,%r10! %r10=2x%r10 st %r10, %r1 nxt: addcc %r1,4,%r1! %r1 = %r1 + 4 ba lp rdy: halt series: 1,-6,2,-5,3,4,0.end a) After this program is executed, what are the changes in main memory? the elements of the array are doubled: 2, -12,4, -10, 6, 8, 0 b) In the program above you have the instruction: lp: ld [%r1], %r10 At what memory address in main memory is this instruction stored? (use decimal representation) 12 Page 4 of 10

5 Question 7 (2 + 1 = 3 points) a) Complete the given state table below for this synchronous system. Name and encoding of the states is: S00 encoding of this state is F0=0, F1=0 S01 encoding of this state is F0=0, F1=1 S10 encoding of this state is F0=1, F1=0 S11 encoding of this state is F0=1, F1=1 Present Next state Output Y State X X X X S00 S00 S S01 S00 S S10 S11 S S11 S11 S b) Give a minimal SOP form for the data input of flip-flop F1 (i.e. DF1=f(X, F1, F0) ) DF1 = F0. Page 5 of 10

6 Question 8 ( = 3 points) address A Amux B Bmux C Cmux Rd Wr ALU Cond Jump addr start address %r0 0-1 %temp ORN next - %temp %temp INC(A) next %temp ADDCC Jump 2047 The ARC processor is extended with the instruction FUN. For this instruction the bit pattern of the OP field is 10 and the bit pattern of OP3 field The number representation is twos complement. FUN %rx, %ry, %rz with rs1=%rx, rs2=%ry and rd=%rz a) What is the start address of this instruction in the microstore (decimal) 1752 b) Give an RTL description of the function FUN ( rd=f(rs1,rs2) ) rd rs1 - rs2 (evt ook nog goto 2047). c) Assume the content of %r2 is decimal 2, %r1 is decimal 1 and %r0 is decimal 0. What is the content of these registers after FUN %r2, %r1, %r0 is executed? %r2 = 2 %r1 = 1 %r0 = 0 Page 6 of 10

7 Question 9 (3 x 1 = 3 points) a) Mention at least three elements of the von Neumann model of a digital computer. Memory unit, Input Unit, Output Unit, Arithmetic Logic Unit and Control Unit. b) On what characteristics of typical programs is the memory hierarchy based? Temporal and spatial locality. Speed versus size c) How many addressable words does the chip below have? 1K or 1024 Or 256 words (due to the word in the assignment). Page 7 of 10

8 Question 10 (4 x 0,5 = 2 points) A computer must service three devices whose interrupting frequencies, service times, and assigned priorities are given in the table below. Device Service time Maximum Frequency Priority D1 20 ms 1/(200 ms) 3 (highest) D2 10 ms 1/(100 ms) 2 D3 80 ms 1/(800 ms) 1 (lowest) a. Assuming a strong priority system (interrupts are enabled during interrupt handling), compute for each device the maximum time between service request and the completion of service for that device. D1: 20.ms (D1 does not have to wait) D2: 30 ms (D1 is busy (wait max 20ms) and 10ms for D2) D3: 120 ms (i.e. t=0ns req of D2 and D2; after 10 ns start D1; so at t 30ns D3 starts execution; at time 100ns (70ns is exectued of D3) again req D2 (worst case) hence after from 100 to 110 ns D2 executes and at 110 ns D3 continues with 10ns 120ms ) b. Assume that all the interrupts listed in the table above occur at their maximum frequency. What percentage of the processor's time is used to service interrupts? 30 % (5 x 20 ms + 10 x 10 ms + 1,25 x 800 ms = 300 ms per sec) Page 8 of 10

9 Question 11 (2 + 2 = 4 points) An embedded microcontroller is used for controlling a heating system. The microcontroller has 16 address pins (A15 - A0), an 8 bit data bus and makes use of I/O-mapped I/O. For selecting the memory space, the M/In is asserted (made high), for selecting the I/O space, M/In is deactivated (made low). The memory system consists of ROM and RAM according the following specifications: ROM: RAM: 32K Bytes at the lowest addresses of the address range 2K Bytes at the highest addresses of the address range. Shadowing is not allowed. The select lines for these areas are respectively SelROM and SelRAM. These select lines are a function of a selection of address lines and the signal M/In. a) Give the minimal expression for SelROM (as a function of the addresslines and M/In). SelROM =!A15&M/In b) Give the expression for SelRAM (as a function of the addresslines and M/In). SelRAM = A15&A14&A13&&A12&A11M/In Page 9 of 10

10 Question 12 ( = 4 points) A 32-bits microprocessor has an on-chip primary cache with the following characteristics: Address space: Primary cache: 4 GB, Byte-addressing Size: 2 MB (excluding tags) Slot size: 128 B Organisation: 8-way set-associative For the primary cache, a byte-address is split into parts that are used for, respectively, comparison with the tag in the cache, selection of a set in the cache, selection of a word in a slot and selection of a byte in a word. Which bit numbers belong to each of these parts? tag set in cache 17-7 word in slot 6-2 byte in word 1-0 Question 13 (2 x 0,5 = 1 point) A processor is connected to byte-addressable 2 16 byte memory via a 16 bit, little endian databus. a) On what datalines of the databus (D15 D0) is the byte on memory location 3FAD Hex transported on the bus? Write your answer in the format Dx - Dy where x and y correspond with the numbers of the datalines. D15-D8 3FAD; D 1101 odd address 15-8 b) Is the datastructure that occupies the addresses 2345 Hex to 2346 Hex aligned? Explain your answer. Aligned? (yes/no): No Explanation: First address should be even; or bit pattern address xxx xxx0110 Red part of address should be equal Page 10 of 10

1 The ARC processor (data path and control)

1 The ARC processor (data path and control) 1 The ARC processor (data path and control)... 1 1.1 Introduction... 2 1.2 Main part of data path... 2 1.3 Data path... 2 1.4 Controller... 3 1.4.1 Micro instruction