ECEN : Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University. Homework #1 Solutions

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1 ECEN : Microprocessor System Design Department of Electrical and Computer Engineering Texas A&M University Homework #1 Solutions Upload your homework solution to ecampus as a single pdf file. Your homework solution should include a listing of any C code or Verilog code, along with any output obtained when the code is run. DO NOT include pictures of your code in your homework solution file, instead, copy the text of your C or Verilog code into your homework solution file. DO NOT upload a zip file. You will have only ONE attempt to upload your homework solution. In addition, your source code (any C code or Verilog code or testbenches) should be sent via to 449and749graders@gmail.com. Your title should state your NAME, SECTION NUMBER and HOMEWORK NUMBER. Name your files in a way that identifies the homework number and the question (e.g. hw1-q1b.v). For all the code that you write, please provide comments for full credit. 1. Write a C program that reads a character string from an input file. Your program performs Run Length Encoding on the input string (as shown below). The result is written to an output file. The input filename should be IN.txt and the output filename should be OUT.txt. Both these files contain exactly one line with no spaces. For example if the input file contains ppaaaarttt then output file should contain p2a4r1t3 Test your code on the following strings: (a) qqqyyyyhiiiqyi (b) Solution. #include <stdio.h> 1

2 2 Solutions to Homework #1 int main() { char str[100]; int count=1; int i; //read string from input file to str FILE * input; input = fopen("in.txt", "r"); fscanf(input,"%s",str); fclose(input); //write the run length encoded string to output file FILE * output; output = fopen("out.txt","w"); for(i=0;str[i];i++){ if(str[i]==str[i+1]){ count++; } return 0; } } else if (str[i]!=str[i+1]){ fprintf(output,"%c%d",str[i],count); count=1; } fclose(output);

3 3 Solutions to Homework #1 2. Consider an input clock signal CLK which operates at 20 MHz. Also consider a signal IN which is 4 bits wide, changing at every positive edge of CLK. Write Verilog code whose output is the signal OUT and the signal CLK OUT shown below. Your code effectively samples IN at the falling edge of CLK, and drives out every alternate value to the OUT signal. Write a testbench to simulate your code. Test your code for 16 clock cycles of the CLK signal, with the input IN = 0000 for the first clock cycle, 0001 for the second cycle, and so on. CLK IN CLK_OUT OUT XXXX Waveform for Question 2 Solution. //Verilog code module downsampler(clk_out, OUT, IN, reset, CLK); input CLK; input reset; input [3:0] IN; output CLK_OUT; output [3:0] OUT; reg[3:0] buff, OUT; reg CLK_OUT; //top entity //latch input data and generate CLK_OUT

4 4 Solutions to Homework #1 (posedge CLK) begin buff <= IN; CLK_OUT <=!CLK_OUT; //assign OUT at negative edge of CLK and CLK_OUT == 1b1 (negedge reset) begin if(!reset) CLK_OUT <= 1 b0; always@ (negedge CLK) begin if(clk_out == 1 b1) begin OUT <= buff; module //Testbench module downsampler_test(); wire CLK_OUT; wire[3:0] OUT; reg CLK; reg[3:0] IN; reg reset; //port mapping downsampler dut(.clk(clk),.reset(reset),.in(in),.clk_out(clk_out),.out(out)); //generate input clock of 20 MHz CLK=0; forever begin CLK = #25 CLK; $monitor("in = %d OUT = %d", IN, OUT); //inital the IN signal reset = 1 b0; IN = 4 b1111;

5 5 Solutions to Homework #1 CLK ) begin IN = IN + 4 b0001; module //simulate the input signal 3. Design an 8-function ALU that accepts 4-bit inputs a and b, a 3-bit input signal select, and produces a 5-bit output out. The ALU implements the following functions based on 3-bit input signal select select signal function b000 out = (a b) (bitwise OR operation) 3 b001 out = a+b 3 b010 out = a-b 3 b011 out = a/b 3 b100 out = a%b (remainder) 3 b101 out = a << 1 3 b110 out = (a b) (magnitude comparison) 3 b111 out = (a & b) (bitwise AND operation) You must simulate all these eight functions using a testbench. For each of these functions, test the design for 9 values in all (a = 3, 2, 1 and b = 1, 2, 3.) Solution. //Verilog code module ALU(out, A, B, select); input [3:0] A; input [3:0] B; output [4:0] out; input [2:0] select; //SELECT signal reg [4:0] out; // Arithmetic operations based on SELECT signal always@(a or B or select) begin case(select) 3 b000:

6 6 Solutions to Homework #1 out = (A B) ; 3 b001: out = A+B; 3 b010: out = A-B; 3 b011: out = A/B; 3 b100: out = A%B; 3 b101: out = A<<1; 3 b110: out = (A>=B); 3 b111: out = (A & B); default: out = 5 b11111; case module //Testbench module ALU_TEST; wire [4:0] out; reg [3:0] a; reg [3:0] b; reg [2:0] select; reg clk; ALU ALU_test(out,a,b,select); //port mapping clk = 1 b0; forever begin clk = #50 clk; a <= 4 b0000; b <= 4 b0000;

7 7 Solutions to Homework #1 select <= 3 b000; always@(posedge clk) begin //a varies from 1 to 3 a <= (a == 4 b0011)? 4 b0001 : (a + 4 b0001); //b varies from 1 to 3 but changes only when a is 3 b <= (a == 4 b0011)? ((b == 4 b0011)? 4 b0001 : (b + 4 b0001)) : b; // selecte varies from 0 to 7 but changes only when a is 3 and b is 3 select <= (b == 4 b0011 && a == 4 b0011)? (select + 3 b001) : select; module 4. Consider a 12 bit serial data string DAT, which arrives at 10 Mbps. Write Verilog code to count the maximum number of occurrences of 101 in DAT. Simulate the Verilog code using a testbench, using the following values of DAT: (a) (b) (c) Solution. //Verilog code timescale 1ns / 1ps module patterncounter( //top entity input clk, input IN, input reset, output[3:0] count, output[1:0] st ); reg[3:0] count; reg[1:0] nextstate; reg[1:0] state; reg[1:0] st; //to observe state transitions

8 8 Solutions to Homework #1 reg tick; //initialize states localparam a = 2 b00; localparam b = 2 b01; localparam c = 2 b10; always@ ( posedge clk or posedge reset) begin if(reset) begin state <= a; count <= 4 b0000; else if(clk) begin state <= nextstate; always@( IN or state ) begin //state machine st <= state; tick <= 1 b0; case(state) a: begin if(in) nextstate = b; else nextstate = a; b: begin if( IN) nextstate = c; else nextstate = b; c: begin if(in) begin nextstate = b; tick = 1 b1; else nextstate = a; default: begin state = a; case

9 9 Solutions to Homework #1 //count the number of occurrences of the pattern "000" in the input sequence tick) begin count = count+ 4 b0001; module //Testbench timescale 1ns / 1ps module patterncounter_test(); wire[3:0] count; wire[1:0] st; reg clk,in,reset; patterncounter DUT(.clk(clk),.IN(IN),.reset(reset),.count(count),.st(st)); clk = 1 b0; forever begin clk = #50 clk; reset = 1 b1; #50 reset = 1 b0; $monitor($time,"count = %d, State= %d",count,st); IN <= 1 b0; #100 IN <= 1 b1; #100 IN <= 1 b0; #100 IN <= 1 b1; #100 IN <= 1 b0;

10 10 Solutions to Homework #1 #100 IN <= 1 b1; #100 IN <= 1 b0; #100 IN <= 1 b0; #100 IN <= 1 b1; #100 IN <= 1 b1; #100 IN <= 1 b0; #100 IN <= 1 b1; module 5. Write Verilog code to implement a Finite State Machine (FSM) represented by the State Transition Table given below. In the State Transition Table, clk is the clock variable, indicates rising edge of the clk, a is an input, PS is the Present State, NS is the Next State and z is the output variable. clk PS a NS z S 1 0 S 3 0 S 1 1 S 2 1 S 2 0 S 3 1 S 2 1 S 4 0 S 3 0 S 4 0 S 3 1 S 1 1 S 4 0 S 4 1 S 4 1 S 1 1 Simulate the Verilog code using a testbench. In your testbench, consider you start at state S 1 and a is driven by the successive values of the 8 bit long string, , which arrives at 1 Mbps. The leftmost bit of the string is fed to the FSM first. Solution. Each edge in Fig 1 is labeled in the form a/z, where a is an input and z is the output as given in the question.

11 11 Solutions to Homework #1 1/1 S 2 0/0 S 1 1/0 0/1 S 3 1/1 0/0 1/1 S 4 0/1 Fig 1 : State Diagram representation of the State Transistion Table //Verilog Code module fsm( input clk, input a, output z, output[1:0] PS, input reset ); reg[1:0] PS; reg[1:0] NS; reg z; reg dz; // present state // next state // output //initialize states localparam S1 = 2 b00; localparam S2 = 2 b01;

12 12 Solutions to Homework #1 localparam S3 = 2 b10; localparam S4 = 2 b11; always@( posedge clk ) begin if(reset) begin PS <= S1; z <= 0; else begin PS <= NS; // updating present state z <= dz; // updating the output always@(a or PS) begin //state machine case(ps) S1: begin if(a) begin NS = S2; dz = 1; else begin NS = S3; dz = 0; S2: begin if(a) begin NS = S4; dz = 0; else begin NS = S3; dz = 1; S3: begin if(a) begin NS = S1; dz = 1; else begin NS = S4; dz = 0; S4: begin if(a) begin NS = S1; dz = 1; else begin NS = S4; dz = 1; default: begin NS = S1; dz = 0; case module

13 13 Solutions to Homework #1 //Testbench module fsm_tb(); wire z; wire[1:0] PS; reg clk, a, reset; fsm DUT(.clk(clk),.a(a),.reset(reset),.z(z),.PS(PS)); //clock signal clk = 1 b0; forever begin clk = #500 clk; //reset reset = 1 b1; #1000 reset = 1 b0; // input stream to a $monitor($time,"z = %d, PS = %d ",z, PS); #1000 a <= 1 b1; #1000 a <= 1 b1; #1000 a <= 1 b0; #1000 a <= 1 b0; #1000 a <= 1 b1; #1000 a <= 1 b0; #1000 a <= 1 b1; #1000 a <= 1 b1;

14 14 Solutions to Homework #1 module 6. [GRADUATE QUESTION] Consider a logic circuit with N gates with no structural feedback. I perform event driven timing simulation on it up to K seconds. The delays of all gates are unity, and the circuit inputs change exactly once at time 0 seconds. What is the maximum number of events that are generated in the timing simulation? Solution. Consider a two-level logic circuit with N gates as shown in Fig 2. Let there be N-1 gates in the first level, the output of which are connected to the gate in the second level. If I perform an event driven timing simulation on it up to K seconds (assuming K>0), then, the number of events generated in the timing simulation is O(N) since there are N gates in the two-level logic circuit. IN_1 1 IN_ n OUT IN_N 1 n 1 Fig 2: A two-level logic circuit

15 15 Solutions to Homework #1 Now consider a circuit given in Fig 3. The number inside a gate is its label. IN_1 IN_2 1 E1 IN_3 2 E1, E2 IN_4 3 E1, E2, E3 (Upto IN_N+1) Fig 3: Circuit for explaining events generated (Upto Nth gate) Let us assume N =3, (K>N) and then calculate the total number of events. (a) At time 0, the inputs of the circuit change. This change generates events at the outputs of all 3 gates which would be processed after delays of the respective gates. (b) Since the delay of each gate is 1, an event will be generated at the ouput of all 3 gates which will be processed at 1. Lets call this event E1. Similary an event generated that would be processed at time 2 would be E2 and so on. (c) At time 1, the E1s at the ouputs of all 3 gates will be processed in no specific order. After processing of E1 at the output of gate 1, it will generate another event to be processed at time 2 at the ouput of gate 2 which is E2. Similarly, processing of E1 at the output of gate 2 will generate E2 at the ouput of gate 3. And processing E1 at the output of gate 3 will not generate any events since it is not connected to the input of any other gates. (d) At time 2, the E2s will be processed. After processing event E2 at the output of gate 2, it will generate an event E3 at the output of gate 3. (e) So when K>N, 3 events (E1) were generated at time 0, 2 events (E2) were generated at time 1, 1 event (E3) was generated at time 2. Total Number of events is 6. (f) Generalising, for K>N, the total number of events generated would be N (N + 1)/2. Similarly, for circuit Fig 3, if K<N, N events (E1) will be generated at time 0, N-1 events (E2) at time 1, and so on. Finally, at time K, N-K events would be generated. So, the total number of events would be (N K) (N K + 1)/2. Concluding, T otal Number of events = max(o(n), N (N + 1)/2, (N K) (N K + 1)/2)