Counters and Simple Design Example
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1 ECE 322 Digital Design with VHDL Counters and Simple Design Example Lecture 2
2 extbook References n Sequential Logic Review Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2 nd or 3 rd Edition Chapter 7 Flip-flop, Registers, Counters, and a Simple Processor n In this lecture, we learn how to implement basic sequential blocks using VHDL Counters n Example of digital system that make use of sequential logic blocks
3 Counters
4 Asynchronous Counters Up-Counter with Flip-Flops Clock 2 (a) Circuit Clock 2 Count (b) iming diagram A three-bit up-counter
5 Asynchronous Counters Down-Counter with Flip-Flops Clock 2 (a) Circuit Clock 2 Count (b) iming diagram A three-bit down-counter
6 Synchronous Counters Synchronous Up-Counter with Flip-Flops Clock cycle changes 2 changes Derivation of the synchronous up-counter
7 Synchronous Counters Synchronous Up-Counter with Flip-Flops Clock 2 3 (a) Circuit Clock 2 3 Count (b) iming diagram A four-bit synchronous up-counter
8 Counters with Enable & Clear Synchronous Up-Counter with Enable & Clear Inputs Enable Clock Clear
9 VHDL Code for a 4-bit Up-Counter with Reset & Enable LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std logic unsigned.all ; ENIY upcount IS POR (Clock, Resetn, Enable : IN SD_LOGIC ; : OU SD_LOGIC_VECOR(3 DOWNO ) ) ; END upcount; ARCHIECURE behavioral OF upcount IS SIGNAL Count : std_logic_vector(3 DOWNO ); BEGIN PROCESS ( Clock, Resetn) BEGIN IF Resetn = HEN Count <= "" ; ELSIF rising_edge(clock) HEN IF Enable = HEN Count <= Count + ; ELSE Count <= Count ; END IF ; END IF; END PROCESS; <= Count; END behavioral; Enable Clock Resetn 4 upcount
10 Design Example
11 Design Example: Bus Structure A digital system with k n-bit registers
12 Design Example: Bus Structure Details for connecting registers to a bus
13 Design Example: Bus Structure Using a shift register for control
14 Design Example: Bus Structure VHDL Code for an n-bit register LIBRARY ieee ; USE ieee.std_logic_64.all ; ENIY regn IS GENERIC ( N : INEGER := 8 ) ; POR ( R : IN SD_LOGIC_VECOR(N- DOWNO ) ; Rin, Clock : IN SD_LOGIC ; : OU SD_LOGIC_VECOR(N- DOWNO ) ) ; END regn ; ARCHIECURE Behavior OF regn IS BEGIN PROCESS BEGIN WAI UNIL Clock'EVEN AND Clock = '' ; IF Rin = '' HEN <= R ; END IF ; END PROCESS ; END Behavior ;
15 Design Example: Bus Structure VHDL Code for an n-bit tri-state buffer LIBRARY ieee ; USE ieee.std_logic_64.all ; ENIY trin IS GENERIC ( N : INEGER := 8 ) ; POR ( X : IN SD_LOGIC_VECOR(N- DOWNO ) ; E : IN SD_LOGIC ; F : OU SD_LOGIC_VECOR(N- DOWNO ) ) ; END trin ; ARCHIECURE Behavior OF trin IS BEGIN F <= (OHERS => 'Z') WHEN E = '' ELSE X ; END Behavior ;
16 Design Example: Bus Structure VHDL Code for the shift register LIBRARY ieee ; USE ieee.std_logic_64.all ; ENIY shiftr IS -- left-to-right shift register with async reset GENERIC ( K : INEGER := 4 ) ; POR ( Resetn, Clock, w : IN SD_LOGIC ; : BUFFER SD_LOGIC_VECOR( O K) ) ; END shiftr ; ARCHIECURE Behavior OF shiftr IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '' HEN <= (OHERS => '') ; ELSIF Clock'EVEN AND Clock = '' HEN FOR i IN K DOWNO 2 LOOP (i) <= (i-) ; END LOOP ; () <= w ; END IF ; END PROCESS ; END Behavior ;
17 Design Example: Bus Structure Package and component declarations PACKAGE components IS COMPONEN regn -- register GENERIC ( N : INEGER := 8 ) ; POR ( R : IN SD_LOGIC_VECOR(N- DOWNO ) ; Rin, Clock : IN SD_LOGIC ; : OU SD_LOGIC_VECOR(N- DOWNO ) ) ; END COMPONEN ; COMPONEN shiftr -- left-to-right shift register with async reset GENERIC ( K : INEGER := 4 ) ; POR ( Resetn, Clock, w : IN SD_LOGIC ; : BUFFER SD_LOGIC_VECOR( O K) ) ; END component ; COMPONEN trin -- tri-state buffers GENERIC ( N : INEGER := 8 ) ; POR ( X : IN SD_LOGIC_VECOR(N- DOWNO ) ; E : IN SD_LOGIC ; F : OU SD_LOGIC_VECOR(N- DOWNO ) ) ; END COMPONEN ; END components ;
18 Design Example: Bus Structure VHDL code for a circuit that swaps the contents of two registers LIBRARY ieee ; USE ieee.std_logic_64.all ; USE work.components.all ; ENIY swap IS POR (Data : IN SD_LOGIC_VECOR(7 DOWNO ) ; Resetn, w : IN SD_LOGIC ; Clock, Extern : IN SD_LOGIC ; RinExt : IN SD_LOGIC_VECOR( O 3) ; BusWires : INOU SD_LOGIC_VECOR(7 DOWNO ) ) ; END swap ;
19 Design Example: Bus Structure VHDL code for a circuit that swaps the contents of two registers ARCHIECURE Behavior OF swap IS SIGNAL Rin, Rout, : SD_LOGIC_VECOR( O 3) ; SIGNAL R, R2, R3 : SD_LOGIC_VECOR(7 DOWNO ) ; BEGIN control: shiftr GENERIC MAP ( K => 3 ) POR MAP ( Resetn, Clock, w, ) ; Rin() <= RinExt() OR (3) ; Rin(2) <= RinExt(2) OR (2) ; Rin(3) <= RinExt(3) OR () ; Rout() <= (2) ; Rout(2) <= () ; Rout(3) <= (3) ; tri_ext: trin POR MAP ( Data, Extern, BusWires ) ; reg: regn POR MAP ( BusWires, Rin(), Clock, R ) ; reg2: regn POR MAP ( BusWires, Rin(2), Clock, R2 ) ; reg3: regn POR MAP ( BusWires, Rin(3), Clock, R3 ) ; tri: trin POR MAP ( R, Rout(), BusWires ) ; tri2: trin POR MAP ( R2, Rout(2), BusWires ) ; tri3: trin POR MAP ( R3, Rout(3), BusWires ) ; END Behavior ;
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