CISC Processor Design

Transcription

1 CISC Processor Hardware Flowchart Virendra Singh Indian Institute of Science Bangalore Lecture 4 SE-273: Processor

2 Processor - Block Diagram Clock-Phase Reset & Power-On Logic Generator Bus Controller Interrupt Logic Control Store Next State Control Branch Control unit IR Decoder Encoded Control Word Fields Control Word Decoder Decoded d Datapath Control Instruction Prefetch Register Address Out Reg. PC R0 R1 Internal A Bus Rn Shifter ALU Internal B Bus Datapath Data Reg. Jan 19, 2011 SE-273@SERC 2

3 Hardware Flowchart Hardware Flowchart Tells us how to get from the architecture to the implementation i Links programmer s (external) model and the hardware (internal) implementation Specify exactly how commands from the instruction set are carried out using Datapath Jan 19, 2011 SE-273@SERC 3

4 Hardware Flowchart Pre-requisites: ii Instruction set summary Instruction Format Operations Addressing modes Registers Datapath Programmer s register set Additional registers ALU and any special functional units Internal data paths Rules of operation Datapath will evolve Jan 19, 2011 SE-273@SERC 4

5 Development of Implementation Clock Phase Generator Datapath The architecture t specification is the only input Begin with a guess of Datapath Do flowchart for the instructions This modifies and refines the Datapath and develops the control store and control strategy The final Datapath is derived output Jan 19, 2011 SE-273@SERC 5

6 Development of Implementation Clock Phase Generator Control Store Control Word Once flowcharts are fairly complete, derive the control word format using the flowchart states When the flowcharts are complete, so is the Datapath Control word format is derived output Datapath Jan 19,

7 Development of Implementation Clock Phase Generator Control Store After defining control word format, you assign bit patterns to the control fields in a way that minimizes control word decoders between the control store and the Datapath Control Word Decoder Datapath Jan 19, 2011 SE-273@SERC 7

8 Development of Implementation Clock Phase Generator Control Store Instruction Decoder Instruction decoders are defined the flowcharts and the architecture specification Control Word Decoder Datapath Jan 19,

9 Development of Implementation Clock Phase Generator Control Store Bus Controller Instruction Decoder Completed flowchars, control word format, and the initial bus specification defines the bus controller Control Word Decoder Datapath Jan 19,

10 Development of Implementation Clock Phase Generator Control Store Control Word Decoder State Sequencer Datapath Bus Controller Instruction Decoder Last is the logic of the state sequencer, the part of the chip that says what to do next (where is the next control word?) Once every thing around it is defined, you build exactly what you need! (The state sequencer is derived output) Jan 19,

11 Flowchart Objective Flowchart Objective Limit controller size to some fraction of chip area Make CPU as fast as possible Complete the project as early as possible Make the flowcharts easy to translate into hardware Jan 19,

12 MIN Instruction ti Set Instruction Format First Word Op-code Rx Mode Ry Operation First Second First Code Operand Register Second Word Operand Address Mode Displacement st Operand Register Optional, depending on second operand address mode Programmer s Register Set R0 R1 R2... Rn Jan 19, 2011 SE-273@SERC 12

13 MIN Instruction ti Set MIN Instruction Set ADD AND BZ Branch if zero bit is set. (Register Indirect only) LOAD Second operand is source and Rx is destination POP Postincrement with register indirect only PUSH Predecrement with register indirect only STORE SUB TEST Jan 19,

14 MIN Instruction ti Set Second Operand Address Mode Second Operand Address Mode Ry First Operand Register Address Modes AB - Base (Ry) plus displacement (second instruction word) is an operand address AI Register indirect. Ry holds an operand address AR Register direct: The result is stored in Ry. For two operand dinstructions, ti Ry also is an operand source Jan 19, 2011 SE-273@SERC 14

15 MIN Datapath th IRE IRF Internal A Bus DO AO PC T2 R0 R1 Rn T1 ALU k Internal B Bus DI External Address Bus (EAB) External Data Bus (EDB) Jan 19, 2011 SE-273@SERC 15

16 MIN Datapath th Rules of Operation 1. A transfer from source to bus to destination takes one state time 2. A source can drive up to three destination loads 3. Inputs to the ALU are from A (internal) bus and either k (values 0, +1, -1) or the B (internal) bus 4. When ALU is destination. Ti is automatically loaded from the ALU output 5. A transfer to AO activates the on-chip external bus controller. This bus controller postpones the next state until the external transfer is complete. Jan 19, 2011 SE-273@SERC 16

17 Flowcharts ADD RX AR RY ADD RX AI (RY) Register-to-Register Register-to-Memory R R ADD R M ADD rx a alu ry b alu edb di ry b ao State t1 b ry di b alu rx a alu Sequence IRE Internal AO PC T2 R0 R1 A Bus Rn T1 ALU Internal B Bus k IRF DO DI ry b ao t1 a do Jan 19, 2011 SE-273@SERC 17

18 Flowcharts ADD RX AR RY Register-to-Register R R edb if irf pc b ao rx a alu ry b alu t1 b ry pc a alu +1 alu t1 b pc ADD ADD RX AI (RY) Register-to-Memory R M ADD edb irf pc b ao edb di ry b ao di b alu rx a alu ry b ao t1 a do pc a alu +1 alu t1 b pc Execution Speed Jan 19, 2011 SE-273@SERC 18

19 MIN Datapath th IRE IRF Internal A Bus DO AO PC T2 R0 R1 Rn T1 ALU k Internal B Bus DI External Address Bus (EAB) External Data Bus (EDB) Jan 19, 2011 SE-273@SERC 19

20 Level 1 Flowchart - ADD ADD RX AR RY Register-to-Register R R ADD rx a alu ry b alu edb irf pc b ao pc a alu +1 alu t1 b ry irf ire t1 b pc IRE IRF Operation tasks Housekeeping tasks Internal AO PC T2 R0 R1 A Bus Rn T1 ALU Internal B Bus (EAB) DO k DI (EDB) Jan 19, 2011 SE-273@SERC 20

21 Thank You Jan 19,