ADVANCED DIGITAL IC DESIGN. Verilog Simulation Techniques (I)

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1 1 ADVANCED DIGITAL IC DESIGN (SESSION 7) Verilog Simulation Techniques (I)

2 Simulation Algorithms 2 There are three broad categories of simulation algorithms: Time-based used by SPICE simulators Event-based used by many HDL simulators like ModelSim Cycle-based used by many simulators like SpeedSim

3 Simulation Algorithms (Continued) 3 Time-based simulation algorithms evaluate the entire circuit on a periodic basis. These algorithms are suitable for simulation of analog circuits, but are inappropriate for simulation of digital circuits having very little activity at any given time step. Event-based simulation algorithms process only the changes in circuit state. The simulation propagates values forward, through the circuit, in response to input pin events or autonomous event generators (such as clocks). These algorithms efficiently simulate digital circuits, especially circuits in which events do not propagate far. Cycle-based simulation algorithms evaluate activated portions of the circuit when a trigger input changes. A trigger is any input that can immediately or eventually cause an output change. These algorithms efficiently simulate synchronous circuits, but are inappropriate for circuits with components that internally generate their own events, such as clocks, one-shots, and phase-locked loops. The essential difference between event and cycle simulation i is that event simulation i "pushes"events through the design, iteratively calculating node states, until the design state settles, while cycle simulation calculates the design state "as a whole" only once for each external trigger. Cycle simulation in this way acts much as a hardware modeler would.

4 4 Event-Based Simulation

5 Event-Based Simulation (Continued) 5 The simulator starts at simulation i time 0. The simulator processes all events on the current time queue, then advances to the next queue. While processing events in the current queue, the simulator can add events to the current and future queues. The interval between time queues can be as low as the simulation time precision and as large as software and hardware limitations i i permit. The total number off uture time queues varies during simulation, and can be as low as 0 (at the end) and as numerous as software and hardware limitations permit.

6 6 Event Simulation of a Verilog Model Event simulation of Verilog designs takes the following steps: 1. Compilation: The simulator reads the design description, processes compiler directives, and builds a data structure that defines the design hierarchy. This step is sometimes separated into two steps: compilation and elaboration. 2. Initialization: The simulator initializes module parameters, sets other storage elements to the unknown (X) state, and sets un-driven nets to the high-impedance (Z) state. When simulation commences at time zero, the simulator propagates these changes and executes the statements in each initial and always block up to a timing control. 3. Simulation: The simulator processes events on the current time queue. This can add more events to the current and future time queues. The simulator processes all events on the current time queue, then advances simulation time to the next time queue. The simulator terminates when no future events exist.

7 7 Modeling a Test Bench

8 8 Verilog HDL Simulation Commands The Verilog HDL includes compiler directives and system tasks to control the simulation of Verilog models `<directive> compiler directives Executed prior to simulation time zero Instructions to simulators on how to compile models Always start with a ` accent grave (the back tic ) $<task> system tasks Executed during simulation (i.e.: to display values) Used as programming statements Always start with a $ dollar sign

9 Compiler Directives 9 The following is a list of keywords frequently used by Verilog simulators for specifying compiler directives.

10 Accessing Simulation Time 10 Use $time, $realtime, or $stime to obtain the current simulation time: $time returns time as a 64-bit unsigned integer $stime returns time as a 32-bit unsigned integer $realtime returns time as a real number Each of these system functions returns a value that is scaled to the time unit of the module that invoked it.

11 11 Time Format

12 12 Displaying Signal Values

13 13 Displaying Signal Values

14 14 Displaying Signal Values

15 15 Monitoring Signal Values

16 16 Monitoring Signal Values (Continued) The $monitor system task continually monitors its signal arguments, and displays the formatted arguments at the end of each simulation time instant in which any of the signal arguments changes value. The change of simulation time does not trigger a display. You can have only one $monitor system task active. Any subsequent invocation of $monitor starts monitoring the new signal arguments and discontinues monitoring the previous signal arguments. You can use the $monitoroff and $monitoron system tasks to restrict monitoring to intervals of time, rather than monitoring the entire remainder of the simulation session. The $monitor system task accepts the same formatters and argument list as $display. The $monitor system tasks support multiple default radixes. The default is decimal. Use $monitorb, $monitorh, and $monitoro for binary, hexadecimal, and octal (respectively).

17 File I/O (Verilog-2001) 17 This is one of the good features that was added d to Verilog In Verilog 1995, file IO was limited to reading hex files into memory array using readmemh and writing file using $display and $monitor. But in Verilog 2001, following operations can performed. C or C++ type file operation (like checking end of file). Reading characters from file from a fixed location. Reading a formatted lines in file. Wii Writing a formatted lines into file.

18 Opening And Closing a File A file can be opened for reading or writing, and the syntax is as below: file = $fopen("filename",r); // For reading file = $fopen("filename",w); // For writing Below table shows all the possible $fopen modes: r or rb w or wb a or ab r+, r+b, or rb+ w+, w+b, or wb+ Open for reading Truncate to zero length or create for writing Append (open for writing at end of file) Open for update (reading and writing) Truncate or create for update a+, a+b, or ab+ Append; Open or create for update at end-of-file fil A file can be cloased as below: $fclose(file); // Here file is the handle which was assigned with $fopen 18

19 Reading data from a file 19 Verilog 2001 FileIO supports fll following ways of reading a file. Reading a character at a time with $fgetc. Reading a line at a time with $fgets. Reading formatted data with $fscanf. The $fscanf function reads characters from the file specified by the file descriptor, interprets them according to a format, and stores the results in its arguments. Reading binary data with $fread. The $fread function reads binary data from the file specified by the file descriptor into a register or into a memory.

20 File I/O (example) 20 module fileio; // DUT input driver code // DUT model integer in,out,mon; reg clk; reg enable; wire valid; reg [31:0] din; reg [31:0] exp; wire [31:0] dout; integer statusi,statuso; dut dut (clk,enable,din,dout,valid); initial begin clk = 0; enable = 0; din = 0; exp = 0; in = $fopen("input.txt","r"); out = $fopen("output.txt","r"); mon = $fopen("monitor.txt","w"); end initial begin repeat (posedge clk); while (!$feof(in)) (negedge clk); enable = 1; statusi = $fscanf(in,"%h (negedge clk); end enable = 0; end repeat (posedge clk); $fclose(in); $fclose(out); $fclose(mon); #100 $finish; // DUT output monitor and compare logic (posedge clk) if (valid) begin $fwrite(mon,"%h %h\n",dout[31:16],dout[15:0]); statuso = $fscanf(out,"%h %h\n",exp[31:16],exp[15:0]); if (dout!== exp) begin $display("%0dns Error : input and output does not match",$time); $display(" Got %h",dout); $display(" Exp %h",exp); end else begin $display("%0dns Match : input and output t match",$time); $display(" Got %h",dout); $display(" Exp %h",exp); end end module dut( input wire clk,enable, input wire [31:0] din, output reg [31:0] dout, output reg valid ); (posedge clk) begin dout <= din + 1; valid <= enable; end endmodule always # 1 clk = ~clk; endmodule

21 File I/O (results) 21 Input File Expected Output File a a a a a a a a4 045a 08a4045a 08a5 045b 08a5045b 08a6 045c 08a6045c 08a7 045d 08a7045d 08a8 045e 08a8045e 08a9 045f 08a9045f 08aa aa ab ab ac ac ad ad ae ae af

22 22 readmem File input

23 23 readmem File input (example)

24 readmem File input (continued) 24 In the memory data file: You can include both single-line and multi-line comments You can assign a starting address for subsequent The hexadecimal address must immediately follow character (no spaces) The hexadecimal address is not case sensitive You can specify binary ($readmemb) or hexadecimal ($readmemh) ASCII data You can specify 0, 1, Z, and X data values You can use underscores (_) to increase readability You can separate memory words by spaces and lines

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