Lab 1: Intro to Xilinx 14.7 Tools & Basic VGA CMPE 415 UMBC
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1 Lab 1: Intro to Xilinx 14.7 Tools & Basic VGA CMPE 415 UMBC Objective: The objective of this lab is to learn the fundamental components of the Xilinx FPGA tools required to enter and assemble HDL code using a schematic entry tool and program an FPGA (Artix-7). Intro: In this lab you will program an FPGA to display a rectangle on a monitor using a VGA cable. The color of the rectangle will depend on the configuration of the twelve switches located on the FPGA board. You will then modify the code provided for this tutorial to provide slightly different functionality, such as displacing the rectangle. NOTE: Before starting this homework, you must have finished Tutorial 2 (and Tutorial 1 if you are using your own ISE 14.7 software) to make sure you can create a project and program FPGA.
2 Equipment Needed: - Working computer with Xilinx ISE 14.7 installed - NEXYS4 DDR (Artix-7) FPGA board + USB Programming Cable - Second monitor - VGA cable Tutorial: 1. Start Xilinx Tool
3 2. In the ISE Project Navigator Window Create a New Project: File New Project 3. Name your project, setup directories, and set top-level source type.
4 3.1. If any _pn.exe error appears, perform the following steps: i) Open the following directory: C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64 ii) Find and rename libportability.dll to libportability.dll.orig iii) Make a copy of libportabilitynosh.dll (copy and paste it to the same directory) and rename it libportability.dll iv) Copy libportabilitynosh.dll again, but this time navigate to C:\Xilinx\14.7\ISE_DS\common\lib\nt64 and paste it there v) In C:\Xilinx\14.7\ISE_DS\common\lib\nt64 Find and rename libportability.dll to libportability.dll.orig vi) Rename libportabilitynosh.dll to libportability.dll 3.2. If any Licensing error appears, go to Help License Manager and make sure the following settings are configured:
5 4. Hit next and configure the Project Settings: 5. Click Next/Finish until the New Project Wizard window closes. 6. Click Project New Source
6 7. Select Verilog Module then continue to hit Next/Finish until the New Source Wizard window closes. 8. Add an Implementation Constraints File, continue to select Next/Finish until the New Source Wizard window closes, and copy the code provided in the Appendix D into its contents. (Mention which file)
7 9. Create two additional Verilog Module files, shown in the figures below, and copy the code provided in the Appendix B and C into their respective files. (mention which file to add)
8 10. Copy provided code for the top Verilog module (vgaproject.v) from the appendix A (mention the file name). Now edit the code to instantiate three modules( vgapulse Horizontal, vgapulse Vertical and clockdiv pixel). Please see the comments in the code to understand where you have to instantiate these modules. Example of instantiation: Usually module instantiation is done as follows, Module_name Instance_name (Port_Association_List). For example, you have declared a module as follows, module addbit (a,b,ci,sum,co); where a,b, ci are the inputs and sum,co are the outputs. Now you can instantiate this module to any other module as follows, addbit addbit1 ( a(0), b(1), ci(0), sum(sum), co(co) ); Remember in the parentheses we provide the values or variable name from where values are coming for the input or output variables. Now save the project. There should be three.v files and one.ucf file listed below the top module in the Hierarchy listing. Also at the end of the vgaproject module you will see a always block. In this always block you will see some values of x and y. According to the values of x and y the rectangle will be placed in the monitor. Think yourself how you can move the square in any place of monitor by changing the values of x and y. You can do this thing after completing the whole project also. The project hierarchy should be look like as below. Your project
9 should exactly match with this view. 11. Synthesize the program by first selecting the top Verilog Module file, expand Configure Target Device inside the Processes section (lower-left corner), right click Manage Configuration Project, then click Run 12. Make sure that there are minimal warnings and no errors shown after Synthesis is complete
10 13. Ensure that your device is connected to your computer. 14. An ISE impact window should appear. Double click on Boundary Scan and right click in the center of the white space, then select Initialize Chain.
11 15. Select Yes in response to assigning configuration files, then select the.bit file. 16. Then select No for the next pop-up request, and Cancel for the final pop-up.
12 17. Right click on the square that is now shown in the white space and select Program. You should momentarily see a Program Succeeded message appear at the bottom of the white space. 18. Make sure the VGA cable is properly connected to the FPGA and a different monitor than the one you are currently using. 19. With all the switches configured in the up-ward or on position, a white rectangle should appear at the bottom left of your second monitor:
13
14 Homework deliveries and report 1. Follow all the instructions and make sure the project is fully working on the FPGA board. 2. Show at least 6 different colors with different configuration of switches 3. Modify the top level vgaproject.v code, so the location of the square on monitor changes (ex. top right or top left). 4. Write a complete report to explain your design and how you found the numbers to move the square. Also in your report always mention on the first page if your design is Fully working and if it s not working upto which stage you could get it working.
15 APPENDIX A vgaproject.v module vgaproject(input clk, vgapulse Vertical vgapulse Horizontal input [3:0]r, input [3:0]g, input [3:0]b, output reg [3:0]red, output reg [3:0]green, output reg [3:0]blue, output VS, output HS, output vfree, output hfree); // System clk // input from switches // display on VGA // Vertical sync obtained from // Horizontal sync obtained from reg [3:0] free; wire [10:0] x,y; // Instantiate vgapulse Horizontal with clk = pixelclk, stage1 = 21 d96, stage2 = 21 d144, stage3 = 21'd784, endstage = 21'd800, syncpulse = HS, free = hfree and position = x // Instantiate vgapulse Vertical with clk = HS, stage1 = 21'd2, stage2 = 21'd35, stage3 = 21'd515, endstage = 21'd525, syncpulse = VS, free = vfree, position = y // Instantiate clockdiv pixel with div = 32'd4, out =pixelclk
16 always begin free[0]=hfree&&vfree&&(x<500)&&(x>450)&&(y<450)&&(y>400); Horizontal free[1]=hfree&&vfree&&(x<500)&&(x>450)&&(y<450)&&(y>400); Vertical free[2]=hfree&&vfree&&(x<500)&&(x>450)&&(y<450)&&(y>400); free[3]=hfree&&vfree&&(x<500)&&(x>450)&&(y<450)&&(y>400); // value of 'x' and 'hfree' obtained from vgapulse // value of 'y' and 'vfree' obtained from vgapulse red=r&free; green=g&free; blue=b&free; // if free show red on VGA // if free show green on VGA // if free show blue on VGA end endmodule APPENDIX B vgapulse.v module vgapulse(input clk, input [21:0]stage1, input [21:0]stage2, input [21:0]stage3, input [21:0]endStage, output syncpulse, output free, output [10:0]position); //96 for Horizontal & 2 for Vertical (Passed from top module) //144 for Horizontal & 35 for Vertical (Passed from top module) //784 for Horizontal & 515 for Vertical (Passed from top module) //800 for Horizontal & 525 for Vertical (Passed from top module) // Sync pulse HS or VS // singla indicating pixel can be passed to VGA port // position of the pixel
17 // Temporary registers reg [12:0] count; reg inc; reg[10:0] poscount; reg S0,S1,S2,S3; reg free_reg,sp; assign position=poscount; assign free=free_reg; assign syncpulse=sp; always begin inc=(count>endstage); S0<=(((count>21'd0) (count==21'd0))&&(count<stage1) (count==endstage)); S1<=(((count>stage1) (count==stage1))&&(count<stage2)); S2<=(((count>stage2) (count==stage2))&&(count<stage3)); // C > 144 or C = 144 && C < > free to display for 640 S3<=(((count>stage3) (count==stage3))&&(count<endstage)); end always@(negedge clk) begin free_reg<=s2; // free at S2 for displaying sp<=s1 S2 S3; // Syncpulse if either of S1,S2 or S3 are 1 end always@(posedge clk) begin case(free) // All always blocks run in parallel so this block will // check for updated status of free and inc at every posedge
18 end 0:posCount=0; 1:posCount=posCount+1; endcase case(inc) 1:count=0; 0:count=count+1; endcase endmodule APPENDIX C clockdiv.v module clockdiv(input clk, input [31:0]div, output reg out); reg [31:0] count; reg inc; reg max; // All Always blocks run in parallel don't get confused always begin // This block will execute continuously and will update 'inc' max=div>>1; inc=(count>max); end always@(posedge clk) begin
19 case(inc) 1:begin count=0; out=~out; end 0:begin count=count+1; end endcase end endmodule APPENDIX D introvga.ucf ## This file is a general.ucf for the Nexys4 DDR Rev C board ## To use it in a project: ## - uncomment the lines corresponding to used pins ## - rename the used signals according to the project ## Clock signal NET "clk" LOC = "E3" IOSTANDARD = "LVCMOS33"; Sch name = clk100mhz #NET "clk100mhz" TNM_NET = sys_clk_pin; #TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100 MHz HIGH 50%; #Bank = 35, Pin name = #IO_L12P_T1_MRCC_35, ## Switches NET "r<0>" NET "r<1>" NET "r<2>" NET "r<3>" NET "g<0>" LOC=J15 IOSTANDARD=LVCMOS33; #IO_L24N_T3_RS0_15 LOC=L16 IOSTANDARD=LVCMOS33; #IO_L3N_T0_DQS_EMCCLK_14 LOC=M13 IOSTANDARD=LVCMOS33; #IO_L6N_T0_D08_VREF_14 LOC=R15 IOSTANDARD=LVCMOS33; #IO_L13N_T2_MRCC_14 LOC=R17 IOSTANDARD=LVCMOS33; #IO_L12N_T1_MRCC_14
20 NET "g<1>" NET "g<2>" NET "g<3>" NET "b<0>" NET "b<1>" NET "b<2>" NET "b<3>" #NET "sw<12>" #NET "sw<13>" #NET "sw<14>" #NET "sw<15>" LOC=T18 IOSTANDARD=LVCMOS33; #IO_L7N_T1_D10_14 LOC=U18 IOSTANDARD=LVCMOS33; #IO_L17N_T2_A13_D29_14 LOC=R13 IOSTANDARD=LVCMOS33; #IO_L5N_T0_D07_14 LOC=T8 IOSTANDARD=LVCMOS33; #IO_L24N_T3_34 LOC=U8 IOSTANDARD=LVCMOS33; #IO_25_34 LOC=R16 IOSTANDARD=LVCMOS33; #IO_L15P_T2_DQS_RDWR_B_14 LOC=T13 IOSTANDARD=LVCMOS33; #IO_L23P_T3_A03_D19_14 LOC=H6 IOSTANDARD=LVCMOS33; #IO_L24P_T3_35 LOC=U12 IOSTANDARD=LVCMOS33; #IO_L20P_T3_A08_D24_14 LOC=U11 IOSTANDARD=LVCMOS33; #IO_L19N_T3_A09_D25_VREF_14 LOC=V10 IOSTANDARD=LVCMOS33; #IO_L21P_T3_DQS_14 ##VGA Connector NET "red<0>" LOC=A3 IOSTANDARD=LVCMOS33; #IO_L8N_T1_AD14N_35 NET "red<1>" LOC=B4 IOSTANDARD=LVCMOS33; #IO_L7N_T1_AD6N_35 NET "red<2>" LOC=C5 IOSTANDARD=LVCMOS33; #IO_L1N_T0_AD4N_35 NET "red<3>" LOC=A4 IOSTANDARD=LVCMOS33; #IO_L8P_T1_AD14P_35 NET "green<0>" NET "green<1>" NET "green<2>" NET "green<3>" NET "blue<0>" NET "blue<1>" NET "blue<2>" NET "blue<3>" LOC=C6 IOSTANDARD=LVCMOS33; #IO_L1P_T0_AD4P_35 LOC=A5 IOSTANDARD=LVCMOS33; #IO_L3N_T0_DQS_AD5N_35 LOC=B6 IOSTANDARD=LVCMOS33; #IO_L2N_T0_AD12N_35 LOC=A6 IOSTANDARD=LVCMOS33; #IO_L3P_T0_DQS_AD5P_35 LOC=B7 IOSTANDARD=LVCMOS33; #IO_L2P_T0_AD12P_35 LOC=C7 IOSTANDARD=LVCMOS33; #IO_L4N_T0_35 LOC=D7 IOSTANDARD=LVCMOS33; #IO_L6N_T0_VREF_35 LOC=D8 IOSTANDARD=LVCMOS33; #IO_L4P_T0_35 NET "HS" NET "VS" LOC=B11 IOSTANDARD=LVCMOS33; #IO_L4P_T0_15 LOC=B12 IOSTANDARD=LVCMOS33; #IO_L3N_T0_DQS_AD1N_15
21 ## LEDs NET "hfree" NET "vfree" #NET "led<2>" #NET "led<3>" #NET "led<4>" #NET "led<5>" #NET "led<6>" #NET "led<7>" #NET "led<8>" #NET "led<9>" #NET "led<10>" #NET "led<11>" #NET "led<12>" #NET "led<13>" #NET "led<14>" #NET "led<15>" LOC=H17 IOSTANDARD=LVCMOS33; #IO_L18P_T2_A24_15 LOC=K15 IOSTANDARD=LVCMOS33; #IO_L24P_T3_RS1_15 LOC=J13 IOSTANDARD=LVCMOS33; #IO_L17N_T2_A25_15 LOC=N14 IOSTANDARD=LVCMOS33; #IO_L8P_T1_D11_14 LOC=R18 IOSTANDARD=LVCMOS33; #IO_L7P_T1_D09_14 LOC=V17 IOSTANDARD=LVCMOS33; #IO_L18N_T2_A11_D27_14 LOC=U17 IOSTANDARD=LVCMOS33; #IO_L17P_T2_A14_D30_14 LOC=U16 IOSTANDARD=LVCMOS33; #IO_L18P_T2_A12_D28_14 LOC=V16 IOSTANDARD=LVCMOS33; #IO_L16N_T2_A15_D31_14 LOC=T15 IOSTANDARD=LVCMOS33; #IO_L14N_T2_SRCC_14 LOC=U14 IOSTANDARD=LVCMOS33; #IO_L22P_T3_A05_D21_14 LOC=T16 IOSTANDARD=LVCMOS33; #IO_L15N_T2_DQS_DOUT_CSO_B_14 LOC=V15 IOSTANDARD=LVCMOS33; #IO_L16P_T2_CSI_B_14 LOC=V14 IOSTANDARD=LVCMOS33; #IO_L22N_T3_A04_D20_14 LOC=V12 IOSTANDARD=LVCMOS33; #IO_L20N_T3_A07_D23_14 LOC=V11 IOSTANDARD=LVCMOS33; #IO_L21N_T3_DQS_A06_D22_14
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