State Machine Descriptions
|
|
- Mavis Hope Cox
- 5 years ago
- Views:
Transcription
1 State Machine Descriptions Can be modelled using many different coding styles Style guidelines available for Moore or Mealy type machines Several encoding schemes for state variables used in FSM descriptions
2 State Machine Descriptions In this module, you will learn basic techniques for describing finite state machines (FSMs) in VHDL. This includes the differences between Mealy and Moore state machines and how to describe each type so that synthesis tools recognize the description as a finite machine. After completing this module, you will be familiar with: The different types of circuits that you can build as FSMs, and their characteristics. How you can describe the controller/sequencer blocks of your design as FSM descriptions. The tasks associated with building controllers/sequencers using the VHDL language for synthesis.
3 Characteristics of State Machine Descriptions State register Use enumerated data type Clock specification Specification of state transition Specification of the outputs Reset/set signal (optional)
4 Characteristics of State Machine Descriptions Four basic requirements to describe a finite state machine. A state register that holds the current state of the machine. A clock specification. Specification of the state transitions. Specification of the outputs. Optional reset/set specification. Synthesis tools allow a variety of styles for describing FSM s Three-process style: A process for the state transition specification, A process for the state register, and a process for specifying the outputs.
5 State Register Requirements (for Automatic State Machine Encoding) Clocked signal or variable Enumerated type State variable assumes the default type value unless it is set to a start state
6 State Variable Requirements To ensure that synthesis tools can perform state machine analysis and use its state machine encoding algorithms, there are requirements regarding the state register in the description. The state register in the description must be defined as either a clocked signal or variable, and it must be an enumerated type. If it is not an enumerated type, this means you have already done the state encoding, in which case synthesis tools cannot perform any state machine analysis. You cannot assign a value to the state register outside the domain of the FSM. It is a good coding practice to explicitly set the state register to a start state.
7 State Encoding Options You can choose a finite state machine (FSM) encoding technique and specify values for generics before reading your VHDL design into the synthesis tool.
8 State Encoding Options FSM encoding example: Example Encoding sa sb sc sd se sf Menu: Synthesize > VHDL Options CLI: add vhdl <options> Binary (defa ult) OneHot Random Gray
9 State Encoding Options The FSM encoding techniques are: Binary -- Assigns the bit-level equivalents of sequential integers (0,1,2,3, ) to each state using the minimum pattern width possible. This encoding technique is the default. OneHot -- Assigns one bit to each state using a pattern that is as wide as the number of enumerated states. Random -- Assigns unique, arbitrary states using the minimum bit width. Gray -- Assigns a sequence of Gray code patterns to the defined states. (This minimizes the number of one-bit transitions.) The FSM encoding technique that you choose applies to every process statement in the VHDL architecture.
10 State Encoding Options To specify FSM encoding within your VHDL, declare an attribute for the state machine type. For example, declare the following type and attribute within the source file (or in a package): attribute TYPE_ENCODING_STYLE : STRING; type STATES is (s0, s1, s2, s3); attribute TYPE_ENCODING_STYLE of STATES : type is onehot ; Where the syntax is: attribute TYPE_ENCODING_STYLE : STRING; type <enum_type_id> is (<state_ids>); attribute TYPE_ENCODING_STYLE of <enum_type_id> : type is { binary gray onehot random };
11 Moore Machine
12 Moore Machine The basic definition of a Moore machine is that the output of the machine is a function of the current state. The characteristics of the general Moore machine are: May not Be Glitch Free - The output from the state register often passes through a combinational network. For this reason, the output may or may not contain glitches, depending on the state assignment. Testable State/Non-Testable Output - This machine type is partially testable. You can insert scanable state register for the purpose of testing the states. When you scan the state register, however, you are not scanning the outputs. Synchronous Output - The output of this machine is independent of the input and changes only on an active transition of the clock.
13 Moore Machine In a circuit representing a general Moore machine, there are three recognizable blocks: The state transition logic for the state. The flip-flops storing the current state of the machine. The decode logic for the output. The VHDL style used for describing a Moore-type machine builds upon this concept. In particular, the recommended style is to describe the state machine as three separate processes: (1) a clocked process for the state register, a combinational process for the state transition logic, and (3) a combinational process for the decode logic.
14 VHDL Moore Machine - Entity Description ENTITY left_right_shifter IS PORT( a: IN std_ulogic; clk: IN std_ulogic; sel: OUT std_ulogic_vector (3 DOWNTO 0)); END left_right_shifter;
15 VHDL Moore Machine Description Although you can encapsulate an entire state machine in an entity by itself, it is not required. A state machine can be part of an architecture containing other parts of a design and a single architecture can contain multiple state machines. The illustration on the facing page shows how you can relate the state machine bubble diagram to the entity declaration that defines the ports for the state machine. In this example, signal a is the input that affects the state transitions and the signal sel is the name given to the 4-bit output shown in each state bubble. The Clock signal clk does not actually appear in the bubble diagram; it is assumed because a a state machine is a sequential design requiring a clock. The viewfoils that follow show the three processes that make up the recommended style for a general Moore FSM description.
16 VHDL Moore Machine - State Register Description ARCHITECTURE moore OF left_right_shifter IS TYPE states IS (s3,s2,s1,s0); SIGNAL present_state : states := s0; SIGNAL next_state : states := s0; BEGIN synch:process (clk) BEGIN IF (clk = 1 AND clk LAST_VALUE = 0 ) THEN present_state <= next_state; END IF; END PROCESS synch; END moore;
17 VHDL Moore Machine - State Register Description The illustration on the facing page shows the state register portion of the general Moore left_right_shifter FSM description that meets the recommended style. This style for the state register portion of the description satisfies the requirement of defining a variable or signal that specifies the current state of the machine (present_state) and, in this case, the next state of the machine (next_state). Notice that the type (states) of the signals in the code is not a key word; it can be any enumerated type that you define. Also, this code satisfies the requirement of a clocked process that defines the clock edge and makes the next-to-present state assignment.
18 VHDL Moore Machine - State Transition Description state_transition:process(a, present_state) BEGIN next_state <= s0; CASE present_state IS WHEN s0 => CASE a IS WHEN 0 => next_state <= s3; WHEN OTHERS => next state <= s1; END CASE ; WHEN s1 => CASE a IS WHEN 0 => next_state <= s0; WHEN OTHERS => next state <= s2; END CASE ; WHEN s2 => CASE a IS WHEN 0 => next_state <= s1; WHEN OTHERS => next state <= s3; END CASE ; WHEN s3 => CASE a IS WHEN 0 => next_state <= s2; WHEN OTHERS => next state <= s0; END CASE ; END CASE; END PROCESS state_transitions;
19 VHDL Moore Machine - State Transition Description The illustration on the facing page shows the state transition logic portion of the general Moore left_right_shifter FSM decription. This code satisfies the requirement of defining the state transitions. As you can see, the style for the state transition logic uses a CASE statement. This is an entirely combinatorial process; the clock specification was defined in the state register portion of the description on page Also, notice the process sensitivity list. The state transition logic is sensitive to signal a and the present state of the machine. Assigning s0 to the next_state signal done to prevent the machine from entering an unknown state. For example, if you use one-hot encoding, the synthesized result will contain four flop-flops for the state register (due to the 4-bit output). With four flip-flops, there are 16 real hardware states; this design only uses four, which leaves 12 unknown states. For this reason, it is good practice to initially set the next_state signal to a known value.
20 VHDL Moore Machine - Output Decode Description output_decode:process(present_state) BEGIN CASE present_state IS WHEN s0 => sel <= 1000 ; WHEN s1 => sel <= 0100 ; WHEN s2 => sel <= 0010 ; WHEN s3 => sel <= 0001 ; END CASE; END PROCESS output_decode;
21 VHDL Moore Machine - Output Decode Description The illustration on the facing page shows the output decode logic portion of the general Moore left_right_shifter FSM. This process, like the state decode logic process, is entirely combinatorial; the clock specification was defined in the state register portion of the description. Also, notice the process sensitivity list. The output is sensitive only to the present state of the machine, which is a deciding characteristic of a Moore machine. The output value is assigned to signal sel based on the present state of the machine.
22 Moore Machine with Output = State
23 Moore Machine with Output = State The second type of machine to consider is also a Moore machine, but the state register is equal to the output. The output of the circuit is taken directly from the state register which is storing the present state, hence the term output = state. This circuit has three characteristics: Glitch Free - Because the output is taken directly from the state register and is not a function of the input, the output data is stable and is not subject to glitches. Testable - Because the output is taken directly from the state register, inserting scanable registers gives you the capability of testing the state and the output. This differs from the partially testable general Moore machine. Synchronous Output - Like the general Moore machine, the output of this machine is independent of the input and will change only with an active transition of the clock.
24 Moore Machine with Output = State In a circuit representing an output-equal-state Moore machine, there are two recognizable blocks: The transition logic for the state. The registers storing the current state of the machine. This type of Moore machine requires the same number of flip-flops for the state register as outputs in the circuit. For example, if your circuit requires a 4-bit output, an output-equal-state Moore implementation requires four flip-flops. The same circuit described as a general Moore machine requires only as many flip-flops as necessary to store the state values (for example, for states require only two flip-flops). Hence an implementation trade-off exists.
25 Moore Machine with Glitch Free Output
26 Moore Machine with Glitch Free Output The third type of machine to consider is another variation of the general Moore machine. This machine also consists of output registers for a glitch-less output. The output registers comprise a second bank of flip-flops; the state register comprises the first bank. The output is latched on the opposite clock edge that latches the state. Therefore, the delay through the output decode logic must be at most the clock pulse width minus the setup time of the output latches. This circuit has three characteristics: Glitch Free - Because the output is taken directly from registers and is not a function of the input, the output data is stable and is not subject to glitches. Testable - Because the output is taken directly from registers, inserting scanable registers gives you the capability of testing the state and the output. This differs from the partially testable general Moore machine. Synchronous Output - Like the general Moore machine, the output of this machine is independent of the input and will change only with an active transition of the clock.
27 Moore Machine with Glitch Free Output In a circuit representing a glitch free Moore machine, there are four recognizable blocks: The transition logic for the state. The registers storing the current state of the machine. The decode logic for the output. The output register bank. This type of Moore machine requires a bank of flip-flops for the state register and a bank of output registers. For a machine with four states and a four-bit output, six total flip-flops are required. It is critical that the output decode logic settle to a valid value before the active clock edge reaches the output registers.
28 Mealy Machine
29 Mealy Machine The other class of state machine to consider is the standard Mealy machine. The output of the Mealy machine is a function of the current state and the input. The characteristics of the Mealy machine are: Testable State/Non-Testable Output - Like the general Moore machine, this machine type is partially testable. You can insert scan registers for the purpose of testing the state; however, when you scan the state register in this type of machine, you are not scanning the outputs. Asynchronous Output - Because the output of the Mealy machine is a function of its input as well as its state, any change in input is reflected at the output. This allows asynchronous changes at the output of the machine. The asynchronous characteristic of the Mealy machine causes it to be prone to glitches as well as false outputs.
30 Mealy Machine Like the general Moore machine, the Mealy machine consists of three recognizable blocks: The transition logic for the state. The state register. The decode logic for the output. In the Mealy machine, the transition logic for the state and/or the input are also fed through to drive the output decode logic.
31 VHDL Mealy Machine - Entity Description ENTITY left_right_shifter IS PORT( a: IN std_ulogic; clk: IN std_ulogic; sel: OUT std_ulogic_vector (3 DOWNTO 0)); END left_right_shifter;
32 VHDL Mealy Machine - Entity Description Like the general Moore machine just discussed, you can also relate the Mealy state machine bubble diagram to the entity declaration that defines the ports for the design. Although the Mealy machine behaves differently than the Moore machine, the entity declaration is the same. That is, the interface from the Mealy machine to the outside is the same as that of the Moore machine. The following three examples show the template style for a Mealy FSM description. Like the general Moore machine, this basic template for the Mealy consists of a three-process description. One process each for the state transition logic, the state register, and the output decode logic.
33 VHDL Mealy Machine - State Register Description ARCHITECTURE mealy OF left_right_shifter IS TYPE states IS (s3,s2,s1,s0); SIGNAL present_state : states := s0; SIGNAL next_state : states := s3; BEGIN synch:process (clk) BEGIN IF (clk = 1 AND clk LAST_VALUE = 0 ) THEN present_state <= next_state; END IF; END PROCESS synch; END mealy;
34 VHDL Mealy Machine - State Register Description The basic template style for the Mealy machine state register process is identical to the Moore machine state register process shown on page Again, you must define the present_state register as either a signal or variable (you can also optionally define the next_state register as in the example). The state register process is a clocked process that defines the clock edge and makes the next-to-present state assignment.
35 VHDL Mealy Machine - State Transition Description state_transition:process(a, present_state) BEGIN next_state <= s0; CASE present_state IS WHEN s0 => CASE a IS WHEN 0 => next_state <= s3; WHEN OTHERS => next state <= s1; END CASE ; WHEN s1 => CASE a IS WHEN 0 => next_state <= s0; WHEN OTHERS => next state <= s2; END CASE ; WHEN s2 => CASE a IS WHEN 0 => next_state <= s1; WHEN OTHERS => next state <= s3; END CASE ; WHEN s3 => CASE a IS WHEN 0 => next_state <= s2; WHEN OTHERS => next state <= s0; END CASE ; END CASE; END PROCESS state_transitions
36 VHDL Mealy Machine - State Register Description The basic recommended style for the Mealy machine state transition logic process is identical to the Moore machine state transition logic process.
37 VHDL Mealy Machine - Output Decode Description outputs:process(a, present_state) BEGIN CASE present_state IS WHEN s0 => CASE a IS WHEN 0 => sel <= 0001 ; WHEN OTHERS => sel <= 0100 ; END CASE ; WHEN s1 => CASE a IS WHEN 0 => sel <= 1000 ; WHEN OTHERS => sel <= 0010 ; END CASE ; WHEN s2 => CASE a IS WHEN 0 => sel <= 0100 ; WHEN OTHERS => sel <= 0001 ; END CASE ; WHEN s3 => CASE a IS WHEN 0 => sel <= 0010 ; WHEN OTHERS => sel <= 1000 ; END CASE ; END CASE; END PROCESS outputs;
38 Mealy Machine with Glitch Free Output
39 Mealy Machine with Glitch Free Output The final type of machine to consider is a variation of the standard Mealy machine. This is a standard Mealy machine that feeds a bank of output registers to create a synchronous, glitch-free output. The output is latched on the opposite clock edge on which the state is latched. This circuit has three characteristics: Glitch Free - Because the output is taken directly from flop-flops, the output data is stable and is not subject to glitches. Testable - Because the output is taken directly from flip-flops, inserting scanable flip-flops gives you the capability of testing the state and the output. This differs from the partially testable standard Mealy machine. Synchronous Output - Unlike the standard Mealy machine, the output of this machine will change only with an active transition of the clock.
40 Mealy Machine with Glitch Free Output In a circuit representing a glitch free Mealy machine, there are four recognizable blocks: The transition logic for the state. The flop-flops storing the current state of the machine. The decode logic for the output. The output register bank. This type of Mealy machine requires a bank of flip-flops for the state register and a bank of output registers. For a machine with four states and a four-bit output, a total of six flip-flops are required. You must clearly understand the input signal behaviour to implement this type of machine. The output is a function of the state and the input and is latched on the clock edge opposite the state latching. It is critical that the output decode logic settle to a valid value before the active clock edge reaches the output registers.
41 Module Summary State Machines are Characterized by: State Register - current_state/next_state State Transition Specification Output Specification Clock Specification Optional Reset/Set specification State Machine Descriptions: Can be modeled using many different coding styles AutoLogic II supports several encoding schemes for the state register A Three-Process Style is Recommended
Finite State Machines (FSM) Description in VHDL. Review and Synthesis
Finite State Machines (FSM) Description in VHDL Review and Synthesis FSM Review A sequential circuit that is implemented in a fixed number of possible states is called a Finite State Machine (FSM). Finite
More informationFSM Components. FSM Description. HDL Coding Methods. Chapter 7: HDL Coding Techniques
FSM Components XST features: Specific inference capabilities for synchronous Finite State Machine (FSM) components. Built-in FSM encoding strategies to accommodate your optimization goals. You may also
More informationLaboratory Exercise 3 Davide Rossi DEI University of Bologna AA
Laboratory Exercise 3 Davide Rossi DEI University of Bologna AA 2017-2018 Objectives Summary of finite state machines (Mealy, Moore) Description of FSMs in System Verilog Design of control blocks based
More informationUsed to perform operations many times. See previous Parallel to Serial Example
Loops- I Used to perform operations many times See previous Parallel to Serial Example Several advantages Coding style (easier to read) Laziness! When used correctly can generate better results at synthesis
More informationFSM and Efficient Synthesizable FSM Design using Verilog
FSM and Efficient Synthesizable FSM Design using Verilog Introduction There are many ways to code FSMs including many very poor ways to code FSMs. This lecture offers guidelines for doing efficient coding,
More informationDIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 6
DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 6 FINITE STATE MACHINES (FSMs) Moore Machines Mealy Machines Algorithmic State Machine (ASM) charts FINITE STATE MACHINES (FSMs) Classification: Moore Machine:
More informationSequential Logic - Module 5
Sequential Logic Module 5 Jim Duckworth, WPI 1 Latches and Flip-Flops Implemented by using signals in IF statements that are not completely specified Necessary latches or registers are inferred by the
More informationECE 551: Digital System *
ECE 551: Digital System * Design & Synthesis Lecture Set 5 5.1: Verilog Behavioral Model for Finite State Machines (FSMs) 5.2: Verilog Simulation I/O and 2001 Standard (In Separate File) 3/4/2003 1 Explicit
More informationDIGITAL LOGIC WITH VHDL (Fall 2013) Unit 6
DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 6 FINITE STATE MACHINES (FSMs) Moore Machines Mealy Machines FINITE STATE MACHINES (FSMs) Classification: Moore Machine: Outputs depend only on the current state
More informationVHDL Modeling Behavior from Synthesis Perspective -Part B - EL 310 Erkay Savaş Sabancı University
VHDL Modeling Behavior from Synthesis Perspective -Part B - EL 310 Erkay Savaş Sabancı University 1 The Wait Statement Syntax wait until condition; Different forms wait until(clk event and clk = 1 ); wait
More informationFinite State Machines
Lab Workbook Introduction (FSM) are sequential circuit used in many digital systems to control the behavior of systems and dataflow paths. Examples of FSM include control units and sequencers. This lab
More informationGraduate Institute of Electronics Engineering, NTU. Lecturer: Chihhao Chao Date:
Design of Datapath Controllers and Sequential Logic Lecturer: Date: 2009.03.18 ACCESS IC LAB Sequential Circuit Model & Timing Parameters ACCESS IC LAB Combinational Logic Review Combinational logic circuits
More informationVHDL: RTL Synthesis Basics. 1 of 59
VHDL: RTL Synthesis Basics 1 of 59 Goals To learn the basics of RTL synthesis. To be able to synthesize a digital system, given its VHDL model. To be able to relate VHDL code to its synthesized output.
More informationCreating Safe State Machines
Creating Safe State Machines Definition & Overview Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using a hardware description language (HDL),
More informationECE 551 Digital System Design and Synthesis. Instructor: Kewal K. Saluja. Midterm Exam
Last (family) name: First (given) name: Student I.D. #: Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE 551 Digital System Design and Synthesis Instructor: Kewal
More informationVHDL. VHDL History. Why VHDL? Introduction to Structured VLSI Design. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language
VHDL Introduction to Structured VLSI Design VHDL I Very High Speed Integrated Circuit (VHSIC) Hardware Description Language Joachim Rodrigues A Technology Independent, Standard Hardware description Language
More informationTwo HDLs used today VHDL. Why VHDL? Introduction to Structured VLSI Design
Two HDLs used today Introduction to Structured VLSI Design VHDL I VHDL and Verilog Syntax and ``appearance'' of the two languages are very different Capabilities and scopes are quite similar Both are industrial
More informationSequential Circuit Design: Principle
Sequential Circuit Design: Principle Chapter 8 1 Outline 1. Overview on sequential circuits 2. Synchronous circuits 3. Danger of synthesizing asynchronous circuit 4. Inference of basic memory elements
More informationFinite State Machines
Lab Workbook Introduction (FSM) are sequential circuit used in many digital systems to control the behavior of systems and dataflow paths. Examples of FSM include control units and sequencers. This lab
More informationVerilog Sequential Logic. Verilog for Synthesis Rev C (module 3 and 4)
Verilog Sequential Logic Verilog for Synthesis Rev C (module 3 and 4) Jim Duckworth, WPI 1 Sequential Logic Module 3 Latches and Flip-Flops Implemented by using signals in always statements with edge-triggered
More informationVHDL for Synthesis. Course Description. Course Duration. Goals
VHDL for Synthesis Course Description This course provides all necessary theoretical and practical know how to write an efficient synthesizable HDL code through VHDL standard language. The course goes
More informationSequential Circuit Design: Principle
Sequential Circuit Design: Principle Chapter 8 1 Outline 1. Overview on sequential circuits 2. Synchronous circuits 3. Danger of synthesizing async circuit 4. Inference of basic memory elements 5. Simple
More informationThe University of Alabama in Huntsville ECE Department CPE Midterm Exam February 26, 2003
The University of Alabama in Huntsville ECE Department CPE 526 01 Midterm Exam February 26, 2003 1. (20 points) Describe the following logic expression (A B D) + (A B C) + (B C ) with a structural VHDL
More informationECE 4514 Digital Design II. Spring Lecture 15: FSM-based Control
ECE 4514 Digital Design II Lecture 15: FSM-based Control A Design Lecture Overview Finite State Machines Verilog Mapping: one, two, three always blocks State Encoding User-defined or tool-defined State
More informationECE Digital Design Laboratory. Lecture 3 Finite State Machines!
ECE 4401 - Digital Design Laboratory Lecture 3 Finite State Machines! 1!!!! Synchronous Sequential Circuits!!! Synchronous sequential logic circuits are realized using combinational logic and storage elements
More informationEECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis
EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis Jan 31, 2012 John Wawrzynek Spring 2012 EECS150 - Lec05-verilog_synth Page 1 Outline Quick review of essentials of state elements Finite State
More informationEECS150 - Digital Design Lecture 20 - Finite State Machines Revisited
EECS150 - Digital Design Lecture 20 - Finite State Machines Revisited April 2, 2009 John Wawrzynek Spring 2009 EECS150 - Lec20-fsm Page 1 Finite State Machines (FSMs) FSM circuits are a type of sequential
More informationModeling of Finite State Machines. Debdeep Mukhopadhyay
Modeling of Finite State Machines Debdeep Mukhopadhyay Definition 5 Tuple: (Q,Σ,δ,q 0,F) Q: Finite set of states Σ: Finite set of alphabets δ: Transition function QχΣ Q q 0 is the start state F is a set
More informationFINITE STATE MACHINES (FSM) DESCRIPTION IN VHDL. Cristian Sisterna UNSJ
FINITE STATE MACHINES (FSM) DESCRIPTION IN VHDL UNSJ FSM Review 2 A sequential circuit that is implemented in a fixed number of possible states is called a Finite State Machine (FSM). Finite state machines
More informationEECS 270 Verilog Reference: Sequential Logic
1 Introduction EECS 270 Verilog Reference: Sequential Logic In the first few EECS 270 labs, your designs were based solely on combinational logic, which is logic that deps only on its current inputs. However,
More informationWriting VHDL for RTL Synthesis
Writing VHDL for RTL Synthesis Stephen A. Edwards, Columbia University December 21, 2009 The name VHDL is representative of the language itself: it is a two-level acronym that stands for VHSIC Hardware
More informationDESCRIPTION OF DIGITAL CIRCUITS USING VHDL
DESCRIPTION OF DIGITAL CIRCUITS USING VHDL Combinatinal circuits Sequential circuits Design organization. Generic design Iterative operations Authors: Luis Entrena Arrontes, Celia López, Mario García,
More informationDesigning Safe Verilog State Machines with Synplify
Designing Safe Verilog State Machines with Synplify Introduction One of the strengths of Synplify is the Finite State Machine compiler. This is a powerful feature that not only has the ability to automatically
More informationSynthesis from VHDL. Krzysztof Kuchcinski Department of Computer Science Lund Institute of Technology Sweden
Synthesis from VHDL Krzysztof Kuchcinski Krzysztof.Kuchcinski@cs.lth.se Department of Computer Science Lund Institute of Technology Sweden March 23, 2006 Kris Kuchcinski (LTH) Synthesis from VHDL March
More informationLecture 12 VHDL Synthesis
CPE 487: Digital System Design Spring 2018 Lecture 12 VHDL Synthesis Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 What is Synthesis?
More informationDebouncing a Switch. A Design Example. Page 1
Debouncing a Switch A Design Example Page 1 Background and Motivation Page 2 When you throw a switch (button or two-pole switch) It often bounces Page 3 Another switch switch after inversion Page 4 Yet
More informationLecture 08 Finite State Machine Design Using VHDL
Lecture 08 Finite State Machine Design Using VHDL 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-1 Today Sequential digital logic system design state diagram/state graph 10/1/2006 ECE 358: Introduction
More informationEE178 Lecture Verilog FSM Examples. Eric Crabill SJSU / Xilinx Fall 2007
EE178 Lecture Verilog FSM Examples Eric Crabill SJSU / Xilinx Fall 2007 In Real-time Object-oriented Modeling, Bran Selic and Garth Gullekson view a state machine as: A set of input events A set of output
More information8 Register, Multiplexer and
8 Register, Multiplexer and Three-State Inference HDL Compiler can infer Registers (latches and flip flops) Multiplexers Three state gates This chapter discusses methods of inferring different types of
More informationIn the previous lecture, we examined how to analyse a FSM using state table, state diagram and waveforms. In this lecture we will learn how to design
1 In the previous lecture, we examined how to analyse a FSM using state table, state diagram and waveforms. In this lecture we will learn how to design a fininte state machine in order to produce the desired
More informationIn the previous lecture, we examined how to analyse a FSM using state table, state diagram and waveforms. In this lecture we will learn how to design
In the previous lecture, we examined how to analyse a FSM using state table, state diagram and waveforms. In this lecture we will learn how to design a fininte state machine in order to produce the desired
More informationVHDL for Logic Synthesis
VHDL for Logic Synthesis Overview Design Flow for Hardware Design VHDL coding for synthesis General guidelines for hardware designers This lecture includes the content from: Nitin Yogi, Modelling for Synthesis
More information3 Designing Digital Systems with Algorithmic State Machine Charts
3 Designing with Algorithmic State Machine Charts An ASM chart is a method of describing the sequential operations of a digital system which has to implement an algorithm. An algorithm is a well defined
More informationCprE 583 Reconfigurable Computing
Recap 4:1 Multiplexer CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #18 VHDL for Synthesis I LIBRARY ieee
More informationFinite-State Machine (FSM) Design
1 Finite-State Machine (FSM) Design FSMs, an important category of sequential circuits, are used frequently in designing digital systems. From the daily used electronic machines to the complex digital
More informationLecture 3. Behavioral Modeling Sequential Circuits. Registers Counters Finite State Machines
Lecture 3 Behavioral Modeling Sequential Circuits Registers Counters Finite State Machines Behavioral Modeling Behavioral Modeling Behavioral descriptions use the keyword always, followed by optional event
More informationCS232 VHDL Lecture. Types
CS232 VHDL Lecture VHSIC Hardware Description Language [VHDL] is a language used to define and describe the behavior of digital circuits. Unlike most other programming languages, VHDL is explicitly parallel.
More informationSummary of FPGA & VHDL
FYS4220/9220 Summary of FPGA & VHDL Lecture #6 Jan Kenneth Bekkeng, University of Oslo - Department of Physics 16.11.2011 Curriculum (VHDL & FPGA part) Curriculum (Syllabus) defined by: Lectures Lecture6:
More informationMulti-valued Logic. Standard Logic IEEE 1164 Type std_ulogic is ( U, uninitialized
Multi-valued Logic Standard Logic IEEE 1164 Type std_ulogic is ( U, uninitialized X, unknown 0, logic 0 1, logic 1 Z, high impedance W, unknown L, logic 0 weak H, logic 1 weak - ); don t care Standard
More informationFPGA for Software Engineers
FPGA for Software Engineers Course Description This course closes the gap between hardware and software engineers by providing the software engineer all the necessary FPGA concepts and terms. The course
More informationECEU530. Homework 4 due Wednesday Oct 25. ECE U530 Digital Hardware Synthesis. VHDL for Synthesis with Xilinx. Schedule
EEU530 EE U530 igital Hardware Synthesis Lecture 11: Prof. Miriam Leeser mel@coe.neu.edu October 18, 2005 Sequential Logic in VHL Finite State Machines in VHL Project proposals due now HW 4 due Wednesday,
More informationWorld Class Verilog & SystemVerilog Training
World Class Verilog & SystemVerilog Training Sunburst Design - Expert Verilog-2001 FSM, Multi-Clock Design & Verification Techniques by Recognized Verilog & SystemVerilog Guru, Cliff Cummings of Sunburst
More informationQuick Introduction to SystemVerilog: Sequental Logic
! Quick Introduction to SystemVerilog: Sequental Logic Lecture L3 8-545 Advanced Digital Design ECE Department Many elements Don Thomas, 24, used with permission with credit to G. Larson Today Quick synopsis
More informationWriting Circuit Descriptions 8
8 Writing Circuit Descriptions 8 You can write many logically equivalent descriptions in Verilog to describe a circuit design. However, some descriptions are more efficient than others in terms of the
More informationECE 2300 Digital Logic & Computer Organization. More Finite State Machines
ECE 2300 Digital Logic & Computer Organization Spring 2018 More Finite State Machines Lecture 9: 1 Announcements Prelab 3(B) due tomorrow Lab 4 to be released tonight You re not required to change partner(s)
More informationVHDL for Logic Synthesis
VHDL for Logic Synthesis Overview Design Flow for Hardware Design VHDL coding for synthesis General guidelines for hardware designers This lecture includes the content from: Nitin Yogi, Modelling for Synthesis
More information10 Writing Circuit Descriptions
10 Writing Circuit Descriptions You can generally use several different, but logically equivalent, VHDL descriptions to describe a circuit. To understand the interaction between VHDL Compiler and Design
More informationCSE140L: Components and Design Techniques for Digital Systems Lab. FSMs. Instructor: Mohsen Imani. Slides from Tajana Simunic Rosing
CSE4L: Components and Design Techniques for Digital Systems La FSMs Instructor: Mohsen Imani Slides from Tajana Simunic Rosing Source: Vahid, Katz Flip-flops Hardware Description Languages and Sequential
More informationVHDL And Synthesis Review
VHDL And Synthesis Review VHDL In Detail Things that we will look at: Port and Types Arithmetic Operators Design styles for Synthesis VHDL Ports Four Different Types of Ports in: signal values are read-only
More informationMealy and Moore examples
CSE 37 Spring 26 Introduction to igital esign ecture 2: uential ogic Technologies ast ecture Moore and Mealy Machines Today uential logic technologies Ving machine: Moore to synch. Mealy OPEN = creates
More informationCprE 583 Reconfigurable Computing
Recap Moore FSM Example CprE / ComS 583 Reconfigurable Computing Moore FSM that recognizes sequence 10 0 1 0 1 S0 / 0 S1 / 0 1 S2 / 1 Prof. Joseph Zambreno Department of Electrical and Computer Engineering
More informationDigital Design with SystemVerilog
Digital Design with SystemVerilog Prof. Stephen A. Edwards Columbia University Spring 25 Synchronous Digital Design Combinational Logic Sequential Logic Summary of Modeling Styles Testbenches Why HDLs?
More informationGraduate Institute of Electronics Engineering, NTU Design of Datapath Controllers
Design of Datapath Controllers Lecturer: Wein-Tsung Shen Date: 2005.04.01 ACCESS IC LAB Outline Sequential Circuit Model Finite State Machines Useful Modeling Techniques pp. 2 Model of Sequential Circuits
More informationVerilog for High Performance
Verilog for High Performance Course Description This course provides all necessary theoretical and practical know-how to write synthesizable HDL code through Verilog standard language. The course goes
More informationLast Lecture: Divide by 3 FSM
Last Lecture: Divide by 3 FSM Output should be 1 every 3 clock cycles S2 S0 S1 The double circle indicates the reset state Slide derived from slides by Harris & Harris from their book 1 Finite State Machines
More informationController FSM Design Issues : Correctness and Efficiency. Lecture Notes # 10. CAD Based Logic Design ECE 368
ECE 368 CAD Based Logic Design Lecture Notes # 10 Controller FSM Design Issues : Correctness and Efficiency SHANTANU DUTT Department of Electrical & Computer Engineering University of Illinois, Chicago
More informationThe Verilog Language COMS W Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science
The Verilog Language COMS W4995-02 Prof. Stephen A. Edwards Fall 2002 Columbia University Department of Computer Science The Verilog Language Originally a modeling language for a very efficient event-driven
More informationLaboratory Finite State Machines and Serial Communication
Laboratory 11 11. Finite State Machines and Serial Communication 11.1. Objectives Study, design, implement and test Finite State Machines Serial Communication Familiarize the students with Xilinx ISE WebPack
More information[VARIABLE declaration] BEGIN. sequential statements
PROCESS statement (contains sequential statements) Simple signal assignment statement
More informationSequential Circuits. inputs Comb FFs. Outputs. Comb CLK. Sequential logic examples. ! Another way to understand setup/hold/propagation time
Sequential Circuits! Another way to understand setup/hold/propagation time inputs Comb FFs Comb Outputs CLK CSE 37 Spring 2 - Sequential Logic - Sequential logic examples! Finite state machine concept
More informationSequential Logic Synthesis
Sequential Logic Synthesis Logic Circuits Design Seminars WS2010/2011, Lecture 9 Ing. Petr Fišer, Ph.D. Department of Digital Design Faculty of Information Technology Czech Technical University in Prague
More informationVerilog introduction. Embedded and Ambient Systems Lab
Verilog introduction Embedded and Ambient Systems Lab Purpose of HDL languages Modeling hardware behavior Large part of these languages can only be used for simulation, not for hardware generation (synthesis)
More informationEL 310 Hardware Description Languages Midterm
EL 3 Hardware Description Languages Midterm 2 3 4 5 Total Name: ID : Notes: ) Please answer the questions in the provided space after each question. 2) Duration is minutes 3) Closed books and closed notes.
More informationSequential Logic Design
Sequential Logic Design Design of Digital Circuits 2017 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan) http://www.syssec.ethz.ch/education/digitaltechnik_17 Adapted
More informationIntroduction to VHDL #3
ECE 322 Digital Design with VHDL Introduction to VHDL #3 Lecture 7 & 8 VHDL Modeling Styles VHDL Modeling Styles Dataflow Concurrent statements Structural Components and interconnects Behavioral (sequential)
More informationControl and Datapath 8
Control and Datapath 8 Engineering attempts to develop design methods that break a problem up into separate steps to simplify the design and increase the likelihood of a correct solution. Digital system
More informationThe University of Alabama in Huntsville ECE Department CPE Midterm Exam Solution March 2, 2006
The University of Alabama in Huntsville ECE Department CPE 526 01 Midterm Exam Solution March 2, 2006 1. (15 points) A barrel shifter is a shift register in which the data can be shifted either by one
More informationSynthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis. Spring 2007 Lec #8 -- HW Synthesis 1
Verilog Synthesis Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis Spring 2007 Lec #8 -- HW Synthesis 1 Logic Synthesis Verilog and VHDL started out
More informationEE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 6 Combinational and sequential circuits
EE 459/5 HL Based igital esign with Programmable Logic Lecture 6 ombinational and sequential circuits Read before class: hapter 2 from textbook Overview ombinational circuits Multiplexer, decoders, encoders,
More informationNote: Closed book no notes or other material allowed, no calculators or other electronic devices.
ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL Fall 2017 Exam Review Note: Closed book no notes or other material allowed, no calculators or other electronic devices. One page
More informationEECS150 - Digital Design Lecture 10 Logic Synthesis
EECS150 - Digital Design Lecture 10 Logic Synthesis September 26, 2002 John Wawrzynek Fall 2002 EECS150 Lec10-synthesis Page 1 Logic Synthesis Verilog and VHDL stated out as simulation languages, but quickly
More informationIntroduction to Design Vision. Instructor: Prof. Shantanu Dutt. TA: Soumya Banerjee
Introduction to Design Vision Instructor: Prof. Shantanu Dutt TA: Soumya Banerjee We use Synopsys Design Vision for synthesizing the VHDL descriptions. If you are aware in the show schematic option in
More informationEECS150 - Digital Design Lecture 10 Logic Synthesis
EECS150 - Digital Design Lecture 10 Logic Synthesis February 13, 2003 John Wawrzynek Spring 2003 EECS150 Lec8-synthesis Page 1 Logic Synthesis Verilog and VHDL started out as simulation languages, but
More informationקורס VHDL for High Performance. VHDL
קורס VHDL for High Performance תיאור הקורס קורסזהמספקאתכלהידע התיאורטיוהמעשילכתיבתקודHDL. VHDL לסינתזה בעזרת שפת הסטנדרט הקורסמעמיקמאודומלמדאת הדרךהיעילהלכתיבתקודVHDL בכדילקבלאתמימושתכןהלוגי המדויק. הקורסמשלב
More informationLuleå University of Technology Kurskod SMD152 Datum Skrivtid
Luleå University of Technology Kurskod SMD152 Datum 2003-10-24 Skrivtid 9.00 13.00 1 Manual synthesis (10 p, 2 p each) Here you are given five different VHDL models. Your task is to draw the schematics
More informationLecture 32: SystemVerilog
Lecture 32: SystemVerilog Outline SystemVerilog module adder(input logic [31:0] a, input logic [31:0] b, output logic [31:0] y); assign y = a + b; Note that the inputs and outputs are 32-bit busses. 17:
More informationProgramable Logic Devices
Programable Logic Devices In the 1970s programmable logic circuits called programmable logic device (PLD) was introduced. They are based on a structure with an AND- OR array that makes it easy to implement
More informationRTL Design (Using ASM/SM Chart)
Digital Circuit Design and Language RTL Design (Using ASM/SM Chart) Chang, Ik Joon Kyunghee University Process of Logic Simulation and Synthesis Design Entry HDL Description Logic Simulation Functional
More informationDIGITAL LOGIC WITH VHDL (Fall 2013) Unit 3
DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 3 BEHAVIORAL DESCRIPTION Asynchronous processes (decoder, mux, encoder, etc): if-else, case, for-loop. BEHAVIORAL DESCRIPTION (OR SEQUENTIAL) In this design style,
More informationOutline. CPE/EE 422/522 Advanced Logic Design L05. Review: General Model of Moore Sequential Machine. Review: Mealy Sequential Networks.
Outline CPE/EE 422/522 Advanced Logic Design L05 Electrical and Computer Engineering University of Alabama in Huntsville What we know Combinational Networks Sequential Networks: Basic Building Blocks,
More informationVHDL Essentials Simulation & Synthesis
VHDL Essentials Simulation & Synthesis Course Description This course provides all necessary theoretical and practical know-how to design programmable logic devices using VHDL standard language. The course
More informationBlocking(=) vs Nonblocking (<=) Assignment. Lecture 3: Modeling Sequential Logic in Verilog HDL. Procedural assignments
Blocking(=) vs Nonblocking (
More informationFinite State Machines
Finite State Machines Design methodology for sequential logic -- identify distinct states -- create state transition diagram -- choose state encoding -- write combinational Verilog for next-state logic
More informationDigital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition
Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition Table of Contents 1. Introduction to Digital Logic 1 1.1 Background 1 1.2 Digital Logic 5 1.3 Verilog 8 2. Basic Logic Gates 9
More informationEPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013
EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013 Print Here Student ID Signature This is a closed book exam. The exam is to be completed in one-hundred ten (110) minutes. Don t use scratch
More informationUNIT I Introduction to VHDL VHDL: - V -VHSIC, H - Hardware, D - Description, L Language Fundamental section of a basic VHDL code Library :
UNIT I Introduction to VHDL VHDL stands for very high-speed integrated circuit hardware description language. Which is one of the programming languages used to model a digital system by dataflow, behavioral
More informationEEL 4783: HDL in Digital System Design
EEL 4783: HDL in Digital System Design Lecture 15: Logic Synthesis with Verilog Prof. Mingjie Lin 1 Verilog Synthesis Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for
More informationECE 2300 Digital Logic & Computer Organization. More Verilog Finite State Machines
ECE 2300 Digital Logic & Computer Organization Spring 2018 More Verilog Finite Machines Lecture 8: 1 Prelim 1, Thursday 3/1, 1:25pm, 75 mins Arrive early by 1:20pm Review sessions Announcements Monday
More informationOutline. Finite State Machine. 2. Representation of FSM. 1. Overview on FSM
Finite State Machine Outline 1. Overview 2. FSM representation 3. Timing and performance of an FSM 4. Moore machine versus Mealy machine 5. VHDL description of FSMs 6. State assignment 7. Moore output
More informationVerilog for Synthesis Ing. Pullini Antonio
Verilog for Synthesis Ing. Pullini Antonio antonio.pullini@epfl.ch Outline Introduction to Verilog HDL Describing combinational logic Inference of basic combinational blocks Describing sequential circuits
More information