Lecture 08 Finite State Machine Design Using VHDL

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1 Lecture 08 Finite State Machine Design Using VHDL 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-1

2 Today Sequential digital logic system design state diagram/state graph 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-2

3 Synchronous sequential design Most sequential systems are synchronous; that is controlled by a clock. State transfer diagram or Algorithmic state machines (ASM) are used to design sequential circuits. Sequential circuits: Mealy machine: output =func (current state, inputs) Moore machine: output=func (current state) 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-3

4 Synchronous Design Summary using VHDL Draw a state graph and state table Write VHDL code and implement in EDA software package Check and simulate your design Download or fabricate 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-4

5 State assignment in VHDL State encoding: Binary state encoding One-hot state encoding Example: four states S0,S1,S2,S3 Binary state encoding: 00,01,10,11 One-hot state encoding: 1000,0100,0010,0001 Binary state encoding: CPLD One-hot state encoding: FPGA, rich resources in registers. 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-5

6 State assignment in VHDL Binary state encoding type STATE_TYPE is (S1, S2, S3, S4); attribute ENUM_ENCODING: STRING; attribute ENUM_ENCODING of STATE_TYPE: type is " "; signal CURRENTSTATE, NEXTSTATE: STATE_TYPE; One-hot state encoding type STATE_TYPE is (S1, S2, S3, S4); Attribute ENUM_ENCODING: STRING; attribute ENUM_ENCODING of STATE_TYPE: type is " "; signal CS, NS: STATE_TYPE; 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-6

7 State machine VHDL code TWO processes for Mealy Machine: One process is used to model the state registers to decide the next state Second process models to update the next state and output logic 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-7

8 State machine VHDL code Two or Three processes for Moore machine: One process is used to model the state registers to decide the next state Second process models to update the next state Three process models the output logic OR 2 nd and 3 rd combined into one process 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-8

9 FSM VHDL Design Example 0110 sequence detector, Mealy machine no pattern overlapping 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-9

10 0110 Detector Mealy FSM No overlapping library IEEE; use IEEE.STD_LOGIC_1164.all; entity MEALY0110NV is port (CLK,RST,X : in std_logic; Z : out std_logic); end entity MEALY0110NV; architecture NOOV of MEALY0110NV is type STATE_TYPE is (IDLE,S0,S01,S011); signal CS,NS: STATE_TYPE; SEQ: process (CLK,RST) is if (rising_edge(clk)) then if (RST= 1 ) then CS<=IDLE; CS <= NS; end process SEQ; 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-10

11 0110 Detector Mealy FSM No overlapping COM: process (CS,X) is when S01=> Z<= 0 ; NS<=S0; case CS is when IDLE => NS<=S011; NS<=S0; when S011 => NS<=IDLE; NS<=IDLE; Z<= 1 ; when S0 => NS<=IDLE; NS<=S0; end case; NS<=S01; end process COM; end architecture NOOV; 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-11

12 0110 Detector Mealy FSM No overlapping Simulation 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-12

13 0110 detector Moore Machine 0110 sequence detector, Moore machine no pattern overlapping 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-13

14 0110 Detector Moore FSM No overlapping library IEEE; use IEEE.STD_LOGIC_1164.all; entity MOORE0110NV is port (CLK,RST,X : in std_logic; Z : out std_logic); end entity MOORE0110NV; architecture NOOV of MOORE0110NV is type STATE_TYPE is (IDLE,S0,S01,S011,S0110); signal CS,NS: STATE_TYPE; SEQ: process (CLK) is if (rising_edge(clk)) then if (RST= 1 ) then CS<=IDLE; CS <= NS; end process SEQ; 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-14

15 0110 Detector Moore FSM No overlapping with two processes COM: process (CS,X) is Z<= 0 ; case CS is when IDLE => NS<=S0; NS<=IDLE; when S0 => NS<=S0; NS<=S01; when S01=> NS<=S0; NS<=S011; when S011 => NS<=S0110; NS<=IDLE; when S0110=> Z<= 1 ; NS<=IDLE; end case; end process COM; end architecture NOOV; 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-15

16 0110 Detector Moore FSM No overlapping Simulation 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-16

17 0110 Detector Moore FSM No overlapping Another VHDL code style (three processes) library IEEE; use IEEE.STD_LOGIC_1164.all; entity MOORE0110NV is port (CLK,RST,X : in std_logic; Z : out std_logic); end entity MOORE0110NV; architecture NOOV of MOORE0110NV is type STATE_TYPE is (IDLE,S0,S01,S011,S0110); signal CS,NS: STATE_TYPE; SEQ: process (CLK) is if (rising_edge(clk)) then if (RST= 1 ) then CS<=IDLE; CS <= NS; end process SEQ; 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-17

18 0110 Detector Moore FSM No overlapping COM: process (CS,X) is case CS is when IDLE => NS<=S0; NS<=IDLE; when S0 => NS<=S0; NS<=S01; when S01=> NS<=S0; NS<=S011; when S011 => NS<=S0110; NS<=IDLE; when S0110=> NS<=IDLE; end case; end process COM; No output Z in the COM process 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-18

19 0110 Detector Moore FSM No overlapping OUTPUTZ: process (CS) is case CS is when IDLE S0 S01 S011=> Z<= 0 ; when S0110=> Z<= 1 ; end case; end process OUTPUTZ; end architecture NOOV; OR Z<= 1 when CS=S ; end architecture NOOV; 3 rd process defines the output function 10/1/2006 ECE 358: Introduction to VHDL Lecture 8-19

DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 6

DIGITAL LOGIC DESIGN VHDL Coding for FPGAs Unit 6 FINITE STATE MACHINES (FSMs) Moore Machines Mealy Machines Algorithmic State Machine (ASM) charts FINITE STATE MACHINES (FSMs) Classification: Moore Machine: