University of Illinois at Chicago. Lecture Notes # 10

Transcription

1 ECE 366 Computer Architecture Instructor: Shantanu Dutt Department of Electrical and Computer Engineering University of Illinois at Chicago Lecture otes # 0 COMPUTER ARITHMETIC: Integer Addition and Multiplication c Shantanu Dutt, UIC

2 c Shantanu Dutt, UIC 2 Inputs Outputs are, where S i FAi C i+ C i X i Y i Full Adder FA: ADDERS 2

3 c Shantanu Dutt, UIC 3 Problem: Delay is gate delays or is each gate has a delay of 2ns, delay for a 32-bit RCA is 64ns. each FA has a 2-gate delay. Thus S7 S6 S5 S4 S3 S2 S S0 cout FA6 c7 FA6 c6 FA5 c5 FA4 c4 FA3 c3 FA2 c2 FA c FA0 c0 x7 y7 x6 y6 x5 y5 x4 y4 x3 y3 x2 y2 x y x0 y0 Ripple-Carry Adder (RCA) 3

4 c Shantanu Dutt, UIC 4 always represents the sign bit of the sign-extended of the sum bit representation For 2 s complement representation of signed numbers overflow occurs when the carry into the MSB (most significant bit), which is also the sign bit, is different from the carry out of that bit. The carry out of the MSB Overflow is detected for unsigned addition when the carry out final Full Adder is For example, if 4-bit unsigned numbers 6 = added the sum (8) overflows since its binary fit in 4 bits equivalent does not of the and 2 = are Overflow occurs when the result of the operation does not fit in the representation being used Overflow in Addition 4

5 of the th stage can be expressed as: (but not both) is c Shantanu Dutt, UIC 5 is the propagate bit, which is only if the output carry is to be the same as the input carry, i.e.,. This will be the case only when either or Thus the carry out is the generate bit, which is only if a carry out is to be generated irrespective of the input carry. This obviously is the case only when To carry gen. logic S i P i G i From carry gen. logic FAi C i X i Y i A faster adder: The traditional carry-lookahead adder (CLA): Define two extra functions: Speeding up addition ADDERS (Contd.) 5

6 c Shantanu Dutt, UIC 6 In this CLA the ( for each, and 2 for the for a 4-bit RCA. s use 2-level s), logic as and thus opposed have to a delay of 3 gate delays!gate delays CARRY GEERATIO LOGIC S 3 P 3 G 3 S 2 P 2 G 2 S P G S 0 P 0 G 0 C 4 C 3 FA 3 FA 2 FA FA 0 C 2 C C 0 X 3 Y 3 X 2 Y 2 X Y X 0 Y 0 The s are generated by a carry-generation unit as shown below. Consider a 4-bit adder: ote that delay) by each modified full adder (MFA). and can be generated in constant time (specifically, gate Traditional CLA Adder (Contd.) 6

7 $ # c Shantanu Dutt, UIC 7 In general for an-bit group-cla adder with 4-bit CLA cells, the delay is gate delays as opposed to gate delays for the ripple-carry adder # Such a 6-bit adder has a delay of 2 gate delays (= 24ns for a gate delayof 2ns) as opposed to a delay of "= 32 gate delays (= = 64ns) in a 6-bit RCA S 5 2 S 8 S 7 4 S 3 0 = S C 6 C 2 C 8 C 4 4 bit CLA 4 bit CLA 4 bit CLA 4 bit CLA C X 5 2 Y 5 2 X 8 Y 8 X 7 4 Y 7 4 X 3 0 Y 3 0 A 6-bit adder can be partitioned into groups of 4 4-bit CLA adders, with the inter-group carries rippling through the four groups: messy Disadvantage: For a 6-bit adder, for example, we cannot go on generating the s in this manner, since the hardware becomess execssive and Traditional CLA Adder (Contd.) 7

8 & % 8 Traditional CLA Adder (Contd.) A note of caution: %-input gates have greater delays than 2-input gates for. We had assumed that for a 4-bit CLA the 5-input OR and AD gates have the same delay as a 2-input gate. The delay of a 5-input gate will be greater because: Vdd A V dd B A B AB AB A B Gnd (a) 2 i/p OR gate: delay = 2t s + 3RC A V dd A B B C D E A+B+C+D+E C (c) 5 i/p OR using 2 i/p gates: delay = 4t s + 7RC D V dd A B C D E E ABCDE ABCDE A B C D E Gnd (b) 5 i/p OR gate: delay = 2t s + 6RC c Shantanu Dutt, UIC 8

9 $ *)be the resistance of a channel, and ' Thus, while a 5-i/p AD/OR gate will be slower than a 2-i/p AD/OR gate, it will be faster than a cascaded implementation of a 5-i/p AD/OR ckt. The latter is primarily because more transistors switch on in parallel in a 5-i/p AD/OR gate than in a 5-i/p AD/OR ckt. ' ( + ) * while a 5-i/p AD/OR ckt. formed of cascaded 2-i/p gates will have a delay of ' ( " ) * a 5-i/p gate has a delay of ' ( # ) * Let MOS transistor, i.e., the max. of the time for charge to collect at the channel or the time for the charge to be removed from the channel Let the input gate capacitance of a transistor Then, a 2-i/p AD/OR gate has a delay of ( be the max. of the switching on and the switching off time of a Traditional CLA Adder (Contd.) 9

10 c Shantanu Dutt, UIC 0 $ 2-i/p gate delays. ote that the delay of an-bit group-cla adder with 4-bit cells will be somewhat more than # In a 4-bit CLA adder, we are essentally replacing a series of 2-i/p cascaded (multi-level) logic by a multiple-input 2-level logic 0

11 , / 0, c Shantanu Dutt, UIC For delays 3,, the time minimizes to (2-i/p) gate If group size is, time taken is $ 2 (2-i/p) gate delays s n Mux Mux Mux s Add c c in Add c c out in Add c 0 out in 0 Add c in c c out Add 0 c c in out Add 0 c c in out Add in x, y x, y n n 0 0 Carry-Select adder: Yes, by using a carry-select adder ( prefix circuit to generate all carries in time.- time), OR by using a parallel Can we do better than a delay that is linear in the number of bits? Faster adders

12 < ; c Shantanu Dutt, UIC 2 Also, 8is not a commutative operator, i.e., 9 8 ; ; 98 ote that 8is an associative operator, i.e., :9 ; ! 7 Define operator 8as: As a matter of fact,, where propagate bits of a FA discussed earlier 7 and are the generate and For the th full adder, define the symbols 4: kill incoming carry (when ) : propagate incoming carry (when ) : generate a carry (when ) We can encode these symbols as pair of bits. Each FA can produce in constant time 7 7 and call these 65 5 The parallel-prefix CLA adder 2

13 = of = 7 8 = 7 7 c Shantanu Dutt, UIC 3 The s can be computed in constant time after the If we can compute each the th FA as follows: If 4then else if then else if then = = quickly, then we can obtain the carry-in s are available = 8 7 is the th prefix of the associative computation: = 8 7 Define = for the th stage as The parallel-prefix CLA adder (contd.) 3

14 = B = = B = B 8 = = c Shantanu Dutt, UIC 4 i k k j r i,k r k,j! r i,j Since 8is associative, we have C BED = 8 D B C. Thus, = C 7 C 8? B C Define as Computing the s quickly: The parallel-prefix CLA adder (contd.) 4

15 = H = CB = CB c Shantanu Dutt, UIC 5 q 7 q 6 q 5 q 4 q 3 q 2 q q 0!!!! r 7,6 r r 5,4 3,2 r,0!! r 7,4! r 3,0 r 7,0 We can use the above property to form -level s by combining 2 adjacent s by combining two adjacent -level s, etc. This yields a tree-structured circuit with a 8logic at every node; this ckt. gives us only those for some s for which GF 7 s, then 2-level = B C The parallel-prefix CLA adder (contd.) 5

16 - / 0 / 0 L K - / 0 / 0 / 0-8-logic steps, = c Shantanu Dutt, UIC 6 VLSI area reqd.: height of tree is -, width of tree is Extra hardware used: JI 8logic units The delay is steps to come down - steps to go up the tree and This circuit is called a parallel prefix circuit, and can be used to obtain the prefixes of any associative operation (like AD, OR, addition, multiplication, etc.) r r r q 6,0 q q 4,0 q q 2,0 q q q 0 r 7,6 r r 5,4 5,0!!!!!!! a y b a b c y r,0 r 3,2 r,0!! c!!!! r 3,0!! r 7,4 r 3,0 x x!! p Legend: r 7,0 To obtain all s, the tree has to be augmented as shown below. The parallel-prefix CLA adder (contd.) 6

17 7 The parallel-prefix CLA adder (contd.) Another VLSI implementation of a parallel prefix tree: q n q 0 2 q i+ q i r i+,i r r n 0 c Shantanu Dutt, UIC 7

18 8 The parallel-prefix CLA adder (contd.) The final hardware: C out q 5 C 5 q 4 Parallel Prefix Module C 4 q C C 2 2 q q 0 C in S S S S S FA FA FA FA FA X Y 5 5 X Y 4 4 X Y 2 2 X Y X Y 0 0 c Shantanu Dutt, UIC 8

19 O c Shantanu Dutt, UIC 9 From Control Unit n bit Adder Cout C in Subtract/Add = /0 n n n n X Y The augmentation to an adder to perform subtraction is shown below: This means that, which we assume is in 2 s complement notation, has to be negated. A 2 s complement number is negated by complementing it and adding a, i.e., Subtraction M can be done using an adder, since M M SUBTRACTIO COMPUTER ARITHMETIC 9

20 Q Q Q P If the additions are done one at a time, we obtain a sequence of partial products AR R R Add-and-shift (A&S) multiplication: Manual Example: Serial Multiplication MULTIPLIERS COMPUTER ARITHMETIC 20

21 Mis the multiplier and M Q Q QEach partial product c Shantanu Dutt, UIC 2 where T the multiplicand T Thus is obtained as 2

22 Q U Q Q P Q c Shantanu Dutt, UIC 22 T However, is the same: Q R Q R In this case, the partial products obtained are: The same effect as shifting the multiplicand left ( ) can be achieved by keeping the multiplicand fixed at the left-most position and shifting the partial product Example: right. R A&S multiplication (contd.): 22

23 * YXW Z * V c Shantanu Dutt, UIC 23 Final product is in AC-Q register OTE: Overflows are tolerated in the additions AC when right shifting is fed to the MSB of If LSB of Q is then AC = AC+M else AC = AC; Shift YXW -AC-Q register combination right by bit Algorithm: Initialize AC = 0; Q = Multiplier; M = Multiplicand. Do the following steps times Add and shift multiplication for unsigned numbers 6 Accumulator Q M 6 6 And 6 C out 6 bit Adder C out Reg. Multiplier X Multiplicand Y Hardware: A&S multiplication (contd.): 23

24 Q Q Mand Q M M Mand c Shantanu Dutt, UIC 24 Disadvantage: Preprocessing and postprocessing can take up to 4 clock cycles (cc s) If exactly one of it becomes negative, i.e. was negative, get Q s 2 s complement so that Multiply M If multiplicand is -ve get its 2 s complement so that it becomes positive, i.e. If multiplier Mis -ve get its 2 s complement so that it becomes positive, i.e. Assumption: Both Method : are in their 2 s complement representation A&S 2 s complement multiplication 24

25 * YXW * YXW * YXW Q QMis +ve perform M c Shantanu Dutt, UIC 25 When the multiplier taking care to do the following when each is shifted right:. When there is no overflow in the addition (recall the condition for overflow for 2 s complement addition), an arithmetic right shift of register AC.Q is performed without shifting in into the MSB of AC 2. Arithmetic right shift: MSB is sign-extended, i.e., if the MSB (sign bit) is a is shifted into the MSB of AC, otherwise a 0 is shifted in 3. If there is an overflow, then as in the unsigned case, shift into MSB of AC when shifting AC.Q right. This works because in this case the bit output of the adder, where is the MSB, is the exact 2 s complement representation of the sum. Check this by sign extending the inputs to bits and compute the sum the output will be the same as for the -bit inputs, but without overflow out of the th bit Method 2: A&S 2 s complement multiplication (contd.) : 25

26 P 26 A&S 2 s complement multiplication (contd.) : Method 2 (contd.): Example: c Shantanu Dutt, UIC 26

27 Mbits of S QThus S ]\[ M c Shantanu Dutt, UIC 27 where the first term represents normal ^ _ `multiplication for the first T is and thus M T M. When U is negative, T M This works because the value of a 2 s complement number is given by R R R additions as ex- If the multiplier Mis negative, perform the first plained above, and then subtract as the final step Method 2 (contd.): A&S 2 s complement multiplication (contd.) : 27

28 Q M S Q P c Shantanu Dutt, UIC 28 Thus which is what we are doing T M U U T, T f \ c M The magnitude of a negative Mis given by ba ced M :f \ c M ote that multiplication is performed on the basis: Method 2 Example: A&S 2 s complement multiplication (contd.) : 28

29 29 A&S 2 s complement multiplication (contd.) : Method 2 (contd.): Hardware: If ovfl then AC[0] Logic : output = C else out output = AC[0] AC[0] Logic Accumulator Q M 6 6 And Ovfl. C det. 5 6 C out 6 6 bit Adder Multiplier X Multiplicand Y Add and shift multiplication for 2 s complement numbers c Shantanu Dutt, UIC 29

30 lm c Shantanu Dutt, UIC 30 Thus when the multiplier contains long (greater than length 2) strings of s, Booth s multiplication is faster Thus instead of adding and shifting 4 times (corresponding to the string of 4 s in 00), we can subtract ( ) when we see the st coming after a 0 inm, i.e., we detect the 2-bit substring 0 in the last 2 bits of the current just shift 4 times and then add M, ( ) when we see that the current string of s inmhave ended, i.e., we detect the 2-bit substring 0 in the last 2 bits of the current M. This saves us two adds n gh hhh o g mi n h o ggggg m j n g gggh g o gh hhh gi h gggggkj ggggh g Idea: Consider the following substring of M: Booth s Algorithm Speeding Up Serial Multiplication 30

31 ! steps ( qp h Mcally. Consider the following c Shantanu Dutt, UIC 3 Since the multiplication algorithm contains "in the above example), the is ignored and we end up subtracting times the multiplicand exactly the right answer! hhh gggi j r i ggggggj gggh gg Booth s multiplication also takes care of a negative multiplier automati- : Booth s Algorithm (contd.) 3

32 at the U C O ote: () For unsigned multiplication, we need to pad the multiplier Mwith mythical 0s on both sides (right of LSB padding required to start off the process) (2) For 2 s complement multiplication, we need to pad the multiplier Mwith a mythical 0 only to the right of its LSB. This works because (for 2 s complement, the last run of s is..., where the leftmost is the sign bit (bit ) and suppose the rightmost is the th bit from left, then the value of this sequence is, which is exactly the value we alloted to this sequence when we subtracted th bit position at the C T Middle of a run of s Only shift 0 0 End of a run of s 0 0 Middle of a run of 0s Only shift 0 0 Beginning of a run of s Bit Bit Explanation Action (current) (prev.) 6s Booth s algorithm is decribed by the following table for iteration : Booth s Algorithm (contd.) 32

33 subtract means add O C tbeginning of this last run of s. Further, if c Shantanu Dutt, UIC 33 Hardware: Excercise is the value we alloted to the rest of the multiplier before the last run of s, then the final value we give to the multiplier is t, which is its correct value in 2 s complement: is the th bit of the Booth Recoding of means no arithmetic means operation, t. (3) M: (4) xs, ws uu C T t v 33

34 P 34 Booth s Algorithm (contd.) Examples: c Shantanu Dutt, UIC 34

35 $ $ % % $ % c Shantanu Dutt, UIC 35 This will enable us to treat isolated s and 0s differently from runs of s and 0s. Solution: Look at 3 consecutive bits of the multiplier instead of 2 to decide what to do. This is called the Modified Booth s Algorithm (MBA) Problem: When the multiplier contains long strings (say, of length %) of alternating s and 0s ( ), then we perform additions and subtractions using Booth s algorithm compared to only additions using regular add-and-shift Booth s Algorithm (contd.) 35

36 have added on detecting 0 and then subtracted and this isolated 0 is not following an isolated, then we subtract on detecting 0 and added c Shantanu Dutt, UIC 36 corresponding to the isolated 0. This is correct, since in BA we would on detecting 0. This is equivalent to adding again, we are doing the RHS in MBA h gh we add corresponding to the isolated. This is correct, since in BA we would have subtracted a on subsequently detecting 0. Thus assuming the is the th bit, we would have added we are doing the RHS in MBA When we see a gh g Thus when we see a Modified Booth s Algorithm 36

37 and not the previous bit of M Thus actually the least significant of the 3 bits that we observe should be M. Except when distinguishing between an These cases are distinguished by setting a latch is spotted, and to if a run of s is spotted to be 0 when an isolated which are identical. In the first case, we need to have noted that the corresponds to an isolated, so that we do not do anything. In the second case, this means end of a run of s, and so we need to add (as in BA). y z { The st has an isolated and the 2nd a run of s. For the st case we have added corresponding to the, and in the second case, we do not do anything as we are in the middle of a run of s (as in BA) After a right shift, we have the patterns y z { After detecting an isolated (00), it should be noted as such so that after shifting right, we don t misinterpret the bit pattern as ending a run of s. For example, consider two bit patterns showing the 4 consecutive bits of Modified Booth s Algorithm (contd.) 37

38 will be the same as the c Shantanu Dutt, UIC 38 y z { isolated (0) and the end of a run of s (0 s) previously observed bit of M. Thus after a right shift, the above 3-bit patterns will be 38

39 second we subtract In the first case, we correctly do nothing (we already subtracted z { z { M c Shantanu Dutt, UIC 39 corresponding to the isolated 0) corresponding to the middle bit and in the, since the middle bit begins a run of s which has not yet been accounted for. y Thus after a right shift, the above 3-bit patterns will not be identical, but will be The st has an isolated 0 in its 2nd bit for which we subtracted and the 2nd pattern has a 0 in its 2nd bit that ends a run of 0 s. y Again, consider two bit patterns showing 4 consecutive bits of Similarly, we need to distinguish between an isolated 0 and the end of a run of 0 s. In the former case, is set to and to 0 in the latter case Modified Booth s Algorithm (contd.) 39

40 O } } which c Shantanu Dutt, UIC 40? ote that except in the isolated /0 case,? (as in BA), otherwise The second bit is bit is (in the th iteration, ), and the leftmost The rightmost bit in the 3 bits that we are looking at is actually is initialized to 0 Modified Booth s Algorithm (contd.) 40

41 $ $ $ M ƒ ƒ ~ Explanationew } } c Shantanu Dutt, UIC 4 OTE: () The multiplier needs to be padded by mythical 0s on both sides for unsigned and 2 s complement multiplication. (2) is the th bit of the Modified Booth Recoding of (3) This signed-digit encoding has #0s on the average, as opposed to in the regular binary code. Thus "fewer arithmetic operations are required on the average using MBA for multiplication. xs 0 Begins a run of s 0 0 Begins a run of 0s 0 0 Middle of a run of s 0 0 Isolated 0 following a run of s Middle of a run of s Isolated 0 following an isolated OR Middle of a run of 0s Middle of a run of 0s Isolated 0 Bit Bit (next) (current) ~ We thus have the following Modified Booth s Algorithm described for iteration, : Modified Booth s Algorithm (contd.) 4

42 P 42 Modified Booth s Algorithm (contd.) Examples: c Shantanu Dutt, UIC 42