Rakesh Kumar, Ph.D., Life Fellow IEEE

Transcription

1 Day 4-2 Successful Entrepreneurship for Microsystems Rakesh Kumar, Ph.D., Life Fellow IEEE October 23, Teaching assistant Sneha Venkatesh Yelimeli ( Sneha VY ) svyelime@eng.ucsd.edu Course presented at UCSD CSE 190, Fall Quarter

2 1 2 DOOM and GLOOM BAU EXCITING Times Must ADAPT, INNOVATE, Be ENTREPRENEURIAL after Let s Make a Deal 2

3 Changes are coming at an amazingly RAPID rate! 3

4 On the Metro in Shenzen, China, October 28,

5 Semiconductors drive the Electronics food chain Product Board Let s educate the people around us, about our complex business Package Process Design Software Die/Dice Chip 5

6 Electronics Value Chain Smartphones Product Board Let s educate the people around us, about our complex business Package Process Design Software 6

7 Smartphones Looking Inside Soure: ifixit iphone5 7

8 MANY Levels of Innovation Software Display Antenna Touchscreen Processor Radio/RF Front End Sensors Soure: ifixit iphone5 8

9 History Some Market Opportunities and some food for thought! 9

10 Mobile Wireless Evolution Wireless Mobile Computing Social Media The Largest Platform in the History of Mankind 10

11 A Qualcomm View. Ref: Qualcomm Analyst Day, November 20,

12 Ref: Qualcomm Analyst Day, November 20,

13 Ref: Qualcomm Analyst Day, November 20,

14 Ref: Qualcomm Stockholder Meeting, March 4,

15 Expanding Application Areas Ref: Qualcomm Stockholder Meeting, March 4,

16 Ref: Qualcomm Stockholder Meeting, March 4,

17 The The New Internet Paradigm of Things Mobile Connected Smarter.. Sensors everywhere Healthcare Digital Home Green Energy 17

18 The Internet of Things (IoT) Ref: Qualcomm Stockholder Meeting, March 4,

19 Ref: Qualcomm Stockholder Meeting, March 4,

20 The Skyworks View Ref: Skyworks, Investor Presentation

21 21

22 Healthcare applications Millimeter-Scale Computer for Glaucoma Patients: Taking charge many Sensors ECG SMART BANDAGES Source: University of Michigan, Feb 2011 BLOOD PRESSURE PULSE GLUCOMETER PEDOMETER SMART PILLS OR INTERNAL SENSORS WEIGHT BODY COMPOSITION ENVIRONMENTAL SENSORS 22

23 Digital 6 th Sense Augmentation of human ability KNOW the LOCATION SENSE the user s MOTION SEE the user s ENVIRONMENT HEAR the user s SURROUNDINGS Ref: Qualcomm Analyst Day, November 20,

24 Ref: Qualcomm Analyst Day, November 20,

25 Good news for Start-ups! Ref: Qualcomm Analyst Day, November 20,

26 History Market Drivers Industry Directions & Challenges 26

27 Ultrabook Smartphones PCs also drive drive diverse diverse technologies User Experience Performance Architecture, SW, Design, Compact More Moore Low Cost More than Moore Battery Life Low Power FC + WB stack TSV + FC stack TSV system stack MEMS Sensors 27

28 Transistors per Chip, M Minimum Feature Size, um More Moore Transistor complexities have doubled every 2 years MF µp PC inet Cellular Moore s Law 2x / 12mos x / 18mos,,, s 2x / 24mos now +43% / year % / year Year Source: IC Knowledge, ISSCC, TCX Fabless Co. s Semiconductor Co s Fairchild, T.I., Motorola, National, Intel, Toshiba, System Co. s IBM, Hitachi, Sony, Philips, Unisys, 28

29 ECONOMIC challenges are threatening Increased Cost of Capital, R&D, Design Costs associated with node progression have been rising significantly Fab cost $ Millions Process development cost $ Millions Chip design cost including fabless overhead costs* $ Millions 6,700 1, % >30% p.a. 4, % ~40% p.a. 4, ~60% +58% p.a ,450 1,800 2, Sources: imec Sematech intel tsmc umc asml nm 90nm 65nm 45nm 32nm 22nm 130nm 90nm 65nm 45nm 32nm 22nm 130nm 90nm 65nm 45nm 32nm 22nm 29

30 Typical QFN Package (3 mils) 0.9 mm max 0.65 Mold Compound b a Die Wirebond Die Attach Material Cu Leadframe 0.2 (8 mils) 0.05 (2 mils) (1 mils) Top View Bottom View QFN: Qual Flat-pack No-lead Source: ASE 30

31 Innovative Packaging Examples for Reducing Form Factor Stacked Chips PNP Spacer PMIC 3D Stacked IC s Stacked Packages Side-by-Side Source: IMEC Die #1 Die #2 IDM 31

32 HTC Desire Smartphone uses Qualcomm s MSM 8255 HTC Desire HD 32

33 4-die stack BGA package Source: ASE 33

34 4-die stack Source: STATS chippac 34

35 An example ASIC* Development Cycle FPGA Ref Board Start Design SW Tapeout ES QS Prod HW/SW Launch ASIC DESIGN Proto Prod Ramp Hi Volume Year 0 Year 1 Year 2 Software α Software β Software Prod. Initial Silicon Initial Silicon Ramp Initial Product Ramp Volume Production * ASIC: Application Specific Integrated Circuit 35