SiP Catalyst for Innovation. SWDFT Conference Calvin Cheung ASE Group

Transcription

1 SiP Catalyst for Innovation SWDFT Conference Calvin Cheung ASE Group May 31, 2007

2 Outline Consumer Electronic Market > Consumer Electronics Market Trends > SiP Drives Innovation > SiP Category SiP - Challenges > Definition > Technologies & Infrastructure > Innovations Current Practice > Known Good Die > Production flows > Test Platforms The next wave in SiP > Collaborative Co-Design > Working outside the Box 2

3 The Consumer Electronics Market

4 Consumer Market Evolution Semiconductor Revenue ($Bs) $450 $400 $350 $300 $250 $200 $150 $100 Mattel Intellivison VCRs Handheld Calculators Digital Cray Watch 1 CD Player Sony TV Sensors Radio Transceiver Epson LCD TV Laser Jet Printer Office PC Sony Walkman Blackberry Internet Portable Toshiba IC Card Camera Sharp Portable PC Motorola MicroTAC Automotive ABS Sony Video Camera Wristwatch Pager 300mm Global Connectivity/Network 4 C Convergence Scanners Smart Phones AT&T ipod Video Phone STB/HDTV Auto Intellegence VoIP MEMs $50 Atari Games $

5 2006 Semiconductor Market Source SIA Cell Phone Shipment +20% (units) Cell Phone /mobil, 17.0% 2006 $250B / +9.8% Wired Comm 7.0% Industrial/Military, 7.3% 2006 PC Shipment +10~12% (units) Automotive 8.7% 2006 Camera Shipment +16% (units) PC/Computer 43.7% Consummer 17.2% 2006 MP3 Shipment +52% (units) 2006 Digital TV Shipment +52% (units) 5

6 Consumer Market Imperatives Fashion Fu nc tio na lity Cost Size &R eli a bil it y Weight Power Source: ITRS Conference, 2005 July 6

7 Consumer Markets Are Becoming Dominant Consumer percent of semiconductor market 60% 50% 40% 30% 20% 10% 0% Previously driven by Corporate and military requirements "Tricky" Markets > Fashion-driven and price sensitive > Cool and trendy is hard to define and harder to deliver > New Brands & New Players High-volume but fragmented applications 3 I s - Innovation, innovation, innovation > Market > Products > Technology Source: Gartner Dataquest Estimates (August 2006) 7

8 Consumer-Driven Market: Faster Product/Technology/Development Current Product Cost of Delay 1. Lost Sales 2. Increased Expense 3. Opportunity Cost Development Time Slippage 12- to 18 Month Product Life Cycle New Product Development Time 4- to 10-Month Product Life Cycle 8

9 Innovations A few Examples Manufacturing > Wafer thinning > Wirebond > Materials: Molding Compounds, DB Epoxy & films.. > Wirebond - flip chip Hybrids > Substrates Package Architecture > Stacked dies, PoP, PiP, TSV,. Design & Test > Co-design tools & environments > Test methodologies > Integration of process technologies (RF, analog/mix signal, and Digital) And Many More 9

10 SiP - Situation Today Markets: End User Markets are the driver for SiP. Consumer Electronics, principally cell phone, demand diverse functions, size, time to market, and cost, & set in the momentum. Now applications in laptops, networks, automotive, medical, industrial applications have followed. Volume Growth: In 2006, 3.31 Billion SiPs were assembled. By 2010, this number is expected to reach 5.95 Billion,* growing at an average rate of about 16% per year. Technology: SiP applications have become the technology driver for small components, packaging, assembly processes and for high density substrates. New variants of SiP technologies are fast proliferating. 3D packaging and TSV technologies are leading the way. SiP vs SoC: Not the question * Source Techsearch International

11 System-in Package (SiP( SiP) ) definition SiP definition is : System in Package (SiP) is a combination of multiple active electronic components of different functionality, assembled into a single unit, that provides multiple functions associated with a system or sub-system. An SiP may optionally contain passives, MEMS, optical components and other packages and devices. International Technology Roadmap for Semiconductors

12 The Way it Was The Transition Package (SiP) Renaissance FC CSP MCM BGA BCC TQFP QFP P-DIP PLCC 84 Enhanced QFP SOJ 91 LQFP TSOP Film BGA SSOP SOP 95 LBGA BGA 96 TFBGA Enhanced BGA COS BGA 3 Stacked Die BGA Stacked-Die BGA LGA Flip Chip BGA Wafer Bump (Solder) ubga VFBGA Clear Comp. Image Sensor (BCC/QFN) CLCC Image Sensor TCP Wafer Bump (Gold) MPBGA LGA FPS Optical Switch PIP Optical Module POP Micro display QFN WFBGA 7 Stacked Die CSP FC + W/B SIP WLCSP 04 FC+WB 06 F/C SiP 12

13 Categories of SiP Horizontal Placement Wire Bonding Type Flip Chip Type Stacked Structure Interposer Type Wire Bonding Type Wire Bonding + Flip Chip Type Flip Chip Type Interposer-less Type Terminal Through Via Type Embedded Structure Chip(WLP) Embedded + Chip on Surface Type 3D Chip Embedded Type WLP Embedded + Chip on Surface Type Source: ITRS K. Nishi, Hitachi, JEITA, Revised by H. Utsunomiya 13

14 Substrate for SiP Wirebond Single Chip Package Wirebond + FC Multiple Chip Package New Interconnection QFP Stacked Package BGA Stacked Die Flip Chip MCM PoP System-in-a-Package FC+WB PiP Chip Multi-Layer PCB Laminate 2 & 4 Layer Build-Up Substrate Embedded Substrate (Embedded Die & Passives)

15 SiP Challenges

16 KEY SiP CHALLENGES Die Co-Design Cost Analysis Substrate DFM Design Tool Linkage Design For Test Package DFM Modeling & Simulation Package Co-Design 16

17 Major Roadblocks >Lack of tools for Chip-Package Co-Design» Dies Package Substrate» Physical simulations electrical, thermal, mechanical, >How to test chips & package» DFT, package test, KGD strategies >How to integrate and test different type of memories» Alternative design & package options» Debug & yield enhancements >How to implement 3D SiP technologies, e.g. TSV 17

18 COLLABORATIONS Collaborations Between All Parties in The Supply Chain is Crucial EDA Tools to Address The 3D Environment Inside SiP, Predictable Designs is Required DFT Strategy and Plan During IC and Substrate Design Phases is Critical for Debug and Yield Enhancements Memory Vendor to Supply Standard Form Factor and Test Methodology 18

19 Current Practice

20 SiP TEST ISSUES KGD Solutions >Characterize individual die >Wafer sort with final-test (FT) quality» At-speed wafer-probing» Comprehensive DFT for KGD testing at low speed >Package-level burn-in conducted through WLBI Design for Connectivity Test at FT >DFT for failure analysis >Multi test platform, multi insertion test flow 20

21 SiP Test Flow Top Package (Memory) 1 Wafer Received (KGD) Memory 2 Wafer Received (KGD) Bottom Package (ASIC/ Digital/ RF) ASIC Wafer Received Assembly Memory Assembly Wafer Probe Test (Wafer Sort) Test (Burn In) Memory B/I IC Package assembly Assembly Test (Final Test) Memory FT Package Final Test Test (Final Test) Memory (Known-Good-Package) ASIC (Known-Good-Package) PKG Stacking Assembly SIP Final Test Test Shipping 21

22 Test challenges for SiP Accessibility Controllability Observability Failure Localization, Failure Analysis Deep Memory and Mixed Signal Test Time Explode due to Memory Test Design for Test (DFT) 22

23 Memory Test Strategy for SiP Cost is King Yield is God Separate memory Insertion OR One memory + SOC insertion Device mix, Package type, Accessibility Memories in the SIPs Pin counts, volumes, mix Test times, site counts How much capacity Needed SOC, Memory 23

24 Considerations of SiP Memory Testing Bottom VFBGA (ASIC/ Digital/ RF) Wafer Received ASIC Probe ASIC Assy ASIC FT PKG Stacking SIP FT Ship Top VFBGA (Memory PKG) Memory 1 Received (KGD) Memory Assy Memory B/I Memory FT Memory 2 Wafer & final testing requirement Laser repair Test time (10-20 min, full function) Parallel testing Handler solution Solution : 1) Dedicate memory tester Memory Flash testers Memory DRAM testers 2) SOC tester Is it possible to test 256M devices by using SOC tester? Yes, but, cost is a issue. - test time - parallel testing & handler - throughput 24

25 SiP Memory Test Options Two-insertion, Two-platforms o For Large Memory/Long Memory Test Time o Separate SOC and Memory Testers, Separate Insertions Two-insertion, One-platform o For moderate Memory Size/Test Time o Both SOC and Memory Tested on SOC Tester (with Limited Memory Test Capability or MTO), Two Separate Insertions One-insertion, One-platform o For Very Small Memory Size/Test Time o Both SOC and Memory Tested on SOC Tester Together in One Insertion 25

26 Case Study : --Test Strategy for Memory in SiP Separate insertion Memory only on SOC tester with high site count #sites Single insertion Memory & SOC tests >>60 Seconds of test time 2 nd insertion dedicated memory tester? If test times are multiple minutes SIP Manufactures will reduce Memory test times by eliminating Non failing patterns Test time in SIPs may be long on memories initially, but must/will be reduced over time. 26

27 Case Study Summary Memory Test Time Dictates Product Test Flow / Test Platform Choice High Volume, Long Memory Test time, Use Two Insertions, Memory Tester + SOC Tester for Cost Effective Test Low to Medium Volume, Use Dual Insertion on SOC Tester Long Memory Test Time Using Single Insertion on SOC Tester Is Cost Prohibitive Test Cost, Yield and Failure Analysis Are The Major Concerns DFT for Mixed-Signal and Memory Silicon is The Prefer Solution 27

28 SiPs ARE UNLIMITED Technology is not the limiting factor, and so future test requirements are hard to predict Especially true because technology (die) is coming from many suppliers And, what combinations will be integrated. Could be BB+RF, BB+MS, BB+MS+Memory, or all, or??? (what will the next mobile application require?) 28

29 IS THERE A TEST SOLUTION? Overkill solution: buy test capacity that is a superset of all possible requirements > Does such a tester even exist today? For all of tomorrow s future requirements? > Test cost with such platform will be inhibiting > Dual platform solution base on memory test time? Standardized test interface: Provide a standardized interface ala JTAG port > Provide sufficient test coverage and debug capability? > Can we standardize? > Nokia will want what Nokia wants None of these seem to be sufficient because they require knowing what the future holds, but cannot just look at the ITRS roadmap. >Who has been able to predict trends in the consumer market? 29

30 The Next Wave Technology Collaborative SiP Co-Design For System Integration

31 Design for the End Product IC, Package, System Integration Collaborative Co-Design 31

32 The next Step to SiP is System Integration: Co -Design Technical Issues Chip Low-k Digital / Analog / Mixed; Peripheral/Matrix I/O SiP SoC Package Integrated Electrical / Thermal / Stress Performance with Optimal Package Solution SiP Board System Functional Blocks With Optimal Power Distribution, Ground Isolation, Thermal & Reliability 32

33 Collaboration Model Customer Customer Design House IC Design Fab Packaging Test IDM Collaboration Pkg. Design / Pkg. Solution Test Solution Foundry Packaging & Test SAT House Customer Packaging * Test * Design for Manufacturing Customer 33

34 Out of the Box Thinking Mindset & Cultural Change Breakdown of walls» Collaborate across supply chain» Co-Design circuit, package, test, and system engineers» DFT: reduce test cost and cost of ownership Readiness to integrate» Integrate diverse technologies to provide greater functions for the consumers Business Models» Cooperation across supply chain & end user» Create Virtual IDM to achieve optimal efficiency 34

35 The End Thank You