Post-Process Process CMOS Front End Engineering With Focused Ion Beams

Transcription

1 Post-Process Process CMOS Front End Engineering With Focused Ion Beams A. Lugstein 1, W. Brezna 1, B. Goebel 2, L. Palmetshofer 3, and E. Bertagnolli 1 1) Vienna University of Technology, Floragasse 7, Vienna, Austria 2) Infineon Technologies AG Manfred von Ardenne Ring 20, Dresden, Germany 3) Johannes Keppler Universität Linz, Altenbergerstr. 69A, Linz, Austria 24 th Sept. 2002

2 introduction experimental setup charge up phenomena conclusion Outline experimental setup that prevents ESD induced device degradation due to FIB processing in situ control of FIB device modification damage related device degradation and annealing MOSFET with inhomogeneous channel doping - a new approach

3 Introduction FIB as a tool for rapid prototyping simplification of debugging process expose buried tracks for -beam or mechanical probing cut tracks and make new connections (chip repair) up to now, circuit modifications are restricted to the back end due to FIB related device degradation the purpose of this work is to explore the FIB as a high resolution restructuring tool for front end prototyping

4 Experimental Setup 5 nm (50 kv) ion column

5 FIB Processing Layout FIB milled trench W=10 µm 200 nm source drain 12 µm oxide window Fully featured CMOS devices with LDD gate oxide thickness d ox =9 nm gate L=600 nm

6 S FIB Substrate FIB Induced ESD D (floating contacts) Drain Current [A/µm] 1.E-04 deep trenc h milling 1.E-06 1.E-08 1.E-10 1.E-12 1.E-14 trench milling imaging reference device Gate Voltage [V]

7 Damage Related Device Degradation (clamped contacts) FIB 1.E-04 imaging S Substrate D Drain Current [A/µm] 1.E-06 1.E-08 1.E-10 1.E-12 1.E-14 deep trench milling reference device Gate Voltage [V]

8 Progressive Nature Of Device Degradation Rel. Drain Current [%] Milling Depth [nm] FIB on! Passivation Source Drain Bulk Bias conditions: V Passivation G =V D =3V V S =V bulk =0V 50 Gate Gate Current [µa] Residual Distance to Interface S [nm]

9 Nature of Damage amorphous region Passivation 1835 nm redeposited material Gate 500 nm interface traps 70 nm 165 nm

10 Residual Distance to Interface [nm] Rel. Drain current [%]100 reference device Interface Trap Density [x10 11 cm -2 ] Interface Trap Density [cm -2 ] Rapid Thermal Annealing after FIB annealing milling

11 New Approach Well Formation LOCOS V th Adjust Gate Oxide Poly-Gate Spacer Formation Source/Drain Metallization FIB Trench Milling Peak Implant RTA

12 Post-Process Process Channel Engineering Ga/P broad FIB trench beam milling implantation SiO 2 Source Drain Bulk

13 Damage Anneal/Dopant Activation Interface Trap Density [x10 12 cm -2 ] Ga Impl. (2x10 13 cm -2 ) P-Impl. RTA (2x10 RTA 13 cm -2 ) (600 C, FIB Milling 40s) (600 C, 40s) 2.3x10 10 cm -2 n-mosfet p-mosfet

14 Subthreshold Characteristics Drain Current [A/µm] 1.E-02 1.E-04 1.E-06 1.E-08 1.E-10 1.E-12 1.E-14 p-mos (P) p-mos reference device n-mos reference device n-mos (Ga) 1.E Gate Voltage [V]

15 Drain Current [µa/µm] Transfer Characteristics n-mos ref. device n-mos (Ga) p-mos ref. device p-mos (P) Vg=-4V Vg=-3V Vg=-2V Vg=-1V Drain Voltage [V] Vg=4V Vg=3V Vg=2V Vg=1V

16 Gate Drive Characteristic of n-mosn Drain Current [µa/µm] 80 V Early =-46V 60 V Early =-185V V G -V th =1V V G -V th =0.75V V G -V th =0.5V V G -V th =0.25V Drain Voltage [V]

17 Device Parameters Device (dopant) Impl. Dose [ions/cm 2 ] Impl. Energy [kev] V th [mv] I leak [A/µm] I Dsat [µa/µm] Subthreshold swing [mv/dec] n-mos ref. device none x n-mos a (Ga) 2x x n-mos s *) (Ga) 5x x p-mos ref. device none x ,7 p-mos a (P) 2x x *) n-mos with low dose peak implantation

18 Conclusion experimental prevention of ESD induced device degradation monitoring of device parameters during ion beam exposure mitigation of damage by a moderate RTA process post-process CMOS front end engineering excellent device performance and SCE control

19 Acknowledgment The authors would like to thank Dirk Schumann (Infineon) for providing the wafers, Ulf Grabner for the TEM sample preparation and Erich Gornik for providing the clean-room facilities of the Microstructure Center of Vienna (MISZ). The financial support from the Austrian Society for Microelectronics is gratefully acknowledged