Volatile and Non Volatile Thin film embedded memory solutions

Transcription

1 NANO2012 Volatile and Non Volatile Thin film embedded memory solutions Pascale Mazoyer, Sophie Puget, Germain Bossu Rossella Ranica, Alexandre Villaret, Pascal Masson 1, Jean Michel Portal ², Philippe Lorenzini 1 Rachid Bouchakour ², Thomas Skotnicki STMicroelectronics Crolles 1 LEAT Nice-Sophia Antipolis University ² IM2np Aix Marseille University pascale.mazoyer@st.com 1

2 OUTLINE Introduction Volatile Non Volatile Conclusion 2

3 Memory Families Memories NVM RAM STATIC DYNAMIC ROM PROM ASYNCHRONOUS SYNCHRONOUS EPROM EEPROM FLASH SRAM FPM EDO SDRAM DDR-SDRAM RAMBUS VCMRAM FCRAM 3

4 Stand Alone Memory Market 50,000 40,000 M$ 30,000 20,000 10, pascale.mazoyer@st.com 4

5 Embedded Memory DATA STORAGE CAMERA SSD FLASH + SRAM + DRAM PRINTER Base for Mobile systems Mobile Toys Console Game Set top BOX Computer SRAM DRAM TV HD Automotive SRAM + DRAM + FLASH pascale.mazoyer@st.com 5

6 embedded solution System in Package SiP Cost - Place on board + + Performance ~ pascale.mazoyer@st.com 6

7 embedded solution Package on Package PoP Cost - Place on board + + Performance ~ pascale.mazoyer@st.com 7

8 embedded solution 3D integration Samsung 16Gb NAND stack with TSV Cost ~ Place on board + + Performance ~ pascale.mazoyer@st.com 8

9 embedded solution System on Chip SoC Advantages: Wider bandwidth Lower power consumption Smaller pin count Higher integration Lower noise Higher performance Lower Soft Error rate (SER) PS3 graphic processor Cost Place on board + + Performance + + pascale.mazoyer@st.com 9

10 CMOS size definition F minimum feature size C90 C65 G C45 C32 S D 2F 2F STI F STI transistor ultimate cell size: 4F² pascale.mazoyer@st.com 10

11 OUTLINE Introduction Volatile Non Volatile Conclusion 11

12 Static RAM 6 Transistors 100F² Non Destructive Read poor cell stability 32nm Lg Vt mismatch from random dopant fluctuations in bulk pascale.mazoyer@st.com 12

13 Dynamic RAM Stack Trench 1 Transistor 1 Capacitor 1 Transistor 1 Capacitor 25F² 65nm MIM capacitor: : TiN / Al2O3 / TiN Destructive Read = Refresh 4F² pascale.mazoyer@st.com 13

14 Volatile Memory Perspectives Random access time: an order of magnitude shorter than competition Fully CMOS-compatible process: using a single fab and few extra masks to minimize cost SRAM-like access: for easy integration with existing intellectual property SoC-friendly macros: to simplify integration Latest CMOS nm family: for significant process enhancements Speed: Operating time ns range Data retention time: large as possible Temperature operation: compatible with automotive specifications Consumption: Low power operation and low standby power Density: Large scale integration 1 Transistor to select, store and sense the data pascale.mazoyer@st.com 14

15 FBC Floating Body Cell: SOI substrate 10F² VG >0 PROG VD > 0 SL BL Wcell n+ n+ Lcell Id Id1 State 1 Vb>0 p BOX VG < 0 ERASE VD < 0 Id Charge accumulation Vb modulation Vth modulation I Id0 Equilibrium Vth1 Vth0 Vg read State 0 Vb<0 Vg BOX n+ p p Holes evacuation through the junction n+ Recombination Concept: M.R. Tack et al. IEEE Trans. Electron Devices vol. 37, 1990 pascale.mazoyer@st.com 15

16 FBC solutions 1TBulk FDSOI Independent Double Gate S Gate D n burried Bulk substrate S Gate D S Gate 1 Gate 2 D N-buried T Si =9.5nm T BOX =19nm Bulk Thin film technology pascale.mazoyer@st.com 16

17 Process based on SON technology STI process Facet free SiGe/Si epitaxy Gate 1 stack S/D epitaxy STI recess SiGe etch (HCl) Dielectric & Gate 2 deposition Gate 2 stack S/D implant Gate 2 spacer Salicidation. Backend process IDG Technology pascale.mazoyer@st.com 17

18 ongoing process Facet free epitaxy Recess of STI Tunnel etching Back gate stack refill Back gate definition 18

19 1T IDG Potentiel Substrate du substrat potential [V] VB (V) 1 0,8 0,6 0,4 0,2 0-0,2-0,4-0,6 S Gate 1 Gate 2 SOIFD Tox2=145nm IDG DGTox2=5nm V G =V D = V S = 0V V BG 1V V BG 0V V BG -10V V BG 0V V BG -1V V BG -2V D Length Distance [nm] (nm) Technology flexibility SCE and DIBL control Selectivity Vt modulation by charge accumulation & Back gate bias Low bias memory operations S. Puget et al., SNW 2008 G. Bossu et al., SNW 2008 S. Puget et al., TED 2008 submitted S. Puget et al., ESSDERC 2009 rejected ST patent: 07-GR3-221 pascale.mazoyer@st.com 19

20 460 1TFDSOI memory effect amplitude 440 Drain current [µa/µm] 440 "1" read 420 Ι DS =44µA/µm 400 Ι DS "0" read T=21 C 380 0,0 5,0x10-6 1,0x10-5 Drain current [µa/µm] State «1» I DS > sense amplifier detection threshold = 16µA/µm State «0» T=85 C "1" T=85 C "0" T=21 C "1" T=21 C "0" 360 1E-6 1E-5 1E-4 1E-3 0,01 0,1 1 Time [s] Time [s] Tox=33Å Lg=65 nm W=10µm Tbox=19nm Thin Box V DS (V) V GS (V) Write Erase Read Hold 0 0 memory amplitude: Is=44µA/ A/µm retention > T=85 C V S (V) V BG (V) [S. Puget et al., IMW 2009] pascale.mazoyer@st.com 20

21 OUTLINE Introduction Volatile Non Volatile Conclusion 21

22 NV IDG principle Gate1 Source Drain Buried oxide Substrate = Gate2 VG1 VG VS VD VS VD ID ID VG2 Charge trapping in ONO layer Vsub Charge trapped = Vsub pascale.mazoyer@st.com 22

23 Process based on SON technology STI process Facet free SiGe/Si epitaxy Front gate patterning S/D epitaxy Recess STI Tunnel etch (HCl) ONO & Back Gate deposition Back gate patterning and etch S/D implant Back gate spacer Salicidation. Backend process NV IDG Technology 23

24 FDSOI measurements ID (µa/µm) Vsub (V) 1V -1V -3V -5V VD=50mV Lg=65nm VG (V) I D V th0 0 V th V T I T 1 Tox 3nm TSi 8nm TBox 20nm Top gate TiN No doping V th1 V G pascale.mazoyer@st.com 24

25 Conclusion Thin film are promising solutions for volatile and non volatile applications SRAM DRAM FLASH IDG cell size 100 F² 4-20F² 5-10 F² 15F² architecture 6T 1T/1C 1T 1T volatility V V NV NV WR/ER/RD time ns/ns/ns ns/ns/ns µs/µs/ns ns/ns/ns Endurance material none HK ONO ONO scalability limits density capacitor litho litho storage flip flop capacitor floating gate acc/trap maturity prod prod prod tentative pascale.mazoyer@st.com 25

26 PhD defence 26 June 2009 CNRS amphitheatre embedded Non Volatile Memory cell on thin silicon film Germain Bossu I D Alain Poncet Adrian Ionescu Gérard Ghibaudo Pascal Masson Pascale Mazoyer Rachid Bouchakour Thomas Skotnicki I T 0 I T =0 V th0 0 Vth V th1 I D V T V G pascale.mazoyer@st.com 26

27 international memory workshop 2 nd International Memory Workshop imw 2010 May 16 th -19 th 2010 THESHILLA Seoul (Korea) NVSMW 1976 ICMTD 2005 Workshop Spirit Non Volatile & Volatile Reduce gap from technology to system Finance Chairman Technical Chairman General Chairman Jung Dal Choi, Samsung, Korea Tamer San, Texas Instruments, USA Pascale Mazoyer, STMicroelectronics, France pascale.mazoyer@st.com 27