ECEN620: Network Theory Broadband Circuit Design Fall 2018

Transcription

1 ECE60: etwork Theory Broadbad Circuit Deig Fall 08 Lecture 3: Phae-Locked Loop Sytem Sam Palermo Aalog & Mixed-Sigal Ceter Texa A&M Uiverity

2 Aoucemet & Readig/Referece HW due Sept. 0 Chapter, 3, 5, & of Phaelock Techique, F. Garder, Joh Wiley & So, Chapter -3.4 of Low-Power Low-Jitter O-Chip Clock Geeratio, M. Mauri, Ph.D. thei, UCLA, 003. Poted o webite Other referece M. Perrott, High Speed Commuicatio Circuit ad Sytem Coure, MIT Ope Coureware Chapter of Phae-Locked Loop, 3rd Ed., R. Bet, McGraw-Hill, 997. Chapter 4 of Phae-Locked Loop for Wirele Commuicatio, D. Stephe, luwer, 00.

3 Ageda PLL Overview PLL Liear Model PLL Stability PLL Uit PLL oie Trafer Fuctio PLL Traiet Behavior 3

4 PLL Block Diagram [Perrott] A phae-locked loop (PLL) i a egative feedback ytem where a ocillator-geerated igal i phae AD frequecy locked to a referece igal 4

5 PLL Applicatio PLL applicatio Frequecy ythei Multiplyig a 00MHz referece clock to 0GHz Skew cacellatio Phae aligig a iteral clock to a I/O clock Clock recovery Extract from icomig data tream the clock frequecy ad optimum phae of high-peed amplig clock Modulatio/De-modulatio Wirele ytem Spread-pectrum clockig 5

6 Forward Clock I/O Circuit TX PLL TX Clock Ditributio Replica TX Clock Driver Chael Forward Clock Amplifier RX Clock Ditributio De-Skew Circuit DLL/PI Ijectio-Locked Ocillator 6

7 Embedded Clock I/O Circuit TX PLL TX Clock Ditributio CDR Per-chael PLL-baed Dual-loop w/ Global PLL & Local DLL/PI Local Phae-Rotator PLL Global PLL require RX clock ditributio to idividual chael 7

8 Ageda PLL Overview PLL Liear Model PLL Stability PLL Uit PLL oie Trafer Fuctio PLL Traiet Behavior 8

9 Liear PLL Model Phae i geerally the key variable of iteret Liear mall-igal aalyi i ueful for udertad PLL dyamic if PLL i locked (or ear lock) Iput phae deviatio amplitude i mall eough to maitai operatio i lock rage 9

10 Phae Detector ref e fb Detect phae differece betwee feedback clock ad referece clock The loop filter will filter the phae detector output, thu to characterize phae detector gai, extract average output voltage (or curret for charge-pump PLL) 0

11 Loop Filter VDD I Chargig Cotrol Voltage I VSS Dichargig C R C F() Lowpa filter extract average of phae detector error pule

12 Voltage-Cotrolled Ocillator 0 0 VDD/ VDD Time-domai phae relatiohip t t dt v t out out c dt out t t v t 0 out 0 Laplace Domai Model c out (t)

13 Loop Divider out (t) fb (t) [Perrott] Time-domai model fb t out t fb t t dt t out out 3

14 Phae & Frequecy Relatiohip Agular Frequecy i the firt derivative (rate of chage v time) of phae d dt t t Coider a iuoid Phae Step u t t u t t u t i u t t d o t with agular frequecy t ad phae t u t i t t t [Bet] o chage i frequecy 4

15 Phae & Frequecy Relatiohip Frequecy Step u t t i t t i t t 0 where 0 t t 0 A frequecy tep produce a ramp i phae [Bet] t t 5

16 quadratic chage i phae a A frequecy ramp produce where i i i t t t t t t d t u t t t Phae & Frequecy Relatiohip 6 [Bet] Frequecy Ramp 0 t 0 t t

17 Udertadig PLL Frequecy Repoe Liear mall-igal aalyi i ueful for udertad PLL dyamic if PLL i locked (or ear lock) Iput phae deviatio amplitude i mall eough to maitai operatio i lock rage Frequecy domai aalyi ca tell u how well the PLL track the iput phae a it chage at a certai frequecy PLL trafer fuctio i differet depedig o which poit i the loop the output i repodig to Iput phae repoe output repoe [Fichette] 7

18 Ope-Loop PLL Trafer Fuctio G out e F Ope-loop repoe geerally decreae with frequecy 8

19 Cloed-Loop PLL Trafer Fuctio Sytem Determiat l Forward Path Gai G Loop Gai F Forward Path Determiat G G 0 G 0 H out ref G G F Low-pa repoe whoe overall order i et by F() F 9

20 PLL Error Trafer Fuctio l Sytem Determiat Forward Path Gai Loop Gai F Forward Path Determiat G G 0 G 0 E e ref G F Ideally, we wat thi to be zero Phae error geerally icreae with frequecy due to thi high-pa repoe 0

21 PLL Order ad Type The PLL order refer to the umber of pole i the cloed-loop trafer fuctio Thi i typically oe greater tha the umber of loop filter pole The PLL type refer to the umber of itegrator withi the loop A PLL i alway at leae Type due to the itegrator ote, the order ca ever be le tha the type

22 Firt-Order PLL Simple firt-order low-pa trafer fuctio Cloed-loop badwidth i equal to the loop gai magitude ote, the Loop Gai Magitude i ot imply the PLL ope-loop gai evaluated at =0. It i lim 0. G F Forward Path Gai : G G Loop Gai Magitude : lim 0 3dB Trafer Fuctio : H 3dB Cloed - Loop Badwidth : 3dB Error Fuctio : E 3dB Thi expreio cacel the pole ad allow a compario betwee PLL of differet order ad type. It i ueful to predict the teady-tate phae error. See Garder..3 ad 5...

23 Firt-Order PLL Trackig Repoe The PLL trackig behavior, or how the phae error repod to a iput phae chage, varie with the PLL type Phae Step Repoe [Bet] u t t t t u t i u o chage i frequecy The fial value theorem ca be ued to fid the teady-tate phae error lim 0 E lim 0 0 All PLL hould have o teady-tate phae error with a phae tep error ote, thi aume that the frequecy of operatio i the ame a the ceter frequecy (V ctrl =0). Workig at a frequecy other tha the ceter frequecy i coidered havig a frequecy offet (tep). 3

24 Firt-Order PLL Trackig Repoe Frequecy Offet (Step) u t t i t t i t t 0 where 0 t t 0 [Bet] A frequecy tep produce a ramp i phae The fial value theorem ca be ued to fid the teadytate phae error lim E 0 0 lim With a frequecy offet (tep), a firt-order PLL will lock with a teady-tate phae error that i iverely proportioal to the loop gai 4

25 Firt-Order PLL Iue The loop gai directly et the PLL badwidth o degree of freedom I order to have low phae error, a large loop gai i eceary, which implie a wide badwidth Thi may ot be deired i applicatio where we would like to filter iput referece clock phae oie Firt-order PLL offer o filterig of the phae detector output Without thi filterig, the may ot be well approximated by a imple factor Multiplier have a ecod-harmoic term Digital output quare pule that eed to be filtered 5

26 Secod-Order Type- PLL w/ Paive Lag-Lead Filter Paive Lag-Lead Loop Filter [Alle] F R C R C 6

27 7 R C R C F Secod-Order Type- PLL w/ Paive Lag-Lead Filter 0 Error Fuctio : Dampig Factor : Frequecy : atural Trafer Fuctio : lim Loop Gai Magitude : Forward Path Gai : E H G G Q : ote

28 Secod-Order Type- PLL Trackig Repoe Phae Step Repoe lim lim E Agai, phae error hould be zero with a phae tep Frequecy Offet (Step) lim E lim 0 0 A ecod-order type- PLL will till lock with a phae error if there i a frequecy offet! 8

29 Secod-Order Type- PLL Propertie While the ecod-order type- PLL will till lock with a phae error with a frequecy offet, it i much more ueful tha a firt-order PLL There are ufficiet deig parameter (degree of freedom) to idepedetly et,, ad The loop filter coditio the phae detector output for proper cotrol Loop tability eed to be coidered for the ecod-order ytem 9

30 Secod-Order Type- PLL w/ Paive Serie- Lag-Lead Filter Paive Serie- Loop Filter F R ote, thi type of loop filter i typically ued with a chargepump drivig it. Thu, the filter trafer fuctio i equal to the impedace. 30

31 Secod-Order Type- PLL w/ Paive Serie- Lag-Lead Filter F R Trafer Fuctio : H Forward Path Gai : G Error Fuctio : E Loop Gai Magitude : R R C atural Frequecy: C Dampig Factor : R G lim 0 3

32 Secod-Order Type- PLL Trackig Repoe Phae Step Repoe lim E lim Agai, phae error hould be zero with a phae tep Frequecy Offet (Step) lim 0 0 E lim 0 A ecod-order type- PLL will lock with o phae error with a frequecy offet! 3

33 Secod-Order Type- PLL Propertie A big advatage of the type- PLL i that it ha zero phae error eve with a frequecy offet Thi i why type- PLL are very popular A type- PLL require a zero i the loop filter for tability. ote, thi i ot required i a type- PLL Thi zero ca caue extra peakig i the frequecy repoe Importat to miimize thi i ome applicatio, uch a cacaded CDR ytem 33

34 Ageda PLL Overview PLL Liear Model PLL Stability PLL Uit PLL oie Trafer Fuctio PLL Traiet Behavior 34

35 Feedback Cofiguratio [arilaya] Here f = feedback factor (B() i previou lide) A CL () If a 0 i large : A 0 f CL p 0 a p f 35

36 ote: a() ca have higher-order pole [arilaya] 36

37 [arilaya] 37

38 [arilaya] 38

39 Firt-Order PLL Trafer Fuctio : H Error Fuctio : E F Forward Path Gai : G Loop Gai Magitude : Cloed - Loop Badwidth : 3dB G lim 0 3dB 3dB 3dB 39

40 Firt-Order PLL Stability Ope-loop Bode plot are ueful for checkig tability via 0log0 G j (db) G the phae margi A firt-order PLL i iheretly table ad alway ha 90 phae margi 40

41 4 0 Error Fuctio : Dampig Factor : Frequecy : atural Trafer Fuctio : lim Loop Gai Magitude : Forward Path Gai : E H G G R C R C F Secod-Order Type- PLL w/ Paive Lag-Lead Filter

42 0log0 Secod-Order Type- PLL w/ Lag-Lead Filter Stability Aumig a decade pacig betwee filter pole ad zero G j (db) G ormalizig for = orm. Zeta PM A larger provide a more table ytem 4

43 Secod-Order Type- PLL w/ Lag-Lead Filter Output Repoe w/ Phae Step orm. Zeta PM ote, time axi i caled by qrt( ) i order to view the phae tep plot o oe graph 43

44 Root Locu A Root-Locu Plot i a plot of the cloed-loop pole i the complex -plae a the loop gai chage from zero to very large Ueful i viualizig ytem tability ad eitivity to variatio i loop gai For tability, all pole hould lie withi the left-half plae, i.e o pole hould be i the right-half plae A good deig eure that the pole have ufficiet margi from the imagiary axi for proper tability, dampig, ad acceptable gai peakig 44

45 Secod-Order Type- PLL w/ Paive Lag-Lead Filter Root Locu G Ope - Loop : =, =9 Cloed - Loop : H Iitial pole value with zero loop gai are the ope-loop pole p 0 p 0. Fial pole value with ifiite loop gai are the ope-loop zero p p 45

46 46 Secod-Order Type- PLL w/ Paive Lag-Lead Filter Root Locu Cloed - Loop : Ope - Loop : H G =, =9 for = 0.* =0.38 0* =3.09 For

47 Secod-Order Type- PLL w/ Paive Lag-Lead Filter Cloed-Loop Repoe 0*log 0 H(j) G Ope - Loop : Cloed - Loop : H ormalized Phae Step Repoe orm. Zeta PM / t*qrt( ) A larger provide a more table ytem ad wider loop badwidth 47

48 Secod-Order Type- PLL w/ Paive Serie- Lag-Lead Filter F R Defie a loop gai factor Forward Path Gai : G R R Trafer Fuctio : H R R C atural Frequecy: C Dampig Factor : Error Fuctio : E 48

49 Secod-Order Type- PLL w/ Paive Serie- Lag-Lead Filter Root Locu R=, C= G Ope - Loop : Cloed - Loop : H Iitial pole value with zero loop gai are the ope-loop pole p 0 p 0 Fial pole value with ifiite loop gai are the ope-loop zero p p 49

50 Secod-Order Type- PLL w/ Paive Serie- Lag-Lead Filter Root Locu R=, C= G Ope - Loop : Cloed - Loop : H for = 0.* =0.38 0* =

51 Secod-Order Type- PLL w/ Paive Serie- Lag-Lead Filter Stability 0log0 G j (db) G ormalizig for = orm. Zeta PM A larger provide a more table ytem 5

52 Secod-Order Type- PLL w/ Paive Serie- Lag-Lead Filter Cloed-Loop Repoe 0*log 0 H(j) G Ope - Loop: Cloed - Loop: H ormalized Phae Step Repoe orm. Zeta PM / t*qrt( ) A larger provide a more table ytem ad wider loop badwidth 5

53 Typical Charge-Pump PLL Loop Filter VDD w/o C I Chargig Cotrol Voltage F R I VSS Dichargig C R C F() A ecodary capacitor C i ofte added for additioal filterig to reduce referece pur Thi itroduce a extra pole ad potetial tability cocer 53 F w/ C C C C C

54 Dampig Factor : Frequecy: atural high frequecy, ca approximate a a ecod - order ytem with the third - pole i at a If Error Fuctio : Trafer Fuctio : Forward Path Gai : loop gai factor Defie a C C C C C C C C C C C C C C C E C C C C C C C C C H C C C C C C C G R Third-Order Type- PLL w/ Paive Serie- Lag-Lead Filter & Additioal Pole C C C C F

55 Third-Order Type- PLL w/ Paive Serie- Lag-Lead Filter & Additioal Pole Root Locu G Ope - Loop: C C C R=, C =, C =0. Cloed - Loop: H C C 3 C Iitial pole value with zero loop gai are the ope-loop pole C C p 0 p 0 p3 C Fial pole value with ifiite loop gai p p,3 5 j 55

56 Third-Order Type- PLL w/ Paive Serie- Lag-Lead Filter & Additioal Pole Root Locu G Ope - Loop: C C C R=, C =, C =0. Cloed - Loop: H C C 3 C for = 0.* =

57 Secod-Order Type- PLL w/ Paive Serie- Lag-Lead Filter Stability 0log0 G j (db) G ormalizig for = orm. Zeta PM A larger provide a more table ytem 57

58 Third-Order Type- PLL w/ Paive Serie- Lag-Lead Filter & Additioal Pole Stability 0log0 G j (db) G C C C ormalizig for = A larger may ot provide a more table ytem 58

59 Third-Order Type- PLL Cloed-Loop Repoe 0*log 0 H(j) G Ope - Loop: C C C Cloed - Loop: H 3 C C C ormalized Phae Step Repoe / t*qrt( ) If i icreaed too high frequecy peakig ad traiet rigig occur! 59

60 Itability ad the yquit Criterio [arilaya] For a PLL T i the forward gai G T multiplied by the feedback factor G 60

61 For a PLL : T G Frequecy Sweep of Loop Gai, T() [arilaya] 6

62 Ageda PLL Overview PLL Liear Model PLL Stability PLL Uit PLL oie Trafer Fuctio PLL Traiet Behavior 6

63 PLL Uit w/ Dimeiole Filter (o-charge-pump PLL) 63

64 Phae Detector Detect phae differece betwee feedback clock ad referece clock The loop filter will filter the phae detector output, thu to characterize phae detector gai, extract average output voltage The factor ca chage depedig o the pecific phae detector circuit PLL w/ dimeio uit - le are V/rad loop filter : 64

65 Dimeio-Le Loop Filter Example: Paive Lag-Lead Loop Filter [Alle] F R C Lowpa filter extract average of phae detector igal o uit for the dimeio-le loop filter R C 65

66 Voltage-Cotrolled Ocillator 0 0 VDD/ VDD Time-domai phae relatiohip t t dt v t out out rad uit are V MHz 6 rad 0 V V c dt out t t v t 0 out 0 Laplace Domai Model c out (t) 66

67 Loop Divider out (t) fb (t) [Perrott] Time-domai model fb t out t The loop divider i dimeio-le i the PLL liear model fb t t dt t out out 67

68 PLL Uit w/ Dimeiole Filter (o-charge-pump PLL) uit are V/rad Loop Filter i uit - le rad uit are V Loop Divider i uit - le 68

69 PLL Uit w/ Impedace Filter (Charge-Pump PLL) [Mauri] D ICP 69

70 Phae Frequecy Detector (PFD) Phae Frequecy Detector allow for wide frequecy lockig rage, potetially etire tuig rage 3-tage operatio with UP ad DOW output et differece i pule width repreet phae error UP loger = Poitive D loger = egative Edge-triggered reult i duty cycle ieitivity The u-averaged PFD gai (ratio of et output pule time width with iput phae error time) i typically ad dimeio-le 70

71 Averaged PFD Trafer Characteritic UP= & D=- [Perrott] Cotat lope ad polarity aymmetry about zero phae allow for wide frequecy rage operatio The averaged PFD gai i typically /(*pi) with uit of rad - 7

72 Charge Pump Covert PFD output igal to charge Charge i proportioal to PFD pule width U - Averaged Charge - Pump Gai I ICP Amp Averaged Charge - Pump Gai rad ICP Amp Total PFD & Charge - Pump Gai rad Thi gai ca vary if a differet phae detector i ued CP Amp 7

73 Loop Filter VDD w/o C I Chargig Cotrol Voltage F R I VSS Dichargig C R C F() F w/ C C C C C Lowpa filter extract average of phae detector error pule The uit of the filter are ohm 73

74 PLL Uit w/ Impedace Filter (Charge-Pump PLL) [Mauri] D ICP i uit - le if u - averaged, uit of Charge Pump Gai uit are A if Total Phae Detector & Charge - Pump combied gai ha uit of Loop Filter ha uit of, u - averaged, Loop divider i uit - le rad - if A rad if rad uit are V averaged averaged A rad Oly Average Oce 74

75 Ageda PLL Overview PLL Liear Model PLL Stability PLL Uit PLL oie Trafer Fuctio PLL Traiet Behavior 75

76 PLL oie Trafer Fuctio [Mauri] 76

77 Iput oie Trafer Fuctio [Mauri] o Iput Phae oie: Voltage oie o Iput Clock Source: ICPR w/ a loop gai factor : (aume ) H I T I out I v out I o out o I 77

78 Iput oie Trafer Fuctio 78 out H I I v T o o out out I I I Iput Phae oie: Voltage oie o Iput Clock Source: 0, 0,.6, 53,, rad 0 *0,, * Simulatio Parameter buf delay V p V MHz k R pf C V GHz A GHz MHz

79 oie Trafer Fuctio [Mauri] i differet if the iput i at the V ctrl iput ( ) or upply ( Vdd ) Phae oie: H out Voltage oie o Iput: T v out out 79

80 oie Trafer Fuctio 80 out H v T out out Phae oie: Voltage oie o Iput: 0, 0,.6, 53,, rad 0 *0,, * Simulatio Parameter buf delay V p V MHz k R pf C V GHz A GHz MHz

81 Clock Buffer oie Trafer Fuctio [Mauri] delay uit = (/V) delay buf Output Phae oie: Voltage oie o Buffer Iput: out out delay T buf v buf buf buf H buf out buf delay buf delay 8

82 Clock Buffer oie Trafer Fuctio 8 out H buf buf v T delay buf delay buf delay out out buf buf buf Output Phae oie: Voltage oie o Buffer Iput: 0, 0,.6, 53,, rad 0 *0,, * Simulatio Parameter buf delay V p V MHz k R pf C V GHz A GHz MHz

83 PLL oie Trafer Fuctio Take-Away Poit The way a PLL hape phae oie deped o where the oie i itroduced i the loop Optimizig the loop badwidth for oe oie ource may ehace other oie ource Geerally, the PLL low-pa hape iput phae oie, bad-pa hape iput voltage oie, ad high-pa hape /clock buffer output phae oie 83

84 Ageda PLL Overview PLL Liear Model PLL Stability PLL Uit PLL oie Trafer Fuctio PLL Traiet Behavior 84

85 Liear PLL Model If the phae iput amplitude i mall, the the liear model ca be ued to predict the traiet repoe E e ref G F Ideally, we wat thi to be zero Phae error geerally icreae with frequecy due to thi high-pa repoe 85

86 Firt-Order PLL Trackig Repoe F, E, 3dB 3dB Phae Step Repoe Uig the Fial Value Theorem : lim 0 E lim 0 0 Phae error hould be zero with a phae tep Traiet Repoe : L e t Traiet Repoe i a expoetialy decayig tep 86

87 Firt-Order PLL Trackig Repoe F, E, 3dB 3dB Frequecy Offet (Step) Repoe Uig the Fial Value Theorem : lim 0 E lim 0 The phae error i iverely proporitioal to the loop gai with a frequecy offet Traiet Repoe : L e t Traiet Repoe i a expoetialy riig tep 87

88 Firt-Order PLL Trackig Repoe F, E, 3dB 3dB Frequecy Ramp Repoe Aume that the iput frequecy i chagig liearly with time at a rate of rad/ec ref t t Uig the Fial Value Theorem : lim 0 3 E lim 0 3 The phae error will grow to ifiity if i fiite Traiet Repoe : L 3 t e t 88

89 E F,, 89 Phae Step Repoe yourelf thi Try to compute Traiet Repoe : phae tep Phae error hould be zero with a 0 lim lim Value Theorem : the Fial Uig 0 0 E L Secod-Order Type- PLL Trackig Repoe

90 E F,, 90 Frequecy Offet (Step) Repoe yourelf thi Try to compute Traiet Repoe : frequecy offet to the loop gai with a phae error i iverely proporitioal The lim lim Value Theorem : the Fial Uig 0 0 E L Secod-Order Type- PLL Trackig Repoe

91 E F,, 9 Frequecy Ramp Repoe yourelf thi Try to compute Traiet Repoe : fiite i grow to ifiity if phae error will The lim lim Value Theorem : the Fial Uig E L Secod-Order Type- PLL Trackig Repoe

92 Secod-Order Type- PLL Trackig Repoe F R, Phae Step Repoe E, R Uig the Fial Value Theorem : lim E 0 lim Phae error hould be zero with a phae tep Traiet Repoe : L 9

93 Secod-Order Type- PLL Phae Step Repoe Traiet Repoe : L 93

94 Secod-Order Type- PLL Trackig Repoe F R, E, R Frequecy Offet (Step) Repoe Uig the Fial Value Theorem : lim E 0 lim 0 The phae error goe to zero with a Type - PLL 3 0 Traiet Repoe : L 94

95 Secod-Order Type- PLL Frequecy Step Repoe Traiet Repoe : L 95

96 96 Frequecy Ramp Repoe E Traiet Repoe : dyamic phae lag frequecy ramp with a A ecod - order type - PLL ca track a lim lim Value Theorem : the Fial Uig L Secod-Order Type- PLL Trackig Repoe R E R F,,

97 Secod-Order Type- PLL Frequecy Ramp Repoe Traiet Repoe : L 3 97

98 Ideal Phae Detector A ideal phae detector ha the ame gai (lope) over a rage Thi allow the liear PLL model to be ued for all phae relatiohip 98

99 Real Phae Detector May phae detector are oliear ad do ot diplay the ame gai for a give phae relatiohip Thi implie that the PLL caot be decribed by the liear model for large iput phae deviatio 99

100 PLL Frequecy Step Repoe: Liear v Behavioral Model Frequecy Step Iput: ref ()= = Mrad/ec 3 o Cycle Slip Oberved with Liear Model Cycle Slip Due to o-liearitie i loop compoet (primarily the ), a real PLL repoe ca vary igificatly from the liear model 00

101 PLL Hold Rage (Siuoidal ) A PLL Hold Rage i the iput frequecy rage over which the PLL ca maitai tatic lock w/ Liear Model the Steady -State Phae Error i e Firt - Order : Secod - Order Type -: Secod - Order Type - : With a iuoidal phae detector, the phae error i i e Sice ie caot exceed, the lock frequecy i cotraied to Hold Rage : H rad/ec The hold rage i fiite for a type- PLL, ad theoretically ifiite for a type- PLL. However i practice it will be limited by aother PLL block, uch a the tuig rage. 0

102 Firt-Order PLL Phaelock Acquiitio (Siuoidal ) Aumig a imple firt - order PLL with a iuoidal F Itataeou Frequecy : Siuoidal Phae Detector Output : o v c i t e Aume the iput igal i at a frequecy differet from, uch that the o iput phae i ref t ad ref o 0

103 Firt-Order PLL Phaelock Acquiitio (Siuoidal ) out t t t v d 0 t i d 0 o o c The PLL output phae i out o t o The PLL phae error i e out e ref out t ref o t i e o d 0 out Differetiatig thi w.r.t. time yield the followig oliear differetial equatio de dt t i e t where 03

104 Firt-Order PLL Hold Rage (Siuoidal ) de dt If the PLL i locked, t e i i e 0 Sice ie caot exceed, the lock frequecy i cotraied to Hold Rage : H rad/ec 04

105 Firt-Order PLL Phaelock Acquiitio (Siuoidal ) ormalizig the firt - order PLL differetial equatio by e ormalized Frequecy Error, e i e I the phae - plae plot, there are ull where egative - lope ull are table lock poit, d e dt 0 Phae Error, e while poitive - lope ull are utable Every cycle ( iterval) cotai a table ull, thu e caot chage by more tha oe cycle before lockig There i o cycle lippig i the lockig proce A cycle lip occur whe the phae error chage by more tha without lockig 05

106 Firt-Order PLL Phaelock Acquiitio Time (Siuoidal ) I order to fid the phaelock acquitio time, we eed to formally olve If e t t i zero ad t o e i d 0 e out 0i mall, uch that i e, e the approximate olutio i the liear model phae tep repoe However, if e 0 e t 0 i large, the repoe will deviate from thi liear approximatio ad ca icreae igificatly out e t 06

107 Firt-Order PLL Lock Failure (Siuoidal ) Firt-Order PLL Cotrol Voltage Hold Rage : H rad/ec If the frequecy offet exceed the PLL hold rage, the phae error will ocillate aymmetrically a the PLL udergoe cycle lip 07

108 Secod-Order Type- PLL Phaelock Acquiitio (Siuoidal ) 08 0 i i 0 PLL output phae i The i i time - domai ca be expreed a The filter repoe i the Aumig a ecod - order type - PLL with a iuoidal out t t e t e o out t o c o out t e e t e e c d d d t d v t t d d v t v t v F

109 Secod-Order Type- PLL Phaelock Acquiitio (Siuoidal ) The PLL phae error i e ref out t ref o t i e e 0 co d i d d 0 Differetiatig thi twice w.r.t. time yield the followig oliear differetial equatio i e e t e t 0 0 e out 09

110 Secod-Order Type- PLL Phaelock Acquiitio (Siuoidal ) For thi Secod - Order Type - PLL, the atural frequecy ad dampig factor are, 4 Subtitutig thi ito the oliear differetial equatio yield the followig e co i 0 e e e o cloed form olutio exit, ad umerical techique are required to olve 0

111 Secod-Order Type- PLL Phaelock Acquiitio (Siuoidal ) co e i 0 e e e Acquiitio with a phae error ad e e v time Phae Plae Plot : v e e

112 Secod-Order PLL Phae Plae Plot (Siuoidal ) A utable igularity i called a Saddle Poit A trajectory that termiate o a addle poit i called a Separatrix e co i 0 e e e If a trajectory lie betwee the eparatrice, it will lock without cycle lippig If a trajectory lie outide the eparatrice, it will cycle lipplig oe or more time before lockig (if at all)

113 Secod-Order PLL Pull-Out Rage ad Lock Time (Siuoidal ) The Pull-Out Rage i the maximum frequecy tep that ca occur before the loop lock without cycle lippig PO.8 for betwee 0.5 ad.4 If a frequecy tep i le tha the pull - out rage, the PLL acquitio t acq t phae t freq for phae error le tha 0% 4 4. f 3 B L time ca be approximated a Here, B L i the PLL oie badwidth B L 0 H f df (Hz) Aumig F, B L 4 (Hz) 3

114 Secod-Order PLL Lockig Outide of the Pull-Out Rage (Siuoidal ) Multiple cycle lip are oberved before the loop lock 4

115 ext Time Phae Detector Circuit 5