256K 8 CMOS FLASH MEMORY

Transcription

1 GENERL ESCRIPTION 256K 8 CMOS FLSH MEMORY The W29C020 is a 2-megabit, 5-volt only CMOS flash memory organized as 256K 8 bits. The device can be written (erased and programmed) in-system with a standard 5V power supply. 2-volt VPP is not required. The unique cell architecture of the W29C020 results in fast write (erase/program) operations with extremely low current consumption compared other comparable 5-volt flash memory products. The device can also be written (erased and programmed) by using standard EPROM programmers. FETURES Single 5-volt write (erase and program) operations Fast page-write operations 28 bytes per page Page write (erase/program) cycle: 0 ms (max.) Effective byte-write (erase/program) cycle time: 39 µs Optional software-protected data write Fast chip-erase operation: 50 ms Two 8 KB boot blocks with lockout Typical page write (erase/program) cycles: 00/K/0K Read access time: 70/90/20 ns Ten-year data retention Software and hardware data protection Low power consumption ctive current: 25 m (typ.) Standby current: 20 µ (typ.) umatic write (erase/program) timing with internal VPP generation End of write (erase/program) detection Toggle bit ata polling Latched address and data ll inputs and outputs directly TTL compatible JEEC standard byte-wide pinouts vailable packages: 32-pin 600 mil IP, 450 mil SOP, TSOP, and 32-pin PLCC Publication Release ate: February Revision 3

2 PIN CONFIGURTIONS BLOCK IGRM NC pin IP V V VSS CONTROL OUTPUT BUFFER Q0.. Q Q7 Q0 Q Q2 GN N C V / W E Q6 Q5 Q4 Q ECR 8K Byte Boot Block (Optional) CORE RRY 8K Byte Boot Block (Optional) pin PLCC Q Q7 PIN ESCRIPTION V NC Q Q2 G N Q3 Q4 Q5 Q Q7 Q6 Q5 Q pin 25 9 TSOP 24 Q3 GN Q2 Q 2 2 Q SYMBOL PIN NME 0 7 ddress Inputs Q0 Q7 ata Inputs/Outputs Chip Enable Output Enable Write Enable V GN NC Power Supply Ground No Connection - 2 -

3 FUNCTIONL ESCRIPTION Read Mode The read operation of the W29C020 is controlled by and, both of which have be low for the host obtain data from the outputs. is used for device selection. When is high, the chip is de-selected and only standby power will be consumed. is the output control and is used gate data from the output pins. The data bus is in high impedance state when either or is high. Refer the read cycle timing waveforms for further details. Page Write Mode The W29C020 is written (erased/programmed) on a page basis. Every page contains 28 bytes of data. If a byte of data within a page is be changed, data for the entire page must be loaded in the device. ny byte that is not loaded will be erased "FF hex" during the write operation of the page. The write operation is initiated by forcing and low and high. The write procedure consists of two steps. Step is the byte-load cycle, in which the host writes the page buffer of the device. Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are simultaneously written in the memory array for non-volatile srage. uring the byte-load cycle, the addresses are latched by the falling edge of either or, whichever occurs last. The data are latched by the rising edge of either or, whichever occurs first. If the host loads a second byte in the page buffer within a byte-load cycle time (TBLC) of 200 µs after the initial byte-load cycle, the W29C020 will stay in the page load cycle. dditional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal write (erase/program) cycle will start if no additional byte is loaded in the page buffer 7 7 specify the page address. ll bytes that are loaded in the page buffer must have the same page address. 0 6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required. In the internal write cycle, all data in the page buffers, i.e., 28 bytes of data, are written simultaneously in the memory array. Before the completion of the internal write cycle, the host is free perform other tasks such as fetching data from other locations in the system prepare write the next page. Software-protected ata Write The device provides a JEEC-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a three-byte command sequence (with specific data a specific address) be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down. The W29C020 is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-byte command sequence cycle. Once enabled, the software data protection Publication Release ate: February Revision 3

4 will remain enabled unless the disable commands are issued. power transition will not reset the software data protection feature. To reset the device unprotected mode, a six-byte command sequence is required. For information about specific codes, see the Command Codes for Software ata Protection in the Table of Operating Modes. For information about timing waveforms, see the timing diagrams below. Hardware ata Protection The integrity of the data sred in the W29C020 is also hardware protected in the following ways: () Noise/Glitch Protection: pulse of less than 5 ns in duration will not initiate a write cycle. (2) V Power Up/own etection: The write operation is inhibited when V is less than 2.5V. (3) Write Inhibit Mode: Forcing low, high, or high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) V power-on delay: When V reaches its sense level, the device will aumatically timeout for 5 ms before any write (erase/program) operation. Chip Erase Modes The entire device can be erased by using a six-byte software command code. See the Software Chip Erase Timing iagram. Boot Block Operation There are two boot blocks (8K bytes each) in this device, which can be used sre boot code. One of them is located in the first 8K bytes and the other is located in the last 8K bytes of the memory. The first 8K or last 8K of the memory can be set as a boot block by using a seven-byte command sequence. See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed by the regular programming method. Once the boot block programming lockout feature is activated, the chip erase function will be disabled. In order detect whether the boot block feature is set on the two 8K blocks, users can perform a six-byte command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout etection for specific code), and then read from address "00002 hex" (for the first 8K bytes) or "3FFF2 hex" (for the last 8K bytes). If the output data is "FF hex," the boot block programming lockout feature is activated; if the output data is "FE hex," the lockout feature is deactivated and the block can be programmed. To return normal operation, perform a three-byte command sequence exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout etection. ata Polling (Q7)- Write Status etection The W29C020 includes a data polling feature indicate the end of a write cycle. When the W29C020 is in the internal write cycle, any attempt read Q7 from the last byte loaded during the page/byte-load cycle will receive the complement of the true data. Once the write cycle is completed. Q7 will show the true data. See the T Polling Timing iagram

5 Toggle Bit (Q6)- Write Status etection In addition data polling, the W29C020 provides another method for determining the end of a write cycle. uring the internal write cycle, any consecutive attempts read Q6 will produce alternating 0's and 's. When the write cycle is completed, this ggling between 0's and 's will sp. The device is then ready for the next operation. See Toggle Bit Timing iagram. Product Identification The product I operation outputs the manufacturer code and device code. The programming equipment aumatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed through software or by hardware operation. In the software access mode, a six-byte command sequence can be used access the product I. read from address "00000 hex" outputs the manufacturer code " hex." read from address "0000 hex" outputs the device code "45 hex." The product I operation can be terminated by a three-byte command sequence. In the hardware access mode, access the product I is activated by forcing and low, high, and raising 9 2 volts. TBLE OF OPERTING MS Operating Mode Selection Operating Range: 0 70 C (mbient Temperature), V = 5V ±0%, VSS = 0V, VHH = 2V M PINS RESS Q. Read VIL VIL VIH IN out Write VIL VIH VIL IN in Standby VIH X X X High Z Write Inhibit X VIL X X High Z/OUT X X VIH X High Z/OUT Output isable X VIH X X High Z 5-Volt Software Chip Erase VIL VIH VIL IN IN Product I VIL VIL VIH 0 = VIL; 7 = VIL; 9 = VHH VIL VIL VIH 0 = VIH; 7 = VIL; 9 = VHH Manufacturer Code (Hex) evice Code 45 (Hex) Publication Release ate: February Revision 3

6 Command Codes for Software ata Protection BYTE SEQUEN TO ENBLE PROTECTION TO ISBLE PROTECTION RESS T RESS T 0 Write 5555H H 5555H H Write 2H 55H 2H 55H 2 Write 5555H 0H 5555H 80H 3 Write H H 4 Write - - 2H 55H 5 Write H 20H Software ata Protection cquisition Flow Software ata Protection Enable Flow Software ata Protection isable Flow Load data Load data address 2 address 2 Load data 0 Load data 80 (Optional page-load operation) Sequentially load up 28 bytes of page data Load data Pause 0 ms address 2 Exit Load data 20 Pause 0 ms Exit Notes for software program code: ata Format: Q7 Q0 (Hex) ddress Format: 4 0 (Hex) - 6 -

7 Command Codes for Software Chip Erase BYTE SEQUEN RESS T 0 Write 5555H H Write 2H 55H 2 Write 5555H 80H 3 Write 5555H H 4 Write 2H 55H 5 Write 5555H 0H Software Chip Erase cquisition Flow Load data address 2 Load data 80 Load data address 2 Load data 0 Pause 50 ms Notes for software chip erase: ata Format: Q7 Q0 (Hex) ddress Format: 4 0 (Hex) Exit Publication Release ate: February Revision 3

8 Command Codes for Product Identification and Boot Block Lockout etection BYTE SEQUEN LTERNTE PROUCT (7) IENTIFICTION/BOOT BLOCK LOCKOUT ETECTION ENTRY SOFTWRE PROUCT IENTIFICTION/BOOT BLOCK LOCKOUT ETECTION ENTRY SOFTWRE PROUCT IENTIFICTION/BOOT BLOCK LOCKOUT ETECTION EXIT RESS T RESS T RESS T 0 Write H H 5555H H Write H 55H 2H 55H 2 Write H 80H 5555H F0H 3 Write H H Write - - 2H 55H Write H 60H - - Pause 0 µs Pause 0 µs Pause 0 µs Software Product Identification and Boot Block Lockout etection cquisition Flow Product Identification Entry () Load data Product Identification and Boot Block Lockout etection Mode (3) Product Identification Exit () address 2 Read address = data = (2) Load data Load data 80 Read address = 0000 data = 45 (2) address 2 Load data Read address = data = FF/FE (4) Load data F0 address 2 Read address = 3FFF2 data = FF/FE (5) Pause 0 µ S Load data 60 Normal Mode (6) Pause 0 µ S Notes for software product identification/boot block lockout detection: () ata Format: Q7 Q0 (Hex); ddress Format: 4 0 (Hex) (2) 6 = VIL; manufacture code is read for 0 = VIL; device code is read for 0 = VIH. (3) The device does not remain in identification and boot block (address 0002 Hex/3FFF2 Hex respond first 8K/last 8K) lockout detection mode if power down. (4), (5) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is inactivated and the block can be programmed. (6) The device returns standard operation mode. (7) This product supports both the JEEC standard 3 byte command code sequence and original 6 byte command code sequence. For new designs, Winbond recommends that the 3 byte command code sequence be used

9 Command Codes for Boot Block Lockout Enable BYTE SEQUEN BOOT BLOCK LOCKOUT FETURE SET ON FIRST 8K RESS BOOT BLOCK BOOT BLOCK LOCKOUT FETURE SET ON LST 8K RESS BOOT BLOCK RESS T RESS T 0 Write 5555H H 5555H H Write 2H 55H 2H 55H 2 Write 5555H 80H 5555H 80H 3 Write 5555H H 5555H H 4 Write 2H 55H 2H 55H 5 Write 5555H 40H 5555H 40H 6 Write 00000H 00H 3FFFFH FFH Pause 0 ms Pause 0 ms Boot Block Lockout Enable cquisition Flow Boot Block Lockout Feature Set on First 8K ddress Boot Block Boot Block Lockout Feature Set on Last 8K ddress Boot Block Load data Load data address 2 address 2 Load data 80 Load data 80 Load data Load data address 2 address 2 Load data 40 Load data 40 Load data 00 address Load data FF address 3FFFF Pause 0 ms Pause 0 ms Notes for boot block lockout enable:. ata Format: Q7 Q0 (Hex) 2. ddress Format: 4 0 (Hex) 3. If you have any questions about this commend sequence, please contact the local distribur or Winbond Electronics Corp. Publication Release ate: February Revision 3

10 C CHRCTERISTICS bsolute Maximum Ratings PRMETER RTING UNIT Power Supply Voltage VSS Potential V Operating Temperature C Srage Temperature C.C. Voltage on ny Pin Ground Potential Except V +.0 V Transient Voltage (<20 ns ) on ny Pin Ground Potential -.0 V +.0 V Voltage on 9 and Pin Ground Potential V Note: Exposure conditions beyond those listed under bsolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (V = 5.0V ±0%, VSS = 0V, T = 0 70 C) PRMETER SYM. TEST CONITIONS LIMITS UNIT Power Supply Current ICC = = VIL, = VIH, all Qs open Standby V Current (TTL input) Standby V Current (CMOS input) ISB ISB2 ddress inputs = VIL/VIH, at f = 5 MHz = VIH, all Qs open Other inputs = VIL/VIH = V -0.3V, all Qs open MIN. TYP. MX m m µ Input Leakage Current ILI VIN = GN V µ Output Leakage Current ILO VIN = GN V µ Input Low Voltage VIL V Input High Voltage VIH V Output Low Voltage VOL IOL = 2.0 m V Output High Voltage VOH IOH = -400 µ V Output High Voltage CMOS VOH2 IOH = -00 µ; VCC = 4.5V V - 0 -

11 Power-up Timing PRMETER SYMBOL TYPICL UNIT Power-up Read Operation TPU. RE 00 µs Power-up Write Operation TPU. WRITE 5 ms CPCITN (V = 5.0V, T = 25 C, f = MHz) PRMETER SYMBOL CONITIONS MX. UNIT Q Pin Capacitance CQ VQ = 0V 2 pf Input Pin Capacitance CIN VIN = 0V 6 pf C CHRCTERISTICS C Test Conditions (V = 5.0V ±0% for 90 ns and 20 ns; V = 5.0V ±5% for 70 ns) PRMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V 3V <5 ns.5v/.5v CONITIONS TTL Gate and CL = 00 pf for 90/20 ns CL = 30 pf for 70 ns C Test Load and Waveform +5V.8KΩ OUT 00 pf for 90/20 ns 30 pf for 70 ns (Including Jig and Scope).3KΩ Input Output 3V 0V Test Point.5V.5V Test Point Publication Release ate: February Revision 3

12 C Characteristics, continued Read Cycle Timing Parameters (V = 5.0V ±0% for 90 ns and 20 ns; V = 5.0V ±5% for 70 ns, VSS = 0V, T = 0 70 C) PRMETER SYM. W29C W29C W29C020-2 UNIT MIN. MX. MIN. MX. MIN. MX. Read Cycle Time TRC ns Chip Enable ccess Time T ns ddress ccess Time T ns Output Enable ccess Time T ns High High-Z Output TCHZ ns High High-Z Output TOHZ ns Output Hold from ddress change TOH ns Byte/Page-write Cycle Timing Parameters PRMETER SYMBOL MIN. TYP. MX. UNIT Write Cycle (erase and program) TWC ms ddress Setup Time TS ns ddress Hold Time TH ns and Setup Time TCS ns and Hold Time TCH ns High Setup Time TS ns High Hold Time TH ns Pulse Width TCP ns Pulse Width TWP ns High Width TWPH ns ata Setup Time TS ns ata Hold Time TH ns Byte Load Cycle Time TBLC µs Note: ll C timing signals observe the following guideline for determining setup and hold times: Reference level is VIH for high-level signal and VIL for low-level signal

13 C Characteristics, continued T Polling Characteristics () PRMETER SYMBOL MIN. TYP. MX. UNIT ata Hold Time TH ns Hold Time TH ns Output elay (2) T ns Write Recovery Time TWR ns Notes: () These parameters are characterized and not 00% tested. (2) See T spec in.c. Read Cycle Timing Parameters. Toggle Bit Characteristics () PRMETER SYMBOL MIN. TYP. MX. UNIT ata Hold Time TH ns Hold Time TH ns Output elay (2) T ns High Pulse THP ns Write Recovery Time TWR ns Notes: () These parameters are characterized and not 00% tested. (2) See T spec in.c. Read Cycle Timing Parameters. TIMING WVEFORMS Read Cycle Timing iagram TRC ddress 7-0 T T VIH TOHZ Q7-0 High-Z ata Valid TOH ata Valid T CHZ High-Z T Publication Release ate: February Revision 3

14 Timing Waveforms, continued Controlled Write Cycle Timing iagram T S T H T WC ddress 7-0 T CS T CH T S TH T WP T WPH T S Q7-0 ata Valid T H Internal write starts Controlled Write Cycle Timing iagram TS TH TWC ddress 7-0 TCP T WPH T S TH TCS TCH Q7-0 High Z TS ata Valid TH Internal Write Starts - 4 -

15 Timing Waveforms, continued Page Write Cycle Timing iagram TWC ddress 7-0 Q7-0 TWP T WPH TBLC Byte 0 Byte Byte 2 Byte N- Internal Write Start Byte N T Polling Timing iagram ddress 5-0 T H Q7 TH T HIGH-Z TWR Publication Release ate: February Revision 3

16 Timing Waveforms, continued Toggle Bit Timing iagram T H Q6 T H T HIGH-Z T WR Page Write Timing iagram Software ata Protection Mode Three-byte sequence for software data protection mode Byte/page load cycle starts TWC ddress Q TWP TWPH TBLC SW0 SW SW2 Word 0 Word N- Word N (last word) Internal write starts - 6 -

17 Timing Waveforms, continued Reset Software ata Protection Timing iagram Six-byte sequence for resetting software data protection mode TWC ddress Q T WP T WPH TBLC SW0 SW SW2 SW3 SW4 SW5 Internal programming starts Software Chip Erase Timing iagram Six-byte code for 5V-only software chip erase TWC ddress Q T WP T WPH T BLC SW0 SW SW2 SW3 SW4 SW5 Internal erasing starts Publication Release ate: February Revision 3

18 ORERING INFORMTION PRT NO. CSS TIME (ns) POR SUPPLY CURRENT MX. (m) STNBY V CURRENT MX. (m ) PCKGE CYCLING W29C mil IP 00 W29C mil IP 00 W29C mil IP 00 W29C020S mil SOP 00 W29C020S mil SOP 00 W29C020S mil SOP 00 W29C020T Type one TSOP 00 W29C020T Type one TSOP 00 W29C020T Type one TSOP 00 W29C020P pin PLCC 00 W29C020P pin PLCC 00 W29C020P pin PLCC 00 W29C mil IP K W29C mil IP K W29C mil IP K W29C020S mil SOP K W29C020S mil SOP K W29C020S mil SOP K W29C020T Type one TSOP K W29C020T Type one TSOP K W29C020T Type one TSOP K W29C020P pin PLCC K W29C020P pin PLCC K W29C020P pin PLCC K W29C020-70B mil IP 0K W29C020-90B mil IP 0K W29C020-2B mil IP 0K W29C020S-70B mil SOP 0K W29C020S-90B mil SOP 0K W29C020S-2B mil SOP 0K W29C020T-70B Type one TSOP 0K W29C020T-90B Type one TSOP 0K W29C020T-2B Type one TSOP 0K W29C020P-70B pin PLCC 0K W29C020P-90B pin PLCC 0K W29C020P-2B pin PLCC 0K Notes:. Winbond reserves the right make changes its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure

19 PCKGE IMENSIONS 32-pin P-IP E 2 L S B e B Base Plane Seating Plane a E e c Symbol B 2 B c E E imension in inches imension in mm Min. Nom. Max. Min. Nom. Max e L a e S Notes:.imensions Max. & S include mold flash or tie bar burrs. 2.imension E does not include interlead flash. 3.imensions & E. include mold mismatch and are determined at the mold parting line. 4.imension B does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches. 6.General appearance spec. should be based on final visual inspection spec. 32-pin SO Wide Body 32 b 7 6 E H E L e etail F Symbol b c E e H E L y θ 2 L E imension in Inches Min. Nom. Max. Min. Nom. Max imension in mm S S Seating Plane y e 2 e See etail F L E c Notes:. imensions Max. & S include mold flash or tie bar burrs. 2. imension b does not include dambar protrusion/intrusion. 3. imensions & E include mold mismatch and determined at the. mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec. Publication Release ate: February Revision 3

20 Package imensions, continued 32-pin PLCC H E E H G Symbol 2 b b c E e imension in Inches imension in mm Min. Nom. Max. Min. Nom. Max G c G E H H E L y θ L Notes: θ Seating Plane e G E b b 2 y. imensions & E do not include interlead flash. 2. imension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc. 32-pin TSOP H c Symbol imension in Inches imension in mm Min. Nom. Max. Min. Nom. Max M e E b c (0.004) b E H e θ L L 2 Y L L Y θ Note: Controlling dimension: Millimeters

21 VERSION HISTORY VERSION TE PGE ESCRIPTION pr. 997 Initial Issued 2 Nov , 8 Correct the address from 3FFF2 7FFF2 9 Correct the boot block from 8K 6K 5 Modify page write cycle timing diagram waveform, 8 elete cycling 00K item 3 Feb dd. pause 0 ms 7 dd. pause 50 ms 8 Correct the time from 0 ms 0 µs, 8 dd. cycling 00 item Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: FX: Voice & Fax-on-demand: Taipei Office F, No. 5, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: FX: Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, 23 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: FX: Winbond Electronics North merica Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab N. First Street, San Jose, C 9534, U.S.. TEL: FX: Note: ll data and specifications are subject change without notice. Publication Release ate: February Revision 3