512K 8 CMOS FLASH MEMORY

Transcription

1 GENERL ESCRIPTION 52K 8 CMOS FLSH MEMORY The W29C040 is a 4-megabit, 5-volt only CMOS page mode Flash Memory organized as 52K 8 bits. The device can be written (erased and programmed) in-system with a standard 5V power supply. 2-volt VPP is not required. The unique cell architecture of the W29C040 results in fast write (erase/ program) operations with extremely low current consumption (compared other comparable 5-volt flash memory products.) The device can also be erased and programmed by using standard EPROM programmers. FETURES Single 5-volt write (erase and program) operations Fast page-write operations 256 bytes per page Page write (erase/program) cycle: 5 ms (typ.) Effective byte-write (erase/program) cycle time: 9.5 µs Optional software-protected data write Fast chip-erase operation: 50 ms Two 6 KB boot blocks with lockout Page write (erase/program) cycles: 50K (typ.) Read access time: 70/90/20 ns Ten-year data retention Software and hardware data protection Low power consumption ctive current: 25 m (typ.) Standby current: 20 µ (typ.) umatic write (erase/program) timing with internal VPP generation End of write (erase/program) detection Toggle bit ata polling Latched address and data ll inputs and outputs directly TTL compatible JEEC standard byte-wide pinouts vailable packages: 32-pin 600 mil IP, TSOP and PLCC Publication Release ate: pril 5, Revision 0

2 - 2 - PIN CONFIGURTIONS Q Q Q 2 V s s Q 3 Q 4 Q 5 Q Q7 2 6 V # W E pin PLCC Q0 Q Q2 Vss 0 Q7 Q6 Q5 Q4 Q3 32-pin TSOP V Q0 Q Q2 Vss V Q7 Q6 Q5 Q4 Q pin IP 8 BLOCK IGRM ECOER CORE RRY CONTROL OUTPUT BUFFER Q0 Q7.. 6K Byte Boot Block (Optional) 6K Byte Boot Block (Optional) V V SS PIN ESCRIPTION SYMBOL PIN NME 0 8 ddress Inputs Q0 Q7 ata Inputs/Outputs Chip Enable Output Enable Write Enable V Power Supply VSS Ground

3 FUNCTIONL ESCRIPTION Read Mode The read operation of the W29C040 is controlled by and, both Chip of which have be low for the host obtain data from the outputs. is used for device selection. When is high, the chip is de-selected and only standby power will be consumed. is the output control and is used gate data from the output pins. The data bus is in high impedance state when either or is high. Refer the read cycle timing waveforms for further details. Page Write Mode The W29C040 is written (erased/programmed) on a page basis. Every page contains 256 bytes of data. If a byte of data within a page is be changed, data for the entire page must be loaded in the device. ny byte that is not loaded will be erased "FF hex" during the write operation of the page. The write operation is initiated by forcing and low and high. The write procedure consists of two steps. Step is the byte-load cycle, in which the host writes the page buffer of the device. Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are simultaneously written in the memory array for non-volatile srage. uring the byte-load cycle, the addresses are latched by the falling edge of either or, whichever occurs last. The data are latched by the rising edge of either or, whichever occurs first. If the host loads a second byte in the page buffer within a byte-load cycle time (TBLC) of 200 µs after the initial byte-load cycle, the W29C040 will stay in the page load cycle. dditional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal write (erase/program) cycle will start if no additional byte is loaded in the page buffer. 8 8 specify the page address. ll bytes that are loaded in the page buffer must have the same page address. 0 7 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required. In the internal write cycle, all data in the page buffers, i.e., 256 bytes of data, are written simultaneously in the memory array. The typical write (erase/program) time is 5 ms. The entire memory array can be written in 0.4 seconds. Before the completion of the internal write cycle, the host is free perform other tasks such as fetching data from other locations in the system prepare write the next page. Software-protected ata Write The device provides a JEEC-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a three-byte command sequence (with specific data a specific address) be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down. The W29C040 is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-byte command sequence cycle. Once enabled, the software data protection will remain enabled unless the disable commands are issued. power transition will not reset the Publication Release ate: pril 5, Revision 0

4 software data protection feature. To reset the device unprotected mode, a six-byte command sequence is required. For information about specific codes, see the Command Codes for Software ata Protection in the Table of Operating Modes. For information about timing waveforms, see the timing diagrams below. Hardware ata Protection The integrity of the data sred in the W29C040 is also hardware protected in the following ways: () Noise/Glitch Protection: pulse of less than 5 ns in duration will not initiate a write cycle. (2) V Power Up/own etection: The write and read operation are inhibited when V is less than 2.5V. (3) Write Inhibit Mode: Forcing low, high, or high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) V power-on delay: When V has reach its sense level, the device will aumatically time-out 0 ms before any write (erase/program) operation. Chip Erase Modes The entire device can be erased by using a six-byte software command code. See the Software Chip Erase Timing iagram. Boot Block Operation There are two boot blocks (6K bytes each) in this device, which can be used sre boot code. One of them is located in the first 6K bytes and the other is located in the last 6K bytes of the memory. The first 6K or last 6K of the memory can be set as a boot block by using a seven-byte command sequence. See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); a regular programming method can change other memory locations. Once the boot block programming lockout feature is activated, the chip erase function will be disabled. In order detect whether the boot block feature is set on the two 6K blocks, users can perform a six-byte command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout etection for specific code), and then read from address "00002 hex" (for the first 6K bytes) or "7FFF2 hex" (for the last 6K bytes). If the output data is "FF hex," the boot block programming lockout feature is activated; if the output data is "FE hex," the lockout feature is inactivated and the block can be programmed. To return normal operation, perform a three-byte command sequence exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout etection. ata Polling (Q7)- Write Status etection The W29C040 includes a data polling feature indicate the end of a write cycle. When the W29C040 is in the internal write cycle, any attempt read Q7 of the last byte loaded during the page/byte-load cycle will receive the complement of the true data. Once the write cycle is completed. Q7 will show the true data. See the #T Polling Timing iagram. Toggle Bit (Q6)- Write Status etection - 4 -

5 In addition data polling, the W29C040 provides another method for determining the end of a write cycle. uring the internal write cycle, any consecutive attempts read Q6 will produce alternating 0's and 's. When the write cycle is completed, this ggling between 0's and 's will sp. The device is then ready for the next operation. See Toggle Bit Timing iagram. Product Identification The product I operation outputs the manufacturer code and device code. Programming equipment aumatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-byte command sequence can be used access the product I. read from address "00000 hex" outputs the manufacturer code " hex." read from address "0000 hex" outputs the device code "46 hex." The product I operation can be terminated by a three-byte command sequence. In the hardware access mode, access the product I is activated by forcing and low, high, and raising 9 2 volts. Note: The hardware SI read function is not included in all parts; please refer Ordering Information for details. TBLE OF OPERTING MOES Operating Mode Selection Operating Range: 0 70 C for normal products, C for W29C040xxxxK, V = 5V ±0 %, VSS = 0V, VHH = 2V MOE PINS RESS Q. Read VIL VIL VIH IN out Write VIL VIH VIL IN in Standby VIH X X X High Z Write Inhibit X VIL X X High Z/OUT X X VIH X High Z/OUT Output isable X VIH X X High Z Product I VIL VIL VIH 0 = VIL; 8 = VIL; 9 = VHH VIL VIL VIH 0 = VIH; 8 = VIL; 9 = VHH Manufacturer Code (Hex) evice Code 46 (Hex) Publication Release ate: pril 5, Revision 0

6 Command Codes for Software ata Protection BYTE SEQUENCE TO ENBLE PROTECTION TO ISBLE PROTECTION RESS T RESS T 0 Write 5555H H 5555H H Write 2H 55H 2H 55H 2 Write 5555H 0H 5555H 80H 3 Write H H 4 Write - - 2H 55H 5 Write H 20H Software ata Protection cquisition Flow Software ata Protection Enable Flow Software ata Protection isable Flow Load data Load data Load data 55 address 2 Load data 55 address 2 Load data 0 Load data 80 (Optional page-load operation) Sequentially load up 256 bytes of page data Load data Wait for 0 ms or ggle/polling completed Exit Load data 55 address 2 Load data 20 Wait for 0 ms Notes for software program code: ata Format: Q7 Q0 (Hex) ddress Format: 4 0 (Hex) Exit - 6 -

7 Command Codes for Software Chip Erase BYTE SEQUENCE RESS T 0 Write 5555H H Write 2H 55H 2 Write 5555H 80H 3 Write 5555H H 4 Write 2H 55H 5 Write 5555H 0H Software Chip Erase cquisition Flow Load data Load data 55 address 2 Load data 80 Load data Load data 55 address 2 Load data 0 W ait for 50 ms or ggle/polling completed Notes for software chip erase: ata Format: Q7 Q0 (Hex) ddress Format: 4 0 (Hex) Exit Publication Release ate: pril 5, Revision 0

8 Command Codes for Product Identification and Boot Block Lockout etection BYTE SEQUENCE LTERNTE PROUCT (7) IENTIFICTION/BOOT BLOCK LOCKOUT ETECTION ENTRY SOFTWRE PROUCT IENTIFICTION/BOOT BLOCK LOCKOUT ETECTION EXIT RESS T RESS T 0 Write H H Write H 55H 2 Write H F0H 3 Write Write Write Pause 0 µs Pause 0 µs Software Product Identification and Boot Block Lockout etection cquisition Flow Product Identification Entry () Load data Product Identification and Boot Block Lockout etection Mode (3) Product Identification Exit () Load data 55 address 2 Read address = data = (2) Load data Load data 90 Read address = 0000 data = 46 (2) Load data 55 address 2 Read address = data = FF/FE (4) Load data F0 Read address = 7FFF2 data = FF/FE (5) Pause 0 us Normal Mode (6) Notes for software product identification/boot block lockout detection: () ata Format: Q7 Q0 (Hex); ddress Format: 4 0 (Hex) (2) 8 = VIL; manufacture code is read for 0 = VIL; device code is read for 0 = VIH. (3) The device does not remain in identification and boot block (address 0002 Hex/7FFF2 Hex respond first 6K/last 6K) lockout detection mode if power down. (4), (5) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is inactivated and the block can be programmed. (6) The device returns standard operation mode. (7) This product supports both the JEEC standard 3 bytes command code sequence and original 6 byte command code sequence. For new designs, Winbond recommends that the 3 bytes command code sequence be used

9 Command Codes for Boot Block Lockout Enable BYTE SEQUENCE BOOT BLOCK LOCKOUT FETURE SET ON FIRST 6K RESS BOOT BLOCK BOOT BLOCK LOCKOUT FETURE SET ON LST 6K RESS BOOT BLOCK RESS T RESS T 0 Write 5555H H 5555H H Write 2H 55H 2H 55H 2 Write 5555H 80H 5555H 80H 3 Write 5555H H 5555H H 4 Write 2H 55H 2H 55H 5 Write 5555H 40H 5555H 40H 6 Write 00000H 00H 7FFFFH FFH Pause 0 ms Pause 0 ms Boot Block Lockout Enable cquisition Flow Boot Block Lockout Feature Set on First 6K ddress Boot Block Load data Boot Block Lockout Feature Set on Last 6K ddress Boot Block Load data Load data 55 address 2 Load data 55 address 2 Load data 80 Load data 80 Load data Load data Load data 55 address 2 Load data 55 address 2 Load data 40 Load data 40 Load data 00 address Load data FF address 7FFFF W ait for 0 ms W ait for 0 ms Notes for boot block lockout enable:. ata Format: Q 7 Q0 (Hex) 2. ddress Format: 4 0 (Hex) 3. If you have any questions about this command sequence, please contact the local distribur or Winbond Electronics Corp. Publication Release ate: pril 5, Revision 0

10 ata Polling cquisition Flow ata Polling Byte Program Initiated Read Q7 No Is Q7= true data? Yes Write Completed ata Toggle cquisition Flow Toggle Bit Byte Program/ Secr Erase Initiated Read byte Read same byte No oes Q6 match? Yes Write Completed - 0 -

11 C CHRCTERISTICS bsolute Maximum Ratings PRMETER RTING UNIT Power Supply Voltage VSS Potential V Operating Temperature C Srage Temperature C.C. Voltage on ny Pin Ground Potential Except V +.0 V Transient Voltage (<20 ns) on ny Pin Ground Potential -.0 V +.0 V Voltage on 9 and Pin Ground Potential V Note: Exposure conditions beyond those listed under bsolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (V = 5.0V ±0 %, VSS = 0V, T = 0 70 C for normal products, C for W29C040xxxxK ) PRMETER SYM. TEST CONITIONS LIMITS UNIT Power Supply Current ICC = = VIL, = VIH, all Qs open ddress inputs = VIL/VIH, at f = 5 MHz Standby V Current ISB = VIH, all Qs open (TTL input) Other inputs = VIL/VIH Standby V Current (CMOS input) ISB2 = V -0.3V, all Qs open MIN. TYP. MX m m µ Input Leakage Current ILI VIN = VSS V µ Output Leakage Current ILO VIN = VSS V µ Input Low Voltage VIL V Input High Voltage VIH For PLCC and TSOP pkg V For IP pkg V Output Low Voltage VOL IOL = 2.0 m V Output High Voltage VOH IOH = -400 µ V Output High Voltage CMOS VOH2 IOH = -00 µ; V = 4.5V V Publication Release ate: pril 5, Revision 0

12 Power-up Timing PRMETER SYMBOL TYPICL UNIT Power-up Read Operation TPU. RE 00 µs Power-up Write Operation TPU. WRITE 0 ms CPCITNCE (V = 5.0V, T = 25 C, f = MHz) PRMETER SYMBOL CONITIONS MX. UNIT Q Pin Capacitance CQ VQ = 0V 2 pf Input Pin Capacitance CIN VIN = 0V 6 pf C CHRCTERISTICS C Test Conditions (V = 5.0V ±0 % for 70, 90,20 ns) PRMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V 3V <5 ns.5v/.5v CONITIONS TTL Gate and CL = 00 pf for 90/20 ns CL = 30 pf for 70 ns C Test Load and Waveform +5V.8KΩ OUT 00 pf for 90/20nS 30 pf for 70nS (Including Jig and Scope).3KΩ Input Output 3V 0V Test Point.5V.5V Test Point - 2 -

13 C Characteristics, continued Read Cycle Timing Parameters (V = 5.0V ±0 % VSS = 0V, T = 0 70 C for normal products, C for W29C040xxxxK) PRMETER SYM. W29C W29C W29C040-2 UNIT MIN. MX. MIN. MX. MIN. MX. Read Cycle Time TRC ns Chip Enable ccess Time TCE ns ddress ccess Time T ns Output Enable ccess Time TOE ns High High-Z Output TCHZ ns High High-Z Output TOHZ ns Output Hold from ddress Change TOH ns Byte/Page-write Cycle Timing Parameters PRMETER SYM. MIN. TYP. MX. UNIT Write Cycle (erase and program) TWC ms ddress Setup Time TS ns ddress Hold Time TH ns and Setup Time TCS ns and Hold Time TCH ns High Setup Time TOES ns High Hold Time TOEH ns Pulse Width TCP ns Pulse Width TWP ns High Width TWPH ns ata Setup Time TS ns ata Hold Time TH ns Byte Load Cycle Time TBLC µs Notes: ll C timing signals observe the following guideline for determining setup and hold times: () High level signal's reference level is VIH (2) Low level signal's reference level is VIL Publication Release ate: pril 5, Revision 0

14 C Characteristics, continued #T Polling Characteristics () PRMETER SYMBOL MIN. TYP. MX. UNIT ata Hold Time TH ns Hold Time TOEH ns Output elay (2) TOE ns Write Recovery Time TWR ns Notes: () These parameters are characterized and not 00% tested. (2) See TOE spec in.c. Read Cycle Timing Parameters. Toggle Bit Characteristics () PRMETER SYMBOL MIN. TYP. MX. UNIT ata Hold Time TH ns Hold Time TOEH ns Output elay (2) TOE ns High Pulse TOEHP ns Write Recovery Time TWR ns Notes: () These parameters are characterized and not 00% tested. (2) See TOE spec in.c. Read Cycle Timing Parameters. TIMING WVEFORMS Read Cycle Timing iagram T RC ddress 8-0 TCE TOE VIH T OHZ Q7-0 High-Z ata Valid TOH ata Valid T CHZ High-Z T - 4 -

15 Timing Waveforms, continued Controlled Write Cycle Timing iagram T S T H T WC ddress 8-0 T CS T CH T OES TOEH T WP T WPH T S Q7-0 ata Valid T H Internal write starts Controlled Write Cycle Timing iagram TS TH TWC ddress 8-0 TCP TWPH T OES TOEH TCS TCH Q7-0 High Z TS ata Valid TH Internal Write Starts Publication Release ate: pril 5, Revision 0

16 Timing Waveforms, continued Page Write Cycle Timing iagram TWC ddress 8-0 Q7-0 TWP T WPH TBLC Byte 0 Byte Byte 2 Byte N- Internal Write Start Byte N #T Polling Timing iagram ddress 8-0 TOEH Q7 TH TOE HIGH-Z TWR - 6 -

17 Timing Waveforms, continued Toggle Bit Timing iagram TOEH Q6 TH TOE HIGH-Z TWR Page Write Timing iagram Software ata Protection Mode Three-byte sequence for software data protection mode Byte/page load cycle starts TWC ddress Q TWP TBLC TWPH SW0 SW SW2 Byte 0 Byte N- Byte N (Last Byte) Internal write starts Publication Release ate: pril 5, Revision 0

18 Timing Waveforms, continued Reset Software ata Protection Timing iagram Six-byte sequence for resetting software data protection mode TWC ddress Q T WP TBLC T WPH SW0 SW SW2 SW3 SW4 SW5 Internal programming starts 5 Volt-only Software Chip Erase Timing iagram Six-byte code for 5V-only software chip erase TWC ddress Q T WP T BLC T WPH SW0 SW SW2 SW3 SW4 SW5 Internal erasing starts - 8 -

19 ORERING INFORMTION PRT NO. CCESS TIME (ns) POWER SUPPLY CURRENT MX. (m) OPERTING TEMP. ( C) PCKGE CYCLING (K) (MIN.) HRWRE SI RE FUNCTION W29C mil IP Y W29C mil IP Y W29C040T Type one TSOP Y W29C040T Type one TSOP Y W29C040P pin PLCC Y W29C040P pin PLCC Y W29C040-90N mil IP N W29C040-2N mil IP N W29C040T-90N Type one TSOP N W29C040T-2N Type one TSOP N W29C040P-90N pin PLCC N W29C040P-2N pin PLCC N W29C040-90B mil IP 0 Y W29C040T-70B Type one TSOP 0 Y W29C040T-90B Type one TSOP 0 Y W29C040P-70B pin PLCC 0 Y W29C040P-90B pin PLCC 0 Y W29C040-90BN mil IP 0 N W29C040T70BN Type one TSOP 0 N W29C040T90BN Type one TSOP 0 N W29C040P70BN pin PLCC 0 N W29C040P90BN pin PLCC 0 N W29C040P-70K pin PLCC 0 Y W29C040P-90K pin PLCC 0 Y W29C040T-70K Type one TSOP 0 Y W29C040T-90K Type one TSOP 0 Y Notes:. Winbond reserves the right make changes its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. In Hardware SI Read column: Y = with SI read function; N = without SI read function. Publication Release ate: pril 5, Revision 0

20 HOW TO RE THE TOP MRKING Example: The p marking of 32-pin TSOP W29C040T-90 W29C040T OBS st line: winbond logo 2 nd line: the part number: W29C040T-90 3 rd line: the lot number 4 th line: the tracking code: 49 O B S 49: Packages made in 0, week 49 O: ssembly house I: means SE, O means OSE,...etc. B: IC revision; means version, B means version B,...etc. S: Process code

21 PCKGE IMENSIONS 32-pin P-IP E 2 L S B e B Base Plane Seating Plane a E e c imension in inches imension in mm Symbol Min. Nom. Max. Min. Nom. Max B B c E E e L a e S Notes:.imensions Max. & S include mold flash or tie bar burrs. 2.imension E does not include interlead flash. 3.imensions & E. include mold mismatch and are determined at the mold parting line. 4.imension B does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches 6.General appearance spec. should be based on final visual inspection spec. 32-pin PLCC H E E Symbol 2 imension in Inches imension in mm Min. Nom. Max. Min. Nom. Max H G b b c E e G G E H c H E L y θ L Notes: θ Seating Plane e b b 2 y. imensions & E do not include interlead flash. 2. imension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc. G E Publication Release ate: pril 5, Revision 0

22 Package imensions, continued 32-pin TSOP H c Symbol imension In Inches imension In mm Min. Nom. Max. Min. Nom. Max M e b (0.004) E c b E H e θ L L 2 Y L L Y θ Note: Controlling dimension: Millimeters

23 VERSION HISTORY VERSION TE PGE ESCRIPTION 3 June Correct Power-on elay from 5 ms 0 ms Correct TPU.WRITE (Typ.) from 5 ms 0 ms 4 Oct Correct 40-pin TSOP Package rawing by 32-pin TSOP 9 Correct the ddress from 3FFFF 7FFFF 5 May 999, 2, 8 Modify TCC: 90/20/50 ns 90/20 ns binning, 2, 8, 9 Modify Packages: PIP/SOP/PLCC/TSOP PLCC/TSOP 6 Nov Change Byte Load Cycle Time from 50 µs 200 µs, 2, 8 Modify TCC: 90/20 ns 70/90/20 ns binning Typo Correction Modify Output Load Parameter, 2, 23, 24 dd IP Package 0 dd ggle and polling cquisition Flow 6, 7 Correct the cquisition Flow Wait Time 5, 23 dd in Hardware SI Read Function Note 7 pril 200 Modify VIH from 2.0V 2.2V for IP only (2.0V for PLCC & TSOP; 2.2V for IP) 8 9/2/200,9 Range page write (erase/program) cycles between K/0K (min.) and 5K/50K (typ.) 9 May 6, ,, 3 dd operating range C 9 dd Part No of W29C040xxxxK for ordering information 4 Correct V Power Up/own etection escription 8 Correct Command Codes and cquisition Flow for Software Product Identification and Boot Block Lockout etection 20 HOW TO RE THE TOP MRKING 0 pril 5, dd Important Notice Publication Release ate: pril 5, Revision 0

24 Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, amic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond cusmers using or selling these products for use in such applications do so at their own risk and agree fully indemnify Winbond for any damages resulting from such improper use or sales. Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: FX: Taipei Office 9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 4, Taiwan, R.O.C. TEL: FX: Winbond Electronics Corporation merica 2727 North First Street, San Jose, C 9534, U.S.. TEL: FX: Winbond Electronics Corporation Japan 7F aini-ueno BLG, Shinyokohama Kohoku-ku, Yokohama, TEL: FX: Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan n W. Rd. Shanghai, China TEL: FX: Winbond Electronics (H.K.) Ltd. Unit 9-5, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: FX: Please note that all data and specifications are subject change without notice. ll the trade marks of products and companies mentioned in this data sheet belong their respective owners