128K 8 CMOS FLASH MEMORY

Transcription

1 128K 8 CMOS FLSH MEMORY GENERL ESCRIPTION The W29EE011 is a 1-megabit, 5-volt only CMOS flash memory organized as 128K 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. 12-volt VPP is not required. The unique cell architecture of the W29EE011 results in fast program/erase operations with extremely low current consumption (compared other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. FETURES Single 5-volt program and erase operations Fast page-write operations 128 bytes per page Page program cycle: 10 ms (max.) Effective byte-program cycle time: 39 µs Optional software-protected data write Fast chip-erase operation: 50 ms Read access time: 90/150 ns Page program/erase cycles: 1K/10K Ten-year data retention Software and hardware data protection Low power consumption ctive current: 25 m (typ.) Standby current: 20 µ (typ.) umatic program timing with internal VPP generation End of program detection Toggle bit ata polling Latched address and data TTL compatible I/O JEEC standard byte-wide pinouts vailable packages: 32-pin 600 mil IP, TSOP (8 x 20 mm), STSOP (8 x 14 mm), and PLCC Publication Release ate: February 19, Revision 15

2 PIN CONFIGURTIONS BLOCK IGRM NC pin IP V NC V GN CONTROL OUTPUT BUFFER Q0. Q Q7 Q Q6 Q1 Q2 GN N C V # W E N C Q5 Q4 Q ECOER CORE RRY NC V NC Q pin PLCC Q 1 Q2 G N Q3 Q4 Q5 Q pin Q7 Q6 Q5 Q4 Q3 9 TSOP 24 GN Q Q Q Q PIN ESCRIPTION SYMBOL PIN NME 0 16 ddress Inputs Q0 Q7 ata Inputs/Outputs Chip Enable Output Enable Write Enable V Power Supply GN Ground NC No Connection - 2 -

3 FUNCTIONL ESCRIPTION Read Mode The read operation of the W29EE011 is controlled by and, both of which have be low for the host obtain data from the outputs. is used for device selection. When is high, the chip is de-selected and only standby power will be consumed. is the output control and is used gate data from the output pins. The data bus is in high impedance state when either or is high. Refer the timing waveforms for further details. Page Write Mode The W29EE011 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of data within a page is be changed, data for the entire page must be loaded in the device. ny byte that is not loaded will be erased "FFh" during programming of the page. The write operation is initiated by forcing and low and high. The write procedure consists of two steps. Step 1 is the byte-load cycle, in which the host writes the page buffer of the device. Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously written in the memory array for non-volatile srage. uring the byte-load cycle, the addresses are latched by the falling edge of either or, whichever occurs last. The data are latched by the rising edge of either or, whichever occurs first. If the host loads a second byte in the page buffer within a byte-load cycle time (TBLC) of 200 µs, after the initial byte-load cycle, the W29EE011 will stay in the page load cycle. dditional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal programming cycle will start if no additional byte is loaded in the page buffer within 300 µs (TBLCO) from the last byte-load cycle, i.e., there is no subsequent high--low transition after the last rising edge of specify the page address. ll bytes that are loaded in the page buffer must have the same page address. 0 6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required. In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously in the memory array. Before the completion of the internal programming cycle, the host is free perform other tasks such as fetching data from other locations in the system prepare write the next page. Software-protected ata Write The device provides a JEEC-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a series of three-byte program commands (with specific data a specific address) be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down. The W29EE011 is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-byte program command cycle. Once enabled, the software data protection will remain enabled unless the disable commands are issued. power transition will not reset the software Publication Release ate: February 19, Revision 15

4 data protection feature. To reset the device unprotected mode, a six-byte command sequence is required. See Table 3 for specific codes and Figure 10 for the timing diagram. Hardware ata Protection The integrity of the data sred in the W29EE011 is also hardware protected in the following ways: (1) Noise/Glitch Protection: pulse of less than 15 ns in duration will not initiate a write cycle. (2) V Power Up/own etection: The programming and read operation are inhibited when V is less than 3.8V. (3) Write Inhibit Mode: Forcing low, high, or high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. ata Polling (Q7)-Write Status etection The W29EE011 includes a data polling feature indicate the end of a programming cycle. When the W29EE011 is in the internal programming cycle, any attempt read Q7 of the last byte loaded during the page/byte-load cycle will receive the complement of the true data. Once the programming cycle is completed. Q7 will show the true data. Toggle Bit (Q6)-Write Status etection In addition data polling, the W29EE011 provides another method for determining the end of a program cycle. uring the internal programming cycle, any consecutive attempts read Q6 will produce alternating 0's and 1's. When the programming cycle is completed, this ggling between 0's and 1's will sp. The device is then ready for the next operation. 5-Volt-only Software Chip Erase The chip-erase mode can be initiated by a six-byte command sequence. fter the command loading cycles, the device enters the internal chip erase mode, which is aumatically timed and will be completed in 50 ms. The host system is not required provide any control or timing during this operation. Product Identification The product I operation outputs the manufacturer code and device code. Programming equipment aumatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-byte command sequence can be used access the product I. read from address 0000H outputs the manufacturer code (h). read from address 0001H outputs the device code (C1h). The product I operation can be terminated by a three-byte command sequence. In the hardware access mode, access the product I is activated by forcing and low, high, and raising 9 12 volts. Note: The hardware SI read function is not included in all parts; please refer Ordering Information for details

5 TBLE OF OPERTING MOES Operating Mode Selection Operating Range = 0 70 C (mbient Temperature), V = 5V ±10%, VSS = 0V, VHH = 12V MOE PINS RESS Q. Read VIL VIL VIH IN out Write VIL VIH VIL IN in Standby VIH X X X High Z Write Inhibit X VIL X X High Z/OUT X X VIH X High Z/OUT Output isable X VIH X X High Z 5-Volt Software Chip Erase VIL VIH VIL IN IN Product I VIL VIL VIH 0 = VIL; 1 16 = VIL; 9 = VHH VIL VIL VIH 0 = VIH; 1 16 = VIL; 9 = VHH Manufacturer Code (Hex) evice Code C1 (Hex) Publication Release ate: February 19, Revision 15

6 Command Codes for Software ata Protection BYTE SEQUENCE TO ENBLE PROTECTION TO ISBLE PROTECTION RESS T RESS T 0 Write 5555H H 5555H H 1 Write 2H 55H 2H 55H 2 Write 5555H 0H 5555H 80H 3 Write H H 4 Write - - 2H 55H 5 Write H 20H Software ata Protection cquisition Flow Software ata Protection Enable Flow Load data Software ata Protection isable Flow Load data Load data 55 address 2 Load data 55 address 2 (Optional page load operation) Load data 0 Sequentially load up 128 bytes of page data Load data 80 Load data Pause 10 ms Exit Load data 55 address 2 Load data 20 Pause 10 ms Notes for software program code: ata Format: Q7 Q0 (Hex) ddress Format: 14 0 (Hex) Exit - 6 -

7 Command Codes for Software Chip Erase BYTE SEQUENCE RESS T 0 Write 5555H H 1 Write 2H 55H 2 Write 5555H 80H 3 Write 5555H H 4 Write 2H 55H 5 Write 5555H 10H Software Chip Erase cquisition Flow Load data Load data 55 address 2 Load data 80 Load data Load data 55 address 2 Load data 10 Pause 50 ms Exit Notes for software chip erase: ata Format: Q7 Q0 (Hex) ddress Format: 14 0 (Hex) Publication Release ate: February 19, Revision 15

8 Command Codes for Product Identification BYTE SEQUENCE SOFTWRE PROUCT IENTIFICTION ENTRY SOFTWRE PROUCT IENTIFICTION EXIT RESS T RESS T 0 Write 5555H H 5555H H 1 Write 2H 55H 2H 55H 2 Write 5555H 80H 5555H F0H 3 Write 5555H H Write 2H 55H Write 5555H 60H - - Pause 10 µs Pause 10 µs Software Product Identification cquisition Flow Product Identification Entry(1) Product Identification Mode(2, 3) Product Identification Exit(1) Load data Load data 55 address 2 Load data Load data 80 Read address = 0 data = Load data 55 address 2 Load data Load data FO Load data 55 address 2 Read address = 1 data = C1 Pause 10 µsm Load data 60 Normal Mode (4) Pause 10 µ S Notes for software product identification: (1) ata format: Q7 Q0 (Hex); address format: 14 0 (Hex). (2) 1 16 = VIL; manufacture code is read for 0 = VIL; device code is read for 0 = VIH. (3) The device does not remain in identification mode if power down. (4) The device returns standard operation mode

9 C CHRCTERISTICS bsolute Maximum Ratings PRMETER RTING UNIT Power Supply Voltage GN Potential V Operating Temperature C Srage Temperature C.C. Voltage on ny Pin Ground Potential Except -0.5 V +1.0 V Transient Voltage (< 20 ns) on ny Pin Ground Potential -1.0 V +1.0 V Voltage on Pin Ground Potential V Note: Exposure conditions beyond those listed under bsolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (V = 5.0V ±10%, GN = 0V, T = 0 70 C) PRMETER SYM. TEST CONITIONS LIMITS UNIT Power Supply Current ICC = = VIL, = VIH, all I/Os open Standby V Current (TTL input) Standby V Current (CMOS input) ISB1 ISB2 ddress inputs = VIL/VIH, at f = 5 MHz = VIH, all I/Os open Other inputs = VIL/VIH = V -0.3V, all I/Os open Other inputs = V -0.3V/GN MIN. TYP. MX m m µ Input Leakage Current ILI VIN = GN V µ Output Leakage Current ILO VIN = GN V µ Input Low Voltage VIL V Input High Voltage VIH V +0.5 V Output Low Voltage VOL IOL = 2.1 m V Output High Voltage VOH IOH = -0.4 m V Power-up Timing PRMETER SYMBOL TYPICL UNIT Power-up Read Operation TPU.RE 100 µs Power-up Write Operation TPU.WRITE 5 ms Publication Release ate: February 19, Revision 15

10 CPCITNCE (V = 5.0V, T = 25 C, f = 1 MHz) PRMETER SYMBOL CONITIONS MX. UNIT I/O Pin Capacitance CI/O VI/O = 0V 12 pf Input Capacitance CIN VIN = 0V 6 pf C CHRCTERISTICS C Test Conditions (V = 5V ±10%) PRMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load CONITIONS 0V 3V < 5 ns 1.5V/1.5V 1 TTL Gate and CL = 30 pf for 70 ns and 100 pf for others. C Test Load and Waveforms +5V 1.8K ohm OUT 100 pf for 90/120/150 ns 30 pf for 70 ns (Including Jig and Scope) 1.3K ohm Input Output 3V 0V 1.5V 1.5V Test Point Test Point

11 Read Cycle Timing Parameters (V = 5.0V ±10 %, V = 5.0 ±5 % for 70 ns, GN = 0V, T = 0 70 C) PRMETER SYMBOL W29EE W29EE UNIT MIN. MX. MIN. MX. Read Cycle Time TRC ns Chip Enable ccess Time TCE ns ddress ccess Time T ns Output Enable ccess Time TOE ns Low ctive Output TCLZ ns Low ctive Output TOLZ ns High High-Z Output TCHZ ns High High-Z Output TOHZ ns Output Hold from ddress Change TOH ns Byte/Page-write Cycle Timing Parameters PRMETER SYMBOL MIN. TYP. MX. UNIT Write Cycle (Erase and Program) TWC ms ddress Setup Time TS ns ddress Hold Time TH ns and Setup Time TCS ns and Hold Time TCH ns High Setup Time TOES ns High Hold Time TOEH ns Pulse Width TCP ns Pulse Width TWP ns High Width TWPH ns ata Setup Time TS ns ata Hold Time TH ns Byte Load Cycle Time TBLC µs Byte Load Cycle Time-out TBLCO µs Note: ll C timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL. Publication Release ate: February 19, Revision 15

12 ata Polling and Toggle Bit Timing Parameters PRMETER SYM. W29EE W29EE UNIT MIN. MX. MIN. MX. ata Polling Output elay TOEP ns ata Polling Output elay TCEP ns Toggle Bit Output elay TOET ns Toggle Bit Output elay TCET ns TIMING WVEFORMS Read Cycle Timing iagram T RC ddress 16-0 TCE TOE VIH TOLZ TOHZ TCLZ TOH TCHZ Q7-0 High-Z ata Valid ata Valid High-Z T

13 Timing Waveforms, continued Controlled Write Cycle Timing iagram T BLCO T WC T S T H ddress 16-0 T CS T CH T OES TOEH T WP T WPH T S Q7-0 ata Valid T H Internal write starts Controlled Write Cycle Timing iagram TS TH TBLCO TWC ddress 16-0 TCP TCPH T OES TOEH Q7-0 High Z TS ata Valid TH Internal Write Starts Publication Release ate: February 19, Revision 15

14 Timing Waveforms, continued Page Write Cycle Timing iagram TWC ddress 16-0 Q7-0 TWP T WPH TBLC TBLCO Byte 0 Byte 1 Byte 2 Byte N-1 Byte N Internal Write Start #T Polling Timing iagram ddress 16-0 TCEP TOEH TOES Q7-0 T OEP X X X X TWC

15 Timing Waveforms, continued Toggle Bit Timing iagram ddress 16-0 TOEH TOES Q6 TWC Page Write Timing iagram Software ata Protection Mode Three-byte sequence for software data protection mode Byte/page load cycle starts TWC ddress Q TWP TBLC T BLCO TWPH SW0 SW1 SW2 Byte 0 Byte N-1 Byte N (last byte) Internal write starts Publication Release ate: February 19, Revision 15

16 Timing Waveforms, continued Reset Software ata Protection Timing iagram Six-byte sequence for resetting software data protection mode TWC ddress Q TWP TBLC TBLCO TWPH SW0 SW1 SW2 SW3 SW4 SW5 Internal programming starts 5 Volt-only Software Chip Erase Timing iagram Six-byte code for 5V-only software chip erase TWC ddress Q TWP TBLC TBLCO TWPH SW0 SW1 SW2 SW3 SW4 SW5 Internal programming starts

17 ORERING INFORMTION PRT NO. CCESS TIME (ns) POWER SUPPLY CURRENT MX. (m) STNBY V CURRENT MX. (m) PCKGE CYCLING HRWRE SI RE FUNCTION W29EE mil IP 1K Y W29EE mil IP 1K Y W29EE011T TSOP (8 x 20 mm) 1K Y W29EE011T TSOP (8 x 20 mm) 1K Y W29EE011Q STSOP (8 x 14 mm) 1K Y W29EE011Q STSOP (8 x 14 mm) 1K Y W29EE011P pin PLCC 1K Y W29EE011P pin PLCC 1K Y W29EE011-90B mil IP 10K Y W29EE011-15B mil IP 10K Y W29EE011T90B TSOP (8x20mm) 10K Y W29EE011T15B TSOP (8x20mm) 10K Y W29EE011Q90B STSOP (8x14mm) 10K Y W29EE011Q15B STSOP (8x14mm) 10K Y W29EE011P90B pin PLCC 10K Y W29EE011P15B pin PLCC 10K Y W29EE011-90N mil IP 1K N W29EE011-15N mil IP 1K N W29EE011P90N pin PLCC 1K N W29EE011P15N pin PLCC 1K N Notes: 1. Winbond reserves the right make changes its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. In Hardware SI Read column: Y = with SI read function; N = without SI read function. Publication Release ate: February 19, Revision 15

18 HOW TO RE THE TOP MRKING Example: The p marking of 32L-PLCC W29EE011P15N W29EE011P15N OBR 1 st line: winbond logo 2 nd line: the part number: W29EE011P15N 3 rd line: the lot number 4 th line: the tracking code: 149 O B R 149: Packages made in 01, week 49 O: ssembly house I: means SE, O means OSE,...etc. B: IC revision; means version, B means version B,...etc. R: Process code Publication Release ate: February 19, Revision 15

19 PCKGE IMENSIONS 32-pin P-IP E1 2 L S B e1 B1 1 Base Plane Seating Plane a E e c imension in inches imension in mm Symbol Min. Nom. Max. Min. Nom. Max B B1 c E E e L a e S Notes: 1.imensions Max. & S include mold flash or tie bar burrs. 2.imension E1 does not include interlead flash. 3.imensions & E1. include mold mismatch an are determined at the mold parting line. 4.imension B1 does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches 6.General appearance spec. should be based on final visual inspection spec. 32-pin PLCC 5 4 H E E Symbol 1 2 b 1 b c E e imension in Inches Min. Nom. Max. Min. Nom. Max imension in mm H G G G E H H E L y θ Notes: L c 1. imensions & E do not include interlead flash. 2. imension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection sepc. 2 θ Seating Plane e G E b b 1 1 y Publication Release ate: February 19, Revision 15

20 Package imensions, continued 32-pin TSOP (8 x 20 mm) H c Symbol 1 imension in Inches imension in mm Min. Nom. Max. Min. Nom. Max M e E b c (0.004) b E H e θ L L Y L L 1 Y θ Note: Controlling dimension: Millimeters 32-pin STSOP (8 x 14 mm) H b e c L E 1 2 c Y imension in Inches imension in mm Symbol Min. Nom. Max. Min. Nom. Max. 1 2 b c E H e L L1 Y θ L

21 VERSION HISTORY VERSION TE PGE ESCRIPTION 9 Feb dd pause 10 ms 7 dd pause 50 ms 8 Correct the time 10 ms 10 µs 1, 17 dd cycing 100 item 10 Jun , 10, 11, 12, 17 dd 70 ns bining 11 ug , 2, 17, 19 dd TSOP package 12 Jul , 17 Change endurance cycles as 1K/10K 1, 11, 12, 17 elete 70, 120 ns bining 1, 17, 18 elete SOP package 13 ec , 17 dd in Hardware SI Read Function note 14 Mar , 17, 18 dd in TSOP (8 x 14 mm) package 17 Correct Part No. in Ordering Information 15 Feb. 19, Modify V Power Up/own etection in Hardware ata Protection 18 dd HOW TO RE THE TOP MRKING 1, 17, 20 Rename TSOP (8 x 14 mm) as STSOP (8 X 14 mm) Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: FX: Taipei Office 9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: FX: Winbond Electronics Corporation merica 2727 North First Street, San Jose, C 95134, U.S.. TEL: FX: Winbond Electronics Corporation Japan 7F aini-ueno BLG, Shinyokohama Kohoku-ku, Yokohama, TEL: FX: Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan n W. Rd. Shanghai, China TEL: FX: Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: FX: Please note that all data and specifications are subject change without notice. ll the trade marks of products and companies mentioned in this data sheet belong their respective owners. Publication Release ate: February 19, Revision 15