256K 8 CMOS FLASH MEMORY

Transcription

1 GENERL DESCRIPTION 256K 8 CMOS FLSH MEMORY The W29C020C is a 2-megabit, 5-volt only CMOS flash memory organized as 256K 8 bits. The device can be written (erased and programmed) in-system with a standard 5V power supply. 2-volt VPP is not required. The unique cell architecture of the W29C020C results in fast write (erase/program) operations with extremely low current consumption compared other comparable 5-volt flash memory products. The device can also be written (erased and programmed) by using standard EPROM programmers. FETURES Single 5-volt write (erase and program) operations Fast page-write operations 28 bytes per page Page write (erase/program) cycle: 0 ms (max.) Effective byte-write (erase/program) cycle time: 39 µs Optional software-protected data write Fast chip-erase operation: 50 ms Two 8 KB boot blocks with lockout Whole chip cycling: 0K (typ.) Read access time: 70/90/20 ns Twenty-year data retention Software and hardware data protection Low power consumption ctive current: 25 m (typ.) Standby current: 20 µ (typ.) umatic write (erase/program) timing with internal VPP generation End of write (erase/program) detection Toggle bit Data polling Latched address and data ll inputs and outputs directly TTL compatible JEDEC standard byte-wide pinouts vailable packages: 32-pin 600 mil DIP, 32-pin TSOP, and 32-pin PLCC Publication Release Date: February 8, Revision 4

2 PIN CONFIGURTIONS BLOCK DIGRM NC pin DIP VDD VDD VSS CONTROL OUTPUT BUFFER DQ0.. DQ DQ7 DQ0 DQ DQ2 GND N C V # D W D E 7 30 DQ6 DQ5 DQ4 DQ DECODER 8K Byte Boot Block (Optional) CORE RRY 8K Byte Boot Block (Optional) VDD NC DQ pin PLCC D Q D Q2 G ND D Q3 D Q4 D Q5 D Q pin DQ7 DQ6 DQ5 DQ4 DQ3 9 TSOP 24 GND 0 23 DQ2 22 DQ 2 2 DQ DQ PIN DESCRIPTION SYMBOL PIN NME 0 7 ddress Inputs DQ0 DQ7 Data Inputs/Outputs Chip Enable Output Enable Write Enable VDD Power Supply GND Ground NC No Connection - 2 -

3 FUNCTIONL DESCRIPTION Read Mode The read operation of the W29C020C is controlled by and, both of which have be low for the host obtain data from the outputs. is used for device selection. When is high, the chip is de-selected and only standby power will be consumed. is the output control and is used gate data from the output pins. The data bus is in high impedance state when either or is high. Refer the read cycle timing waveforms for further details. Page Write Mode The W29C020C is written (erased/programmed) on a page basis. Every page contains 28 bytes of data. If a byte of data within a page is be changed, data for the entire page must be loaded in the device. ny byte that is not loaded will be erased "FF hex" during the write operation of the page. The write operation is initiated by forcing and low and high. The write procedure consists of two steps. Step is the byte-load cycle, in which the host writes the page buffer of the device. Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are simultaneously written in the memory array for non-volatile srage. During the byte-load cycle, the addresses are latched by the falling edge of either or, whichever occurs last. The data are latched by the rising edge of either or, whichever occurs first. If the host loads a second byte in the page buffer within a byte-load cycle time (TBLC) of 200 µs after the initial byte-load cycle, the W29C020C will stay in the page load cycle. dditional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal write (erase/program) cycle will start if no additional byte is loaded in the page buffer 7 7 specify the page address. ll bytes that are loaded in the page buffer must have the same page address. 0 6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required. In the internal write cycle, all data in the page buffers, i.e., 28 bytes of data, are written simultaneously in the memory array. Before the completion of the internal write cycle, the host is free perform other tasks such as fetching data from other locations in the system prepare write the next page. Software-protected Data Write The device provides a JEDEC-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a three-byte command sequence (with specific data a specific address) be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down. The W29C020C is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-byte command sequence cycle. Once enabled, the software data protection will remain enabled unless the disable commands are issued. power transition will not reset the software data protection feature. To reset the device unprotected mode, a six-byte command sequence is required. For information about specific codes, see the Command Codes for Software Data Protection in the Table of Operating Modes. For information about timing waveforms, see the timing diagrams below. Publication Release Date: February 8, Revision 4

4 Hardware Data Protection The integrity of the data sred in the W29C020C is also hardware protected in the following ways: () Noise/Glitch Protection: pulse of less than 5 ns in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The write and read operation are inhibited when VDD is less than 2.5V. (3) Write Inhibit Mode: Forcing low, high, or high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD reaches its sense level, the device will aumatically timeout for 5 ms before any write (erase/program) operation. Chip Erase Modes The entire device can be erased by using a six-byte software command code. See the Software Chip Erase Timing Diagram. Boot Block Operation There are two boot blocks (8K bytes each) in this device, which can be used sre boot code. One of them is located in the first 8K bytes and the other is located in the last 8K bytes of the memory. The first 8K or last 8K of the memory can be set as a boot block by using a seven-byte command sequence. See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed by the regular programming method. Once the boot block programming lockout feature is activated, the chip erase function will be disabled. In order detect whether the boot block feature is set on the two 8K blocks, users can perform a six-byte command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "00002 hex" (for the first 8K bytes) or "3FFF2 hex" (for the last 8K bytes). If the output data is "FF hex," the boot block programming lockout feature is activated; if the output data is "FE hex," the lockout feature is deactivated and the block can be programmed. To return normal operation, perform a three-byte command sequence exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection. Data Polling (DQ7)- Write Status Detection The W29C020C includes a data polling feature indicate the end of a write cycle. When the W29C020C is in the internal write cycle, any attempt read DQ7 from the last byte loaded during the page/byte-load cycle will receive the complement of the true data. Once the write cycle is completed. DQ7 will show the true data. See the Polling Timing Diagram

5 Toggle Bit (DQ6)- Write Status Detection In addition data polling, the W29C020C provides another method for determining the end of a write cycle. During the internal write cycle, any consecutive attempts read DQ6 will produce alternating 0's and 's. When the write cycle is completed, this ggling between 0's and 's will sp. The device is then ready for the next operation. See Toggle Bit Timing Diagram. Product Identification The product ID operation outputs the manufacturer code and device code. The programming equipment aumatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed through software or by hardware operation. In the software access mode, a six-byte command sequence can be used access the product ID. read from address "00000 hex" outputs the manufacturer code "D hex." read from address "0000 hex" outputs the device code "45 hex." The product ID operation can be terminated by a three-byte command sequence. In the hardware access mode, access the product ID is activated by forcing and low, high, and raising 9 2 volts. Note: The hardware SID read function is not included in all parts; please refer Ordering Information for details. TBLE OF OPERTING MODES Operating Mode Selection Operating Range: 0 70 C (mbient Temperature), VDD = 5V ±0 %, VSS = 0V, VHH = 2V MODE PINS DDRESS DQ. Read VIL VIL VIH IN Dout Write VIL VIH VIL IN Din Standby VIH X X X High Z Write Inhibit X VIL X X High Z/DOUT X X VIH X High Z/DOUT Output Disable X VIH X X High Z 5-Volt Software Chip Erase VIL VIH VIL IN DIN Product ID VIL VIL VIH 0 = VIL; 7 = VIL; 9 = VHH VIL VIL VIH 0 = VIH; 7 = VIL; 9 = VHH Manufacturer Code D (Hex) Device Code 45 (Hex) Publication Release Date: February 8, Revision 4

6 Command Codes for Software Data Protection BYTE SEQUENCE TO ENBLE PROTECTION TO DISBLE PROTECTION DDRESS DT DDRESS DT 0 Write 5555H H 5555H H Write 2H 55H 2H 55H 2 Write 5555H 0H 5555H 80H 3 Write H H 4 Write - - 2H 55H 5 Write H 20H Software Data Protection cquisition Flow Software Data Protection Enable Flow Software Data Protection Disable Flow Load data Load data address 2 address 2 Load data 0 Load data 80 (Optional page-load operation) Sequentially load up 28 bytes of page data Load data Pause 0 ms address 2 Exit Load data 20 Pause 0 ms Exit Notes for software program code: Data Format: DQ7 DQ0 (Hex) ddress Format: 4 0 (Hex) - 6 -

7 Command Codes for Software Chip Erase BYTE SEQUENCE DDRESS DT 0 Write 5555H H Write 2H 55H 2 Write 5555H 80H 3 Write 5555H H 4 Write 2H 55H 5 Write 5555H 0H Software Chip Erase cquisition Flow Load data address 2 Load data 80 Load data address 2 Load data 0 Pause 50 ms Exit Notes for software chip erase: Data Format: DQ7 DQ0 (Hex) ddress Format: 4 0 (Hex) Publication Release Date: February 8, Revision 4

8 Command Codes for Product Identification and Boot Block Lockout Detection BYTE SEQUENCE LTERNTE PRODUCT (7) IDENTIFICTION/BOOT BLOCK LOCKOUT DETECTION ENTRY SOFTWRE PRODUCT IDENTIFICTION/BOOT BLOCK LOCKOUT DETECTION ENTRY SOFTWRE PRODUCT IDENTIFICTION/BOOT BLOCK LOCKOUT DETECTION EXIT DDRESS DT DDRESS DT DDRESS DT 0 Write H H 5555H H Write H 55H 2H 55H 2 Write H 80H 5555H F0H 3 Write H H Write - - 2H 55H Write H 60H - - Pause 0 µs Pause 0 µs Pause 0 µs Software Product Identification and Boot Block Lockout Detection cquisition Flow Product Identification Entry () Load data Product Identification and Boot Block Lockout Detection Mode (3) Product Identification Exit () address 2 Read address = data = D (2) Load data Load data 80 Read address = 0000 data = 45 (2) address 2 Load data Read address = data = FF/FE (4) Load data F0 address 2 Read address = 3FFF2 data = FF/FE (5) Pause 0 µ S Load data 60 Normal Mode (6) Pause 0 µ S Notes for software product identification/boot block lockout detection: () Data Format: DQ7 DQ0 (Hex); ddress Format: 4 0 (Hex) (2) 6 = VIL; manufacture code is read for 0 = VIL; device code is read for 0 = VIH. (3) The device does not remain in identification and boot block (address 0002 Hex/3FFF2 Hex respond first 8K/last 8K) lockout detection mode if power down. (4), (5) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is inactivated and the block can be programmed. (6) The device returns standard operation mode. (7) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new designs, Winbond recommends that the 3 byte command code sequence be used

9 Command Codes for Boot Block Lockout Enable BYTE SEQUENCE BOOT BLOCK LOCKOUT FETURE SET ON FIRST 8K DDRESS BOOT BLOCK BOOT BLOCK LOCKOUT FETURE SET ON LST 8K DDRESS BOOT BLOCK DDRESS DT DDRESS DT 0 Write 5555H H 5555H H Write 2H 55H 2H 55H 2 Write 5555H 80H 5555H 80H 3 Write 5555H H 5555H H 4 Write 2H 55H 2H 55H 5 Write 5555H 40H 5555H 40H 6 Write 00000H 00H 3FFFFH FFH Pause 0 µs Pause 0 µs Boot Block Lockout Enable cquisition Flow Boot Block Lockout Feature Set on First 8K ddress Boot Block Load data Boot Block Lockout Feature Set on Last 8K ddress Boot Block Load data address 2 address 2 Load data 80 Load data 80 Load data Load data address 2 address 2 Load data 40 Load data 40 Load data 00 address Load data FF address 3FFFF Pause 0 ms Pause 0 ms Notes for boot block lockout enable:. Data Format: DQ7 DQ0 (Hex) 2. ddress Format: 4 0 (Hex) 3. If you have any questions about this commend sequence, please contact the local distribur or Winbond Electronics Corp. Publication Release Date: February 8, Revision 4

10 DC CHRCTERISTICS bsolute Maximum Ratings PRMETER RTING UNIT Power Supply Voltage VSS Potential V Operating Temperature C Srage Temperature C D.C. Voltage on ny Pin Ground Potential Except VDD +.0 V Transient Voltage (<20 ns) on ny Pin Ground Potential -.0 VDD +.0 V Voltage on 9 and OE Pin Ground Potential V Note: Exposure conditions beyond those listed under bsolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VDD = 5.0V ±0%, VSS = 0V, T = 0 70 C) PRMETER SYM. TEST CONDITIONS LIMITS UNIT Power Supply Current Standby VDD Current (TTL input) Standby VDD Current (CMOS input) ICC ISB = = VIL, = VIH, all DQs open ddress inputs = VIL/VIH, at f = 5 MHz = = VIL, = VIH, all DQs open ddress inputs = VIL/VIH, at f = 2 MHz = VIH, all DQs open Other inputs = VIL/VIH MIN. TYP. MX m m ISB2 = VDD -0.3V, all DQs open µ Input Leakage Current ILI VIN = VSS VDD µ Output Leakage Current ILO VIN = VSS VDD µ Input Low Voltage VIL V Input High Voltage VIH V Output Low Voltage VOL IOL = 2.0 m V Output High Voltage VOH IOH = -400 µ V Output High Voltage CMOS VOH2 IOH = -00 µ; VDD = 4.5V V - 0 -

11 Power-up Timing PRMETER SYMBOL TYPICL UNIT Power-up Read Operation TPU. RED 00 µs Power-up Write Operation TPU. WRITE 5 ms CPCITNCE (VDD = 5.0V, T = 25 C, f = MHz) PRMETER SYMBOL CONDITIONS MX. UNIT DQ Pin Capacitance CDQ VDQ = 0V 2 pf Input Pin Capacitance CIN VIN = 0V 6 pf C CHRCTERISTICS C Test Conditions (VDD = 5.0V ±0 % for 90 ns and 20 ns; VDD = 5.0V ±5 % for 70 ns) PRMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V 3V <5 ns.5v/.5v CONDITIONS TTL Gate and CL = 00 pf for 90/20 ns CL = 30 pf for 70 ns C Test Load and Waveform +5V.8KΩ D OUT 00 pf for 90/20 ns 30 pf for 70 ns (Including Jig and Scope).3KΩ Input Output 3V 0V Test Point.5V.5V Test Point Publication Release Date: February 8, Revision 4

12 C Characteristics, continued Read Cycle Timing Parameters (VDD = 5.0V ±0 % for 90 ns and 20 ns; VDD = 5.0V ±5 % for 70 ns, VSS = 0V, T = 0 70 C) PRMETER SYM. W29C020C-70 W29C020C-90 W29C020C-2 UNIT MIN. MX. MIN. MX. MIN. MX. Read Cycle Time TRC ns Chip Enable ccess Time TCE ns ddress ccess Time T ns Output Enable ccess Time TOE ns High High-Z Output TCHZ ns High High-Z Output TOHZ ns Output Hold from ddress change TOH ns Byte/Page-write Cycle Timing Parameters PRMETER SYMBOL MIN. TYP. MX. UNIT Write Cycle (erase and program) TWC ms ddress Setup Time TS ns ddress Hold Time TH ns and Setup Time TCS ns and Hold Time TCH ns High Setup Time TOES ns High Hold Time TOEH ns Pulse Width TCP ns Pulse Width TWP ns High Width TWPH ns Data Setup Time TDS ns Data Hold Time TDH ns Byte Load Cycle Time TBLC µs Note: ll C timing signals observe the following guideline for determining setup and hold times: Reference level is VIH for high-level signal and VIL for low-level signal

13 C Characteristics, continued #DT Polling Characteristics () PRMETER SYMBOL MIN. TYP. MX. UNIT Data Hold Time TDH ns Hold Time TOEH ns Output Delay (2) TOE ns Write Recovery Time TWR ns Notes: () These parameters are characterized and not 00% tested. (2) See TOE spec in.c. Read Cycle Timing Parameters. Toggle Bit Characteristics () PRMETER SYMBOL MIN. TYP. MX. UNIT Data Hold Time TDH ns Hold Time TOEH ns Output Delay (2) TOE ns High Pulse TOEHP ns Write Recovery Time TWR ns Notes: () These parameters are characterized and not 00% tested. (2) See TOE spec in.c. Read Cycle Timing Parameters. TIMING WVEFORMS Read Cycle Timing Diagram T RC ddress 7-0 TCE TOE VIH T OHZ DQ7-0 High-Z Data Valid TOH Data Valid T CHZ High-Z T Publication Release Date: February 8, Revision 4

14 Timing Waveforms, continued Controlled Write Cycle Timing Diagram T S T H T WC ddress 7-0 T CS T CH T OES T OEH T WP T WPH T DS DQ7-0 Data Valid T DH Internal write starts Controlled Write Cycle Timing Diagram TS TH TWC ddress 7-0 TCP TWPH TOES TOEH TCS TCH DQ7-0 High Z TDS Data Valid TDH Internal Write Starts - 4 -

15 Timing Waveforms, continued Page Write Cycle Timing Diagram TWC ddress 7-0 DQ7-0 TWP T WPH TBLC Byte 0 Byte Byte 2 Byte N- Internal Write Start Byte N #DT Polling Timing Diagram ddress 5-0 TOEH DQ7 TDH TOE HIGH-Z TWR Publication Release Date: February 8, Revision 4

16 Timing Waveforms, continued Toggle Bit Timing Diagram TOEH DQ6 TDH TOE HIGH-Z TWR Page Write Timing Diagram Software Data Protection Mode Three-byte sequence for software data protection mode Byte/page load cycle starts TWC ddress DQ TWP TWPH TBLC SW0 SW SW2 Word 0 Word N- Word N (last word) Internal write starts - 6 -

17 Timing Waveforms, continued Reset Software Data Protection Timing Diagram Six-byte sequence for resetting software data protection mode TWC ddress DQ T WP T WPH TBLC SW0 SW SW2 SW3 SW4 SW5 Internal programming starts Software Chip Erase Timing Diagram Six-byte code for 5V-only software chip erase TWC ddress DQ TWP TWPH T BLC SW0 SW SW2 SW3 SW4 SW5 Internal erasing starts Publication Release Date: February 8, Revision 4

18 ORDERING INFORMTION PRT NO. CCESS TIME (ns) POWER SUPPLY CURRENT MX. (m) STNDBY VDD CURRENT MX. (m) PCKGE CYCLING HRDWRE SID RED FUNCTION W29C020C-70B mil DIP 0K Y W29C020C-90B mil DIP 0K Y W29C020C-2B mil DIP 0K Y W29C020CT70B Type one TSOP 0K Y W29C020CT90B Type one TSOP 0K Y W29C020CT2B Type one TSOP 0K Y W29C020CP70B pin PLCC 0K Y W29C020CP90B pin PLCC 0K Y W29C020CP2B pin PLCC 0K Y W29C020C90BN mil DIP 0K N W29C020C2BN mil DIP 0K N W29C020CT90N Type one TSOP 0K N W29C020CT2N Type one TSOP 0K N W29C020CP90N pin PLCC 0K N W29C020CP2N pin PLCC 0K N Notes:. Winbond reserves the right make changes its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. In Hardware SID Read column: Y = with SID read function; N = without SID read function

19 HOW TO RED THE TOP MRKING Example: The p marking of 32-pin TSOP W29C020CT70B W29C020CT70B OBS st line: Winbond logo 2 nd line: the part number: W29C020CT70B 3 rd line: the lot number 4 th line: the tracking code: 49 O B S 49: Packages made in 0, week 49 O: ssembly house ID: means SE, O means OSE,...etc. B: IC revision; means version, B means version B,...etc. S: Process code Publication Release Date: February 8, Revision 4

20 PCKGE DIMENSIONS 32-pin P-DIP E 2 L D S B e B Base Plane Seating Plane a E e c Symbol B 2 B c D E E e L Dimension in inches Dimension in mm Min. Nom. Max. Min. Nom. Max a e S Notes:.Dimensions D Max. & S include mold flash or tie bar burrs. 2.Dimension E does not include interlead flash. 3.Dimensions D & E. include mold mismatch an are determined at the mold parting line. 4.Dimension B does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches. 6.General appearance spec. should be based on final visual inspection spec. 32-pin TSOP H D D c Symbol Dimension in Inches Dimension in mm Min. Nom. Max. Min. Nom. Max M e E b c (0.004) D b E H D e θ L L 2 Y L L Y θ Note: Controlling dimension: Millimeters

21 Package Dimensions, continued 32-pin PLCC H E E D H D G D Symbol 2 b b c D E e Dimension in Inches Min. Nom. Max. Min. Nom. Max Dimension in mm G D c G E H D H E L y θ L Notes: θ Seating Plane e G E b b 2 y. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc. Publication Release Date: February 8, Revision 4

22 VERSION HISTORY VERSION DTE PGE DESCRIPTION May Initial Issued 2 pr Change Byte Load Cycle Time from 50 µs 200 µs 3 Dec , 8 dd in Hardware SID Read function note 4 Feb. 8, dd in one more Test Condition in Power Supply Current (Icc): f = 2 MHz 4 Modify VDD Power Up/Down Detection description 9 dd HOW TO RED THE TOP MRKING Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: FX: Taipei Office 9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 4, Taiwan, R.O.C. TEL: FX: Winbond Electronics Corporation merica 2727 North First Street, San Jose, C 9534, U.S.. TEL: FX: Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, Shinyokohama Kohoku-ku, Yokohama, TEL: FX: Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan n W. Rd. Shanghai, China TEL: FX: Winbond Electronics (H.K.) Ltd. Unit 9-5, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: FX: Please note that all data and specifications are subject change without notice. ll the trade marks of products and companies mentioned in this data sheet belong their respective owners