256K 8 CMOS FLASH MEMORY

Transcription

1 256K 8 CMOS FLSH MEMORY GENERL ESCRIPTION The W49F002U is a 2-megabit, 5-volt only CMOS flash memory organized as 256K 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. 2-volt VPP is not required. The unique cell architecture of the W49F002U results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. FETURES Single 5-volt operations: 5-volt Read 5-volt Erase 5-volt Program Fast Program operation: Byte-by-Byte programming: 35 µs (typ.) Fast Erase operation: 00 ms (typ.) Fast Read access time: 70/90/20 ns Endurance: 0K cycles (typ.) Ten-year data retention Hardware data protection One 6K byte Boot Block with Lockout protection Two 8K byte Parameter Blocks Two Main Memory Blocks (96K, 28K) Bytes Low power consumption ctive current: 25 m (typ.) Standby current: 20 µ (typ.) utomatic program and erase timing with internal VPP generation End of program or erase detection Toggle bit ata polling Latched address and data TTL compatible I/O JEEC standard byte-wide pinouts vailable packages: 32-pin IP, 32-pin STSOP (8 mm 4 mm), 32-pin TSOP (8 mm 20 mm) and 32-pin-PLCC Publication Release ate: February 2, Revision 6

2 - 2 - PIN CONFIGURTIONS Q0 Q Q2 Vss V #WE Q7 Q6 Q5 Q4 Q pin IP #RESET Q Q Q 2 V s s Q 3 Q 4 Q 5 Q Q7 2 6 V # W E 5 32-pin PLCC 7 # R ES E T 32-pin TSOP V #WE #RESET Q0 Q Q2 Vss 0 Q7 Q6 Q5 Q4 Q BLOCK IGRM CONTROL OUTPUT BUFFER ECOER #WE Q0 V VSS Q7 3FFFF FFFF FFF FFF C000 3BFFF PRMETER BLOCK2 8K BYTES BOOT BLOCK 6K BYTES PRMETER BLOCK 8K BYTES #RESET MIN MEMORY BLOCK2 28K BYTES MIN MEMORY BLOCK 96K BYTES PIN ESCRIPTION SYMBOL PIN NME #RESET Reset 0 7 ddress Inputs Q0 Q7 ata Inputs/Outputs Chip Enable Output Enable #WE Write Enable V Power Supply VSS Ground

3 FUNCTIONL ESCRIPTION evice Operation Read Mode The read operation of the W49F002U is controlled by and, both of which have to be low for the host to obtain data from the outputs. is used for device selection. When is high, the chip is de-selected and only standby power will be consumed. is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either or is high. Refer to the timing waveforms for details. Write Mode evice erase and program are accomplished via the command register. The content of the register serves as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written to bring #WE to logic low state when is at logic low state and is at logic high state. ddresses are latched on the falling edge of #WE or, whichever happens later; while data is latched on the rising edge of #WE or, whichever happens first. Standard microprocessor write timings are used. Refer to C Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Standby Mode There are two ways to implement the standby mode on the W49F002U device, both using the pin. CMOS standby mode is achieved with the input held at V -0.3V. Under this condition the current is typically reduced to less than 00 µ. TTL standby mode is achieved with the pin held at VIH. Under this condition the current is typically reduced to less than 3 m. In the standby mode the outputs are in the high impedance state, independent of the input. Output isable Mode With the input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state. uto-select Mode The auto-select mode allows the reading of a binary code from the device and will identify its manufacturer and type. This mode is intended to be used by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VI (.5V to 2.5V) on address pin 9. Two identifier bytes may then be sequenced from the device outputs by toggling address 0 from VIL to VIH. ll addresses are don t cares except 0 and (see "uto-select Codes"). Note: The hardware SI read function is not included in all parts; please refer to Ordering Information for details. Publication Release ate: February 2, Revision 6

4 The manufacturer and device codes may also be read via the command register; i.e., the W49F002U is erased or programmed in a system without access to high voltage on the 9 pin. The command sequence is illustrated in "uto-select Codes". Byte 0 (0 = VIL) represents the manufacturer s code (Winbond = h) and byte (0 = VIH) the device identifier code (W49F002U = 0Bh,). ll identifiers for manufacturer and device will exhibit odd parity with Q7 defined as the parity bit. In order to read the proper device codes when executing the uto-select, must be VIL. Reset Mode: Hardware Reset The #RESET pin provides a hardware method of resetting the device to reading array data. When the system drives the #RESET pin low for at least a period of trp, the device immediately terminates any operation in progress, tri-states all data output pins, and ignores all read/write attempts for the duration of the #RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the #RESET pulse. When #RESET is held at VIL, the device enters the TTL standby mode; if #RESET is held at Vss, the device enters the CMOS standby mode. The #RESET pin may be tied to the system reset circuitry. system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. ata Protection The W49F002U is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. uring power up the device automatically resets the internal state machine in the Read mode. lso, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from V power-up and power-down transitions or system noise. Low V Inhibit To avoid initiation of a write cycle during V power-up and power-down, the W49F002U locks out when V < 2.5V. The write and read operations are inhibited when V is less than 2.5V typical. The W49F002U ignores all write and read operations until V > 2.5V. The user must ensure that the control pins are in the correct logic state when V > 2.5V to prevent unintentional writes. Write Pulse "Glitch" Protection Noise pulses of less than 0 ns (typical) on,, or #WE will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of = VIL, = VIH, or #WE = VIH. To initiate a write cycle and #WE must be a logical zero while is a logical one. Power-up Write and Read Inhibit Power-up of the device with #WE = = VIL and = VIH will not accept commands on the rising edge of #WE. The internal state machine is automatically reset to the read mode on power-up

5 Command efinitions evice operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. "Command efinitions" defines the valid register command sequences. Moreover, both Reset/Read commands are functionally equivalent, resetting the device to the read mode. Read Command The device will automatically power-up in the read state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. The device will automatically returns to read state after completing an Embedded Program or Embedded Erase algorithm. Refer to the C Read Characteristics and Waveforms for the specific timing parameters. uto-select Command Flash memories are intended for use in applications where the local CPU can alter memory contents. s such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising 9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally a desirable system design practice. The device contains an auto-select command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the auto-select command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of h. read cycle from address XX0H returns the device code (W49F002U = 0Bh). Byte Program Command The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two "unlock" write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded program algorithm. ddresses are latched on the falling edge of or #WE, whichever happens later and the data is latched on the rising edge of or #WE, whichever happens first. The rising edge of or #WE (whichever happens first) begins programming using the Embedded Program lgorithm. Upon executing the algorithm, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on Q7 (also used as ata Polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time for ata Polling operations. ata Polling must be performed at the memory location which is being programmed. Publication Release ate: February 2, Revision 6

6 ny commands written to the chip during the Embedded Program lgorithm will be ignored. If a hardware reset occurs during the programming operation, the data at that particular location will be corrupted. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "". Only erase operations can convert "0"s to ""s. Refer to the Embedded Programming lgorithm using typical command strings and bus operations. Chip Erase Command Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase lgorithm command sequence the device will automatically erase and verify the entire memory for an all one data pattern. The erase is performed sequentially on each sector at the same time (see "Feature"). The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and terminates when the data on Q7 is "" at which time the device returns to read the mode. Refer to the Embedded Erase lgorithm using typical command strings and bus operations. Sector Erase Command Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the sector erase command. The sector address (any address location within the desired sector) is latched on the falling edge of #WE, while the command (30H) is latched on the rising edge of #WE. Sector erase does not require the user to program the device prior to erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the rising edge of the #WE pulse for the last sector erase command pulse and terminates when the data on Q7, ata Polling, is "." Refer to the Embedded Erase lgorithm using typical command strings and bus operations. Write Operation Status Q7: ata Polling The W49F002U device features ata Polling as a method to indicate to the host that the embedded algorithms are in progress or completed. uring the Embedded Program lgorithm, an attempt to read the device will produce the complement of the data last written to Q7. Upon completion of the Embedded Program lgorithm, an attempt to read the device will produce the true data last written to Q7. uring the Embedded Erase lgorithm, an attempt to read the device will produce a "0" at the Q7 output. Upon completion of the Embedded Erase lgorithm, an attempt to read the device will produce a "" at the Q7 output. The flowchart for ata Polling (Q7) is shown in "ata Polling lgorithm"

7 For chip erase, the ata Polling is valid after the rising edge of the sixth pulse in the six #WE write pulse sequence. For sector erase, the ata Polling is valid after the last rising edge of the sector erase #WE pulse. Just prior to the completion of Embedded lgorithm operations Q7 may change asynchronously while the output enable () is asserted low. This means that the device is driving status information on Q7 at one instant of time and then that byte s valid data at the next instant of time. epending on when the system samples the Q7 output, it may read the status or valid data. Even if the device has completed the Embedded lgorithm operations and Q7 has a valid data, the data outputs on Q0 Q6 may be still invalid. The valid data on Q0 Q7 will be read on the successive read attempts. The ata Polling feature is only active during the Embedded Programming lgorithm, Embedded Erase lgorithm, or sector erase time-out (see "Command efinitions"). See " #T Polling uring Embedded lgorithm Timing iagrams". Q6: Toggle Bit The W49F002U also features the "Toggle Bit" as a method to indicate to the host system that the embedded algorithms are in progress or completed. uring an Embedded Program or Erase lgorithm cycle, successive attempts to read ( toggling) data from the device at any address will result in Q6 toggling between one and zero. Once the Embedded Program or Erase lgorithm cycle is completed, Q6 will stop toggling and valid data will be read on the next successive attempt. uring programming, the Toggle Bit is valid after the rising edge of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of the sixth #WE pulse in the six write pulse sequence. For Sector erase, the Toggle Bit is valid after the last rising edge of the sector erase #WE pulse. The Toggle Bit is active during the sector erase time-out. TBLE OF OPERTING MOES evice Bus Operations MOE PIN #WE #RESET 0-7 Q0 - Q7 Read VIL VIL VIH VIH in out Write VIL VIH VIL VIH in in Write Inhibit VIH X VIL X X High Z/OUT VIH X X VIH X High Z/OUT Standby VIH X X VIH X High Z Output isable VIL VIH VIH VIH X High Z Reset X X X VIL X High Z Publication Release ate: February 2, Revision 6

8 uto-select Codes (High Voltage Method) ESCRIPTION #WE OTHER 9 0 Q7 TO Q0 Manufacturer I: Winbond VIL VIL VIH X VI VIL VIL h evice I: W49F002U (Top Boot Block) Notes: VIL VIL VIH X VI VIL VIH 0Bh. S = Sector ddress, X = on t Care. Sector Protection Verification: 0h (protected); 00h (unprotected). 2. The hardware SI read function is not included in all parts; please refer to Ordering Information for details. Hardware Sequence Flags Standard Mode OPERTION Q7 Q6 (Note) Embedded Program lgorithm #Q7 Toggle Embedded Erase lgorithm 0 Toggle Note: Q7 require a valid address when reading status information. Refer to the appropriate subsection for further details. Command efinition () COMMN No. of th Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle ESCRIPTION Cycles ddr. ata ddr. ata ddr. ata ddr. ata ddr. ata ddr. ata Read IN OUT Chip Erase Sector Erase S (3) 30 Byte Program IN IN Boot Block Lockout Product I Entry Product I Exit (2) F0 Product I Exit (2) XXXX F0 Notes:. ddress Format: 4 0 (Hex); ata Format: Q7 Q0 (Hex) 2. Either one of the two Product I Exit commands can be used. 3. S means: Sector ddress If S is within 3C000 to 3FFFF (Boot Block address range), and the Boot Block programming lockout feature is activated, nothing will happen and the device will go back to read mode after 00nS. If the Boot Block programming lockout feature is not activated, this command will erase Boot Block. If S is within 3000 to 3BFFF (Parameter Block address range), this command will erase PB. If S is within to 39FFF (Parameter Block2 address range), this command will erase PB2. If S is within to 37FFF (Main Memory Block address range), this command will erase MMB. If S is within to FFFF (Main Memory Block2 address range), this command will erase MMB

9 Embedded Programming lgorithm Start Write Program Command Sequence (see below) #ata Polling/ Toggle bit Pause TBP Increment ddress No Last ddress? Yes Programming Completed Program Command Sequence (ddress/command): 5555H/H 2H/55H 5555H/0H Program ddress/program ata Publication Release ate: February 2, Revision 6

10 Embedded Erase lgorithm Start Write Erase Command Sequence (see below) #ata Polling or Toggle Bit Successfully Completed Pause T EC /TSEC Erasure Completed Chip Erase Command Sequence (ddress/command): 5555H/H Individual Sector Erase Command Sequence (ddress/command): 5555H/H 2H/55H 2H/55H 5555H/80H 5555H/80H 5555H/H 5555H/H 2H/55H 2H/55H 5555H/0H Sector ddress/30h - 0 -

11 Embedded #ata Polling lgorithm Start Read Byte (Q0 - Q7) ddress = V V = Byte address for programming = ny of the sector addresses within the sector being erased during sector erase operation = Valid address equals any sector group address during chip erase No Q7 = ata? Pass Yes Embedded Toggle Bit lgorithm Start Read Byte (Q0 - Q7) ddress = on't Care Yes Q6 = Toggle? Pass No Publication Release ate: February 2, Revision 6

12 Software Product Identification and Boot Block Lockout etection cquisition Flow Product Identification Entry () Load data to address 5555 Product Identification and Boot Block Lockout etection Mode (3) Product Identification Exit(6) Load data to address 5555 Load data 55 to address 2 Read address = 0000 data = 00 (2) Load data 55 to address 2 Load data 90 to address 5555 Read address = 000 data = 00E (2) Load data F0 to address 5555 Pause 0 µ S Read address = 0002 data in Q0 =/0 (4) Pause 0 µ S Normal Mode (5) Notes for software product identification/boot block lockout detection: () ata Format: Q5 Q8 (on't Care), Q7 Q0 (Hex); ddress Format: 4 0 (Hex) (2) 6 = VIL; manufacture code is read for 0 = VIL; device code is read for 0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the output data in Q0 =, the boot block programming lockout feature is activated; if the output data in Q0 = 0, the lockout feature is inactivated and the block can be programmed. (5) The device returns to standard operation mode. (6) Optional -write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection

13 Boot Block Lockout Enable cquisition Flow Boot Block Lockout Feature Set Flow Load data to address 5555 Load data 55 to address 2 Load data 80 to address 5555 Load data to address 5555 Load data 55 to address 2 Load data 40 to address 5555 Pause 200 ms Exit Publication Release ate: February 2, Revision 6

14 C CHRCTERISTICS bsolute Maximum Ratings PRMETER RTING UNIT Power Supply Voltage to Vss Potential -0.5 to +7.0 V Operating Temperature 0 to +70 C Storage Temperature -65 to +50 C.C. Voltage on ny Pin to Ground Potential Except to V +.0 V Transient Voltage (<20 ns) on ny Pin to Ground Potential -.0 to V +.0 V Voltage on 9 Pin to Ground Potential -0.5 to 2.5 V Note: Exposure to conditions beyond those listed under bsolute Maximum Ratings may adversely affect the life and reliability of the device. C Operating Characteristics (V = 5.0V ±0%, VSS = 0V, T = 0 to 70 C) PRMETER SYM. TEST CONITIONS LIMITS UNIT Power Supply Current Standby V Current (TTL input) Standby V Current (CMOS input) Input Leakage Current Output Leakage Current ICC ISB ISB2 = = VIL, #WE = VIH, all Qs open ddress inputs = VIL/VIH, at f = 5 MHz = VIH, all Qs open Other inputs = VIL/VIH = V -0.3V, all Qs open Other inputs = V -0.3V/ Vss MIN. TYP. MX m m µ ILI VIN = Vss to V µ ILO VOUT = Vss to V µ Input Low Voltage VIL V Input High Voltage VIH V +0.5 V Output Low Voltage VOL IOL = 2. m V Output High Voltage VOH IOH = -0.4 m V - 4 -

15 Power-up Timing PRMETER SYMBOL TYPICL UNIT Power-up to Read Operation TPU. RE 00 µs Power-up to Write Operation TPU. WRITE 5 ms CPCITNCE (V = 5.0V, T = 25 C, f = MHz) PRMETER SYMBOL CONITIONS MX. UNIT I/O Pin Capacitance CI/O VI/O = 0V 2 pf Input Capacitance CIN VIN = 0V 6 pf C CHRCTERISTICS C Test Conditions PRMETER CONITIONS Input Pulse Levels 0V to 3V Input Rise/Fall Time <5 ns Input/Output Timing Level.5V /.5V Output Load TTL Gate and CL = 30pF (for 70 ns/ 90 ns), 00 pf (for 20 ns) C Test Load and Waveform +5V.8KΩ OUT 30 pf for 70nS / 90nS 00 pf for 20nS (Including Jig and Scope).3KΩ Input Output 3V 0V Test Point.5V.5V Test Point Publication Release ate: February 2, Revision 6

16 C Characteristics, continued Read Cycle Timing Parameters (V = 5.0V ±0%, V = 0V, T = 0 to 70 C) PRMETER SYM. W49F002U-70 W49F002U-90 W49F002U-20 UNIT MIN. MX. MIN. MX. MIN. MX. Read Cycle Time TRC ns Chip Enable ccess Time TCE ns ddress ccess Time T ns Output Enable ccess Time TOE ns Low to ctive Output TCLZ ns Low to ctive Output TOLZ ns High to High-Z Output TCHZ ns High to High-Z Output TOHZ ns Output Hold from ddress Change TOH ns Write Cycle Timing Parameters PRMETER SYMBOL MIN. TYP. MX. UNIT ddress Setup Time TS ns ddress Hold Time TH ns #WE and Setup Time TCS ns #WE and Hold Time TCH ns High Setup Time TOES ns High Hold Time TOEH ns Pulse Width TCP ns #WE Pulse Width TWP ns #WE High Width TWPH ns ata Setup Time TS ns ata Hold Time TH ns Byte Programming Time TBP µs Erase Cycle Time TEC S Note: ll C timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL

17 C Characteristics, continued ata Polling and Toggle Bit Timing Parameters PRMETER SYM. W49F002U-70 W49F002U-90 W49F002U-20 UNIT MIN. MX. MIN. MX. MIN. MX. to ata Polling Output elay TOEP ns to ata Polling Output elay TCEP ns to Toggle Bit Output elay TOET ns to Toggle Bit Output elay TCET ns Reset Timing Parameters PRMETER SYMBOL MIN. TYP. MX. UNIT V stable to Reset ctive TPRST - - ms Reset Pulse Width TRSTP ns Reset ctive to Output Float TRSTF ns Reset Inactive to Input ctive TRST - - µs Publication Release ate: February 2, Revision 6

18 TIMING WVEFORMS Read Cycle Timing iagram TRC ddress 7-0 TCE TOE #WE VIH TOLZ TOHZ TCLZ TOH TCHZ Q7-0 High-Z ata Valid ata Valid High-Z T #WE Controlled Command Write Cycle Timing iagram T S T H ddress 7-0 T CS T CH T OES T OEH #WE T WP T WPH T S Q7-0 ata Valid T H - 8 -

19 Timing Waveforms, continued Controlled Command Write Cycle Timing iagram TS TH ddress 7-0 T CP TCPH T OES TOEH #WE Q7-0 High Z TS ata Valid TH Program Cycle Timing iagram Byte Program Cycle ddress ddress Q ata-in #WE TWP TWPH TBP Byte 0 Byte Byte 2 Byte 3 Internal Write Start Publication Release ate: February 2, Revision 6

20 Timing Waveforms, continued #T Polling Timing iagram ddress 7-0 n n n n #WE T CEP T OEH T OES Q7 T OEP X X X X T EC T BP or Toggle Bit Timing iagram ddress 7-0 #WE TOEH TOES Q6 TBP ortec

21 Timing Waveforms, continued Boot Block Lockout Enable Timing iagram Six byte code for Boot Block Lockout Feature Enable ddress Q #WE TWP TWPH TEC SB0 SB SB2 SB3 SB4 SB5 Chip Erase Timing iagram Six-byte code for 5V-only software chip erase ddress Q #WE TWP TEC TWPH SB0 SB SB2 SB3 SB4 SB5 Internal Erase starts Publication Release ate: February 2, Revision 6

22 Timing Waveforms, continued Sector Erase Timing iagram Six-byte code for 5V-only software Main Memory Erase ddress S Q #WE TWP TWPH TEC SB0 SB SB2 SB3 SB4 SB5 Internal Erase starts S = Sector ddress Reset Timing iagram V T PRST #RESET T RSTP TRSTF T RST ddress 7-0 Q

23 ORERING INFORMTION PRT NO. CCESS TIME (ns) POWER SUPPLY CURRENT MX. (m) STNBY V CURRENT MX. (m) PCKGE CYCLE HRWRE SI RE FUNCTION W49F002U-70B (CMOS) 32-pin IP 0K Y W49F002U-90B (CMOS) 32-pin IP 0K Y W49F002U-2B (CMOS) 32-pin IP 0K Y W49F002UT70B (CMOS) 32-pin TSOP (8 mm 20 mm) 0K Y W49F002UT90B (CMOS) 32-pin TSOP (8 mm 20 mm) 0K Y W49F002UT2B (CMOS) 32-pin TSOP (8 mm 20 mm) 0K Y W49F002UP70B (CMOS) 32-pin PLCC 0K Y W49F002UP90B (CMOS) 32-pin PLCC 0K Y W49F002UP2B (CMOS) 32-pin PLCC 0K Y W49F002UQ70B (CMOS) 32-pin STSOP (8 mm 4 mm) 0K Y W49F002UQ90B (CMOS) 32-pin STSOP (8 mm 4 mm) 0K Y W49F002UQ2B (CMOS) 32-pin STSOP (8 mm 4 mm) 0K Y W49F002U70BN (CMOS) 32-pin IP 0K N W49F002U90BN (CMOS) 32-pin IP 0K N W49F002U2BN (CMOS) 32-pin IP 0K N W49F002UT70N (CMOS) 32-pin TSOP (8 mm 20 mm) 0K N W49F002UT90N (CMOS) 32-pin TSOP (8 mm 20 mm) 0K N W49F002UT2N (CMOS) 32-pin TSOP (8 mm 20 mm) 0K N W49F002UP70N (CMOS) 32-pin PLCC 0K N W49F002UP90N (CMOS) 32-pin PLCC 0K N W49F002UP2N (CMOS) 32-pin PLCC 0K N W49F002UQ70N (CMOS) 32-pin STSOP (8 mm 4 mm) 0K N W49F002UQ90N (CMOS) 32-pin STSOP (8 mm 4 mm) 0K N W49F002UQ2N (CMOS) 32-pin STSOP (8 mm 4 mm) 0K N Notes:. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. Winbond offers Top Boot Block device, if any of Bottom Boot Block devices is required, please contact Winbond FEs. 4. In Hardware SI read function column: Y = with SI read function; N = without SI read function. Publication Release ate: February 2, Revision 6

24 HOW TO RE THE TOP MRKING Example: The top marking of 48-pin TSOP W49F002UT70B W49F002UT70B OBS st line: winbond logo 2 nd line: the part number: W49F002UT70B 3 rd line: the lot number 4 th line: the tracking code: 49 O B S 49: Packages made in 0, wee k 49 O: ssembly house I: means SE, O means OSE,...etc. B: IC revision; means version, B means version B,...etc. S: Process code

25 PCKGE IMENSIONS 32-pin P-IP E 2 L S B e B Base Plane Seating Plane a E e c imension in inches imension in mm Symbol Min. Nom. Max. Min. Nom. Max B B c E E e L a e S Notes:.imensions Max. & S include mold flash or tie bar burrs. 2.imension E does not include interlead flash. 3.imensions & E. include mold mismatch an are determined at the mold parting line. 4.imension B does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches 6.General appearance spec. should be based on final visual inspection spec. 32-pin PLCC 5 4 H E E Symbol 2 b b c E e imension in Inches Min. Nom. Max. Min. Nom. Max imension in mm H G G G E H H E L y θ Notes: L 4 20 c. imensions & E do not include interlead flash. 2. imension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection sepc. 2 θ Seating Plane e G E b b y Publication Release ate: February 2, Revision 6

26 Package imensions, continued 32-pin STSOP (8 x 4 mm) H b e c L E 2 c Y imension in Inches imension in mm Symbol Min. Nom. Max. Min. Nom. Max. 2 b c E H e L L Y θ L 32-pin TSOP (8 x 20 mm) H c Symbol imension in Inches imension in mm Min. Nom. Max. Min. Nom. Max M e E b c (0.004) b E H e θ L L 2 Y L L Y θ Note: Controlling dimension: Millimeters

27 VERSION HISTORY VERSION TE PGE ESCRIPTION Nov Renamed from W49F002/B/U/N 2 pr. 2000, 3 5, 20 dd the 20 ns bin 4 Change Tbp(typ.) from 0 µs to 35 µs Change Tec (max.) from Sec to 0.2 Sec 3 ec ll Modify some function description 3, 9, 25 dd in Hardware SI read note 4 Jan. 200 ll Typo correction, 25, 27 dd in 32-pin TSOP (8 mm x 4 mm) package 5 ug. 3, 200 6,22 dd Reset Timing Parameters and iagram 6 Feb. 2, 2002, 25, 28 Rename STOP (8 x 4 mm) as STSOP (8 x 4 mm) 4 Modify Low V Write Inhibit description 3 dd in Software Product Identification and Boot Block Lockout etection cquisition Flow 4 dd in Boot Block Lockout Enable cquisition Flow 24 dd HOW TO RE THE TOP MRKING Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: FX: Taipei Office 9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 4, Taiwan, R.O.C. TEL: FX: Winbond Electronics Corporation merica 2727 North First Street, San Jose, C 9534, U.S.. TEL: FX: Winbond Electronics Corporation Japan 7F aini-ueno BLG, Shinyokohama Kohoku-ku, Yokohama, TEL: FX: Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan n W. Rd. Shanghai, China TEL: FX: Winbond Electronics (H.K.) Ltd. Unit 9-5, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: FX: Please note that all data and specifications are subject to change without notice. ll the trade marks of products and companies mentioned in this data sheet belong to their respective owners. Publication Release ate: February 2, Revision 6