MMP16: Didactic Micro-Programmed Micro-Processor
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1 MMP16: Didactic Micro-Programmed Micro-Processor José Luis López Presa Elio Pérez Calle Department of Telematic Engineering and Architecture, Universidad Politécnica de Madrid, Spain (UPM) EU Science and Technology Fellowship Programme, University of Science and Technology of China (USTC) 3rd International Conference on Computer Research and Development Shanghai, March 2011
2 Overview MMP16 stands for 16-bit Micro-programmed Micro-Processor. MMP16 is a didactic micro-programmed micro-processor for those students that, having studied the basics of digital electronics, need to understand the principles of computer organization prior to study advanced computer architecture. MMP16 has been designed as a bridge between the study and use of digital electronic components and a full implementation of a digital microprocessor. These concepts have been identified as a teaching need by authors such as Hennessy, Patterson, Tomek and Tanenbaum. Besides the theoretical approach, MMP16 may be used as a learning tool, allowing the students to develop and test their own microprograms. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
3 Motivation Tanembaum defines the following levels, present on most modern computers (Tanenbaum, SCO, 2006). J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
4 Motivation Tanembaum s model L2. Conventional machine level L1. Microprogramming level L0. Data logic level Knowledge areas Computer architecture Principles of comp. organization Digital electronics J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
5 Main Design Features The main idea behind MMP16 is to build a bridge between Level-0 and Level-2 of Tanenbaum s model using simple circuits that any student with basic knowledge of digital electronics is able to understad. As a didactic tool, efficiency and performance are not the main design goals. By learning MMP16, students understand that they would be able to build a CPU following Von Neumann s model. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
6 Main Design Features Why micro-programmed (and not wired)? MMP16 is a didactic tool. MMP16 is micro-programmed, and not wired beacuse of the simplicity of the former over the latter. Allows the students to design automata corresponding to the instructions sequencing without having to struggle with the hardware, so they don t need to modify the software simulator. Segmentation is easier to understand (extending segmentation to the data processing unit, as done in RISC superescalar machines, is easier after having understood this example). J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
7 Main Design Features Simplified architecture and reduced instruction set, but not RISC. Set of bit registers, including SP and PC. 16-bit ALU able to perform arithmetic operations such as addition, substraction and logic ones such as AND, OR, XOR and NOT. 16-bit address and data bus. 64K 16-bit memory. Segmented control unit. No I/O devices. Design is focused on CPU. External signals are: r (memory read), w (memory write), ready (used by memory to inform the processor that the required operation has concluded), reset (resets CPU) and int (interrupts, may be activated in the software simulator.) J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
8 General Description data_bus mmp16 addr_bus r w ready memory int Φ1 Φ2 reset J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
9 Organization A 16-bit Internal Data Bus (IDB) connects all the functional areas. Every register and bus are 16-bit ones, and a byte word cannot be addressed, in order to achieve the highest simplicity. Its control memory has 32-bit 256 words. 8 bits microaddresses are needed to address the control memory, each word contaning a microinstruction. The main goal of MMP16 is to consolidate the student s knowledge about CPU innner organization and instruction sequencing. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
10 I/O Devices For the sake of simplicity, there are not I/O devices, but they could be easily added. Even though there are not separated I/O and memory maps, this is not a architectural limitation, used from the early PDP-11 to x86 architecture. Nevertheless, interrupts are already present in MMP16. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
11 System layout Control Unit reset ready condition microprogram int selection r external control 5 IR w signals microorders 16 IDB Data Bus interface Address bus Interface Register array Operands selection 5 16 Data Bus 16 Address Bus SP ALU 4 flags PC J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
12 Register array There are 16 general purpose registers. R14 is the stack pointer (SP) and R15 is the program counter (PC). Registers may be addressed in two cases: a instruction referring a register is executed, or the control unit selects SP or PC for an operation to update PC or to handle the stack. To increment and decrement PC and SP faster, an incrementer and a decrementer are available, to avoid the use of the ALU for these operations. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
13 Register array op1r op2r op3r pc_sp selr MUX 2 4 Φ2 SEL CLK R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 SP PC 16 MUX opr R2IDB IDB J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
14 Register array seir is a microinstruction field that selects how the register array is addressed: one of the two fields of the instruction register (IR), op1r (0), op2r (1) or op3r (2); or control unit directly selecting PC or SP. In this case, the control signal pc sp allows selecting between PC and SP. opr is a microcommand used to select the operation to perform with the selected register: nothing (0), increment it (1), decrement it (2) or load it from IDB (3). Register array has a selection input (SEL) that selects the register whose data is obtained and that will be updated. Finally, the control signal R2IDB lets the content of the selected register to go IDB through a tristate. RaIDB is obtained decoding aidb command from the microinstruction. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
15 Operand selection The first ALU operand (op1) can be loaded from IDB using the control signal ld op1. Sel op2 selects if the second operand (op2) is loaded from IDB or is loaded with the 8-bit immediate field of IR (sign extended) Ld op2 allows to load this second operand with the selected value. ALU s first operand will always be op1, but the second one may be modified to perform several special operations, such as subtractions using two s complement representation for negative numbers. It is possible to force op2 to have all its bits to one or to zero. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
16 Operand selection IDB 16 imm<7> imm<7:0> sel_op2 0 1 MUX ld_op1 Φ2 op1 ld_op2 Φ2 op2 op2_0 16 inv_op2 16 op1 op2 J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
17 Arithmetic Logic Unit (ALU) The 16-bit ALU is able to perform arithmetic operations such as addition, substraction (using two s complement ) and logic ones such as AND, OR, XOR and NOT. The ALU includes an adder and three sets of logical gates. The NOT operation has only one operand (op1) and it is performed through a XOR operation with as a second operand. The operation to be performed in the ALU (addition, substraction, AND, OR, XOR, NOT) can be selected using op ALU. The signal ALUaIDB, obtained decoding aidb microcommand, allows the result of the ALU to go to IDB through the appropriate tristate. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
18 Arithmetic Logic Unit (ALU) op1 op2 inv_cin V C n-2 C n-1 op1 Σ op2 Cin sel_cin C C op1 op2 op1 op2 op1 op2 sel_carry op_alu MUX Z N 16 IDB ALU2IDB J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
19 Arithmetic Logic Unit (ALU) When performing an addition or substration, initial carry has to be set using the sel Cin and inv Cin signals. Initial carry is 0 for a addition. Substration is performed adding op1 and op2 s two s complement (negated op2 and initial carry 1). To perform a 32-bit addition, both 16 LSB are added with initial carry 0 and then both 16 MSB using as initial carry the one generated in the LSB addition. To perform a 32-bit substraction, both 16 LSB are substracted using borrow as carry flag, and then both 16 MSB using as initial carry the negation of the one generated in the LSB substraction. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
20 Flags Flags indicate four conditions that can occur as a result of a operation in the ALU, as well as one bit indicating if interruptions are enabled or disabled. The four possible conditions are: Z: 1 if result is zero and 0 otherwise. N: 1 if result is negative (MSB equals 1), and 0 otherwise. V: 1 if overflow in a two s complement operation is detected. C: Cn-1 en case of addition (carry) and NOT Cn-1 in case of substraction (borrow). To indicate interruptions: I: 1 if interruptions are enabled, 0 otherwise. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
21 Flags Sel f allows to select if flags are loaded from the data bus, if they are updated from flags generated in the ALU, if interruptions are enabled or not. Mod f allows to update the flags register. The flagsaidb signal activates the tristate that allows the flags to go to IDB (i.e. go to stack). This signal is obtained decoding aidb. Flags register is 5-bit, so they will be the five LSB from IDB. 16 ld_ir Φ2 IR IDB 2IDB 2 DEC R2IDB flags2idb data2idb ALU2IDB J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
22 Flags 0, Z, V, N, C 1, Z, V, N, C I, Z, V, N, C sel_f MUX mod_f Φ2 flags I, Z, V,N, C 5 flags2idb IDB 16 J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
23 Interfaces with external buses Ld data allows to load the data register from IDB. When the w signal is activated, data from this register will go to the data bus so they can be written on memory. Data register keeps the data stable in the data bus during all the memory write cycle. Data can go from the external data bus to IDB through a tristate control by dataaidb generated from aidb. Ld addr enables loading the addr register from IDB. When the signales r or w are activated, its content will go to the address bus. Addr register keeps the address stable durgin both memory read or write cycles. IR can be loaded from IDB activating the ld IR signal. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
24 Instruction Register and aidb decoding (I) 16 data_bus w ld_data Φ2 16 ld_addr Φ2 r data addr data2idb IDB 16 w addr_bus J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
25 Instruction Register and aidb decoding (II) 16 ld_ir Φ2 IR IDB 2IDB 2 DEC R2IDB flags2idb data2idb ALU2IDB J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
26 Pipelining The control unit of MMP16 is segmented: Segment I is devoted to the search of the next microinstruction to execute. Segment II is devoted to the execution of the current microinstruction. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
27 Pipelining J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
28 Pipelining This kind of pipeline is one of the most frequent ones. It tries to parallelize two slow processes: the search of a new microinstruction in the memory and the execution of the microinstruction, and therefore accelerate the machine. The basic feature of this kind of organization is that the election of next microinstruction in the case of a conditional jump inside the microprogram is performed depending on the status of the machine at the end of the previous microinstruction, and not on the status of the machine at the end of the current cycle. maddress i+1 = f (minstruction i, status i 1 ) J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
29 Condition selection The status register stores the conditions in function of which is it possible to modify the ordinary program execution sequence. Some of these conditions are: Those indicated in the cond field of IR, based on values of the flag registry. The ready condition used for wait cycles until memory operations are completed. When interruptions are allowed (flag I), activating the interruption request (int) external signal. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
30 Condition selection N V I int Z Z C C N Z V ready sel_cond inv_cond Φ1 status register MUX cond MUX cond<3:1> cond<0> J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
31 Microprogram control mpc is the microprogram counter, contains the control memory address where the microinstruction that is being executing is contained and that would be stored in the microinstruction register (mi). The selection of the next microinstruction (where am I going) is made depending on the selected condition (cond ) and sel sig, that indicate where am I going if selected conditions occurs. In case this doesn t occur, I will go to the next microinstruction, following mpc (mpc+1). Due to the segmentation of the control unit, jump condition that is evaluated in a given status is the one generated in the previous one. MMP16 has a external reset signal that allows to intialize the machine. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
32 Microprogram control jump address computed from the content of IR save_mpc Φ1 Φ1 save mpc +1 d_alt sel_next cond MUX reset 0 1 MUX 8 microprogram memory (mrom) 32 Φ1 microinstruction register (mi) microorders J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
33 Microprogram control The save registry may be used to save any frequently used microaddress. It is loaded with the save mpc signal. D alt is a field of the microinstruction that allows to jump to any address of the control memory. As it overlaps with the microcommands that control ALU, if d alt is used, ALU cannot be used in this status. It is possible to jump to any address depending on the instruction contained in the IR. The microprogram implementing this instruction should be loaded in this address. This is a basic possibility in any instruction interpreter. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
34 Decoding of the instruction The hardware of MMP16 determines the memory address where the microprogram the executes the corresponding instruction is located, what is commonly referred to as the decoding of the instruction. MMP16 operation codes may be 4, 8, 12 or 16-bit. 16-bit operation codes have their 12 MSB (cop1, cop2, cop3) to bit operation codes have their 8 MSB (cop1, cop2) to 1. 8-bit operation codes have their 4 MSB (cop1) to 1. This allows 15 4-bit, 15 8-bit, bit and bit codes, up to 61 in total. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
35 Jump address depending on IR opc3 opc MUX opc3 opc MUX opc2 opc MUX opc1 8 f(ir) 2 0 J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
36 External signals generation J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
37 Fetch phase flux diagram NO int? SI PC addr, incpc, r DecSP, flags data data_bus IR SP addr, decsp, w NO ready? SI NO ready? f(ir)? 0 I SI PC data SI microprograma correspondiente NO ready? data_bus PC SP addr, w 0 addr, r SI ready? NO J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
38 Software simulator MMP16 software simulator (available in both GNU/Linux and Windows platforms) is one of the project s advantages. The simulator helps to understand instruction sequencing and the data path management, and helps the students to comprehend the inner operation of the processor they have already studied in theory. The simulator is the last step in the process of connecting the student s knowledge about digital electronics (Tanenbaum s Level-0) to the principles of computer organization and the basics of computer architecture (Tanenbaum Level-2). J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
39 Software simulator A typical session would include the following steps: Load the microprograms into the control memory. Load the program into main memory. Send a reset pulse. Run the processor some clock cycles. Test the content of the desired registers or memory words. J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
40 Conclusions As a didactic project, MMP16 covers the gap between digital electronics and computer architecture offering a complete set of tools: The design of a modern computer. The practical application of the principles of computer organization including advanced concepts such as pipelining. The possibility to code and test microprograms. A GNU/Linux and Windows-based software simulator as the last step of the process. Full information and downloads in: J.L. López, E. Pérez (UPM-USTC) MMP16 Didactic Microprocessor ICCRD Shanghai / 40
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