ECE U530 Digital Hardware Synthesis. What is the course about?

Transcription

1 ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser Sept 6, 2006 Lecture 1: Overview Organization What is an ASIC? Why FPGAs? Hardware Description Languages and VHDL ECE U530 F06 What is the course about? ECEU530 follows closely the material learned in ECEU322 (ECE1382): Digital Logic Design Digital Logic Design using VHDL Synthesize VHDL to FPGAs VHDL: Combinational Logic Design Sequential Logic Design System Design Writing Testbenches Synthesis tools Targetting FPGAs 2

2 Web: Blackboard Getting Help Copies of lectures, assignments, handouts, solutions Clarifications to assignments Questions answered Personal help Professor: Office Hours 10:30 to 11:30 am Tues and Wed or by appointment 3 Required Textbook: Reading Ashenden, The Designer's Guide to VHDL 2 nd Edition, Morgan Kaufmann, 2001 Recommended Text: Mano and Kime, Logic and Computer Design Fundamentals, 3 rd Edition Prentice Hall,

3 Programming Assignments All assignments are expected to represent individual work! Programming Assignments will be submitted electronically. Tools: Xilinx ISE version 6.2i Modelsim 5.7e Programming assignments will be done on WinCOE systems. Computers are available on the second floor of Snell Engineering. You must have a COE account for this class: Go to then click on HELP! then click on Account Information For New Users 5 Programming Assignments I have the tools (at work) on a PC. Can I work there, then upload the tools? Yes, but... It is your responsibility to make sure: 1. You are using the same version of the tools: Version 6.2i of the Xilinx ISE tools Version 5.7e of Modelsim 2. Your programs run under the WinCOE tools i.e. no problems with formatting, etc. You can download evaluation versions from Xilinx and Modelsim. These are newer versions of the tools. YOU MUST MAKE SURE YOUR ANSWERS WORK on the WinCOE system!! 6

4 Midterm Exam (30%) Policies: Grading Midterm Exam in class Tuesday, November 1 Homework and Programming Assignments (30%) Frequent homeworks (1 or 2 per week) most will be programming assigments using Xilinx and Modelsim Final Project (30%) December 13 at 1:00pm 7 Our Design Flow 8

5 How to learn VHDL The course textbook: Ashenden, The Designer's Guide to VHDL 2 nd Edition, Morgan Kaufmann, 2001 Many VHDL web pages VHDL on line tutorial: The Green Mountain VHDL tutorial: VHDL tutorial: learn by example The VHDL mini reference: 9 Why VHDL? VHDL more dominant in FPGA design than Verilog VHDL tools more advanced than tools for other languages: SystemC has no synthesis tool for FPGAs HandelC does not have a good simulation environment... We may look at SystemC later in the semester 10

6 An Integrated Circuit Wafer (holding hundreds of dice) Pin-grid array (PGA) package Silicon die or chip Measurement of chip size, gate count: the number of logic gates A logic gate = a two-input NAND gate 11 CMOS is based on a MOSFET Metal Polysilicon Oxide (S i O 2 ) W n + n + L p-well The smallest feature size, λ=l/2 (unit: micron or µm) e.g., λ=0.25 µm in a 0.5 micron process 12

7 ASIC (Application-Specific IC) Not all ICs are ASICs CPU, microprocessor TTL ICs (74-series) ROMs, DRAMs, and SRAMs IC = Integrated Circuit Some ICs are ASICs Toy chips (e.g. ICs for e-pets, talking dolls, and so on) DSP processors? MPEG II decoder, xdsl ICs ICs for interfacing between memory and microprocessor Types of ASICs Full-custom ASICs Semicustom ASICs: cell-based, gate-array-based Programmable ASICs: PLD, FPGA 13 Taxonomy of Digital Hardware 14

8 Full-Custom ASICs Some (or all) logic cells are customized All mask layers are customized Design for: High speed Low power Small size Applications: Analog IC Mixed analog/digital ASIC Memory cells FPGA cells 15 Advantages Full-Custom ASICs (2) Optimal performance area speed power Disadvantages Time/effort to design Time to market Cost Cannot change once fabricated 16

9 Cell-based ASICs (CBICs) Use predesigned logic cells (standard cells) in combination with larger cells (megacells) Standard cells AND/OR gates, NAND/NOR gates,.. Multiplexers, adders,... Flip-flops, latches, registers,... Fixed blocks Flexible block Mega cells (full-custom blocks, system-level macros, fixed blocks, cores, functional standard blocks, or IP) Microcontrollers, mp, MPEG decoder RAM, ROM All mask layers are customized Custom blocks can be embedded 17 Advantages Cell-Based ASICs (2) Faster to design the Custom Logic Can optimize some logic cells: choose dfferent library components for different drive requirements Disadvantages Time/effort to design Less than full-custom, worse than other design styles Time to market Cost still need a full mask set Cannot change once fabricated 18

10 Gate-Array Based ASICs Gate array (or prediffused array) Transistors are predifined on the silicon wafer Base array: the predifined pattern of transistors Base cell: the smalles element that is replicated to make the base array Masked gate array (MGA) Only the top few layers of metal are defined by the designer using custom masks The designer chooses from a gate-array library of predesigned logic cells (macros) Types of MGA ASICs Channeled gate arrays Channelless gate arrays Structured gate arrays 19 Advantages Gate-Array Based ASICs (2) Faster to design the Semi-custom Logic Lower cost only need top few layers of mask Lower fabrication time Disadvantages Cannot optimize for performance Time to market faster than CBICs, slower than FPGAs Cannot change once fabricated 20

11 Programmable Logic Not all programmable logic is FIELD programmable PLAs and PALs implement AND-OR logic Useful for implementing combinational logic PLA : Programmable Logic Array programmable AND, programmable OR Planes PAL: Programmable Array Logic programmable AND, fixed OR plane PLAs and PALs similar architectures Programmable by adding connections May be mask programmable or field programmable depending on design, chip 21 PAL (Programmable Array Logic)! "# $ = x + 1x2 x3 x1x2 x3 = x + 1 x2 x1x2 x3 22

12 FPL: Field Programmable Logic (FPL) Logic for computing functions Interconnect I/O CPLD Complex, Programmable Logic Device Computations based on PAL FPGA Field Programmable Gate Array Computations based on LUT: Look up table 23 Field Programmable Logic (2) Advantages Low cost Very low fabrication time Fast time to market Volatile: Can change once fabricated Disadvantages Cannot optimize for performance Wasted area to allow reprogrammability Volatile: lose design on power down 24

13 FPGA FPGAs do not contain AND or OR planes Three elements: Logic blocks I/O blocks Interconnection wires and switches 25 Lookup Table (LUT) x 1 x 2 f %& %& % %& %& % 26

14 SRAM-controlled Switches ( #' ( #' #' ( ( 27 ASIC Cell Libraries FPGA: a library of logic cells that make up bigger components MGAs and CBICs: ASIC vendor: using an ASIC-vendor library Enter and simulate the design thru a set of design tools approved by the vendor Library vendor: purchasing a cell library Use a phantom library whose cells are empty boxes but contain enough information for layout The vendor will fills in the empty boxes after receiving the netlist In-house design: developing a cell library in-house Qualified cell library: the cell library that meets the foundry specifications An ASIC foundry only provides manufacturing without design help 28

15 Cell Information A physical layout The designer may not actually see the layout A behavioral model A high-level model to shorten the simulation time A Verilog/VHDL model A detailed timing model Determined by performing a simulation of each cell including the parasitic elements The simulation models are derived from measurements on special chips (process control monitors, PCMs, or drop-ins) A test strategy A circuit schematic A netlist description for the layout versus schematic (LVS) check A cell icon An icon for schematic entry A wire-load model A model for estimating the parasitic capacitance of wires before routing A routing model A model tells where it can and cannot place wires over the cell, as well as the location and types of the connections 29 Losses due to delayed market entry Revenues ($) Market rise D On-time Delayed W Peak revenue Peak revenue from delayed entry Market fall 2W Simplified revenue model Product life = 2W, peak at W Time of market entry defines a triangle, representing market penetration Triangle area equals revenue Loss The difference between the on-time and delayed triangle areas On-time entry Delayed entry Time 30

16 Exploding: Cost of IC Mask Set Process (µ) Single Mask cost ($K) # of Masks Mask Set cost ($K) , Quote from Cost of an ASIC Spending on masks can pay off, Sematech finds By David Lammers EE Times, July 30, 2003 A mask set for 130-nm logic devices costs $750,000, on average. Saying that "we think we have a decent handle on mask cost projections," Trybula said that Sematech expects the price tag to rise to $1.6 million for 90-nm technology and $3 million for a 65-nm mask set. "The price goes up very significantly" after that, Trybula said. 32

17 Why FPGAs? FPGAs allow you to take advantage of latest technology FPGAs are high volume, custom designs FPGA manufacturers pay the high cost of a mask set sell same chip to thousands of customers Disadvantages Designs mapped on FPGAs are slower, larger, dissipate more power than designs implemented on ASICs Disadvantages amount to sticking with one or two previous generations of ASIC chip Advantages No NRE (Non-recurring Engineering cost) for an FPGA Fast time to market FPGA CAD tools are cheaper than ASIC CAD tools 33 ASIC Market FPGAs vs. ASICs per month 34

18 When to use FPGAs? Replace components on a board easier to integrate a single chip Replace an ASIC ASICs getting expensive to fabricate FPGAs getting denser Accelerate algorithms that run in software for embedded systems but PCs are getting faster all the time... factor of 2 speed increase in PC parallels a factor of 4 speedup in an FPGA: 2xclock + 2x area Goals: High performance design Fast design turn around 35 Classification of Digital Hardware Chips can be: Gate Array or Custom Programmable Logic can be: Mask Programmable (Program once, in the foundary) Field Programmable (Program anywhere) Field Programmable Logic can be: Program once Reprogrammable Reprogrammable Logic can be: Reprogrammable out of the circuit (EEPROM based) Reprogrammable in the circuit Reconfigurable Logic is Reprogrammable in the circuit 36

19 SRAM-based FPGAs Programmed by loading configuration memory cells from an external source Memory cells are distributed among the logic they control Configuration memory is written once for each application high speed read/write is NOT important stability and density of RAM IS important 37 FPGA Density Gates 10M 1M Approx. 65% growth per year Virtex Virtex-II 100K XC K XC3000 XC2000 1K

20 Xilinx FPGA Architecture CLB Configurable Logic Block IOB Input/Output Block PSM Programmable Switch Matrix PIP Programmable Interconnect Point 39 There are no Logic Gates on an FPGA Logic Gates are implemented via a LUT: Look up table 40

21 FPGA CAD FLOW Synthesis Technology Mapping Placement Routing Timing Analysis Bitstream generation and download Simulation, simulation, simulation Trends in Digital Hardware Improvements in device technology Smaller circuits Higher performance More devices per chip Higher degree of integration More complex systems Lower cost of computation Higher reliability 42

22 Hardware Design Challenges Use most recent technology To be competitive in performance Reduce design cost To be competitive in price Speed up design time Time to market is critical 43 Modern FPGAs Take advantage of the latest technology.13 micron,.09 micron... High cost is amortized over many customers Millions of transistors per FPGA Millions of gate equivalents per FPGA One gate equivalent = 1 2-input NAND gate (4 transistors) Difficult to measure in FPGA due to LUT technology Clock speeds greater than 100 MHz Integrate larger logic blocks: Memories Multipliers Processor cores 44

23 FPGAs require ASIC design styles Density and performance of best FPGAs rival ASICs of 1 or 2 years ago Same design issues: controlling complexity ability to simulate 45 Moore s law The most important trend in microelectronics Predicted in 1965 by Intel co-founder Gordon Moore IC transistor capacity has doubled roughly every 18 months for the past several decades Logic transistors per chip (in millions) Note: logarithmic scale 10,000 1,

24 Moore s Law: CPUs and Memory 47 Graphical illustration of Moore s law ,000 transistors 150,000,000 transistors Leading edge chip in 1981 Leading edge chip in 2002 Something that doubles frequently grows more quickly than most people realize! A 2002 chip can hold about 15, chips inside itself 48

25 Facts about the Transistor In 2002, transistors are produced. This is about 100 times more transistors than there are ants in the world! More transistors are produced per year in DRAMs only than grains of rice. One grain of rice can buy 100 s of transistors! 49 The Importance of CAD Tools #"'() ) *+, &'(),!"!"#!"!!!$!!% & &# &! 50 [ Keutzer] Source: SEMATECH

26 Evolution of the EDA Industry -* ) 2/ 3* 2 *) ) /0* [ Keutzer] IC Design Steps (cont.) 71* * 8* / / 9 * 37/ * 37/ 52 Figs. [ Sherwani]

27 IC Design Steps (cont.) 71* * / * :- /?1* * / 8* / / ;<09= /> 0>/>09> (<09> >0 > />09 >/ 53 Design Synthesis The manner in which we convert our concept of desired system functionality into an implementation Compilation/ Synthesis Libraries/ IP Test/ Verification Compilation/Synthesis: Automates exploration and insertion of implementation details for lower level. System specification System synthesis Hw/Sw/ OS Model simulat./ checkers Libraries/IP: Incorporates predesigned implementation from lower abstraction level into higher level. Behavioral specification RT specification Behavior synthesis RT synthesis Cores RT components Hw-Sw cosimulators HDL simulators Test/Verification: Ensures correct functionality at each level, thus reducing costly iterations between levels. Logic specification Logic synthesis Gates/ Cells Gate simulators To final implementation 54

28 Design Methodology Specification Design domains - abstraction level Top-down vs. Bottom-up design Schematic based vs. HDL based Getting it right Simulation and verification Design libraries 55 Specification A specification of what to construct is the first major step. Compromise between what is wanted and what can be made Requires experience Requirements must be considered at many levels System, sub-system, Board Specifications can be verified by system simulations 56

29 Design domains Gajski chart Structural Processor, memory ALU, registers Cell Device, gate Transistor Program State machine Module Boolean equation Transfer function Behavioral Masks Gate Functional unit Macro IC Geometric 57 Design Domains (2) Behavioral: Abstract function Structural: Interconnection of parts Geometric: physical objects with sizes and position 58

30 Abstraction levels and synthesis Architectural level Logic level Circuit level Layout level Behavioral level For I=0 to I=15 Sum = Sum + array[i] 0 State Architecture synthesis Logic synthesis Circuit synthesis Layout synthesis Structural level Memory Control + (register level) Clk (Library) Ideal synthesis system 59 Top - down design Choice of algorithm Definition of functional modules Definition of design hierarchy Split up in small boxes - split up in small boxes - split up in small boxes Define required units ( adders, state machine, etc.) Floor-planning Map into chosen technology (synthesis, schematic, bitstream) Behavioral simulation tools 60

31 Bottom - up Build basic units in technology Build generic modules of use Put modules together Hope that you arrived at some reasonable architecture Gate level simulation tools Old fashioned design methodology a la discrete logic Comment by one of the main designers of a Pentium processor The design was made in a typical top - down, bottom - up, inside - out design methodology 61 Schematic based Symbol of module defines interface Schematic of module defines function Top - down: Make first symbol and then schematic Bottom - up: Make first Schematic and then symbol Basic gate Logic module Symbol Long and tedious Schematic 62

32 Synthesis based Define modules and their behavior in a hardware description language (also used for simulation) Use synthesis tools to generate netlist clk) begin if (set) coarse <= #(test.ff_delay) offset; else if (coarse == count_roll_over) coarse <= #(test.ff_delay) 0; else coarse <= #(test.ff_delay) coarse + 1; end 63 Getting it right - Simulation Simulate the design at all levels: behavioral level netlist level netlist with timing information Behavioral simulation at system/module level (Verilog, VHDL) All functions must be simulated and verified Worst case data must be used if exhaustive simulation impossible Use programming approach to verify large set of functions (not looking at waveform displays) 64

33 Architectural Synthesis Hardware Synthesis Determine the interconnection of large building blocks Logic Synthesis Determine the interconnection of logic gates Geometric level Synthesis (Place and Route) Determine positions and connections 65 Circuit Optimization Performance (speed) Delay and cycle time Latency Throughput -- for pipelined applications Area Power 66

34 Our Design Flow 67 How to Describe FPGA Designs Use CAD Tools CAD Tools translate your design into an FPGA architecture Two types of design entry: Schematic capture This is what you used in ECE U322 (ECE 1382) Hardware Description Language This is what this class is about CAD tools translate both types of descriptions to FPGA hardware 68

35 Technology trends The Need for HDLs 1 billion transistor chip running at 20 GHz in 2007 Need for Hardware Description Languages Systems become more complex Design at the gate and flip-flop level becomes very tedious and time consuming HDLs allow Design and debugging at a higher level before conversion to the gate and flip-flop level Tools for synthesis do the conversion VHDL, Verilog are the most popular VHDL VHSIC Hardware Description Language 69 HDLs vs. Programming Languages Procedural programming languages provide algorithms, or the how of implenting a design for computation for data manipulation typically independent of the hardware it is running on Hardware description languages describe a system Interfaces are important May want to describe in different ways behavior structure May want to specify specific physical properties 70

36 HDLs vs. Programming Languages (2) Procedural programming languages: sequential execution structural information less important exact timing information is NOT important Hardware description languages: Parallel execution I/O ports, building blocks Exact timing information IS important 71 Why Describe a System? Design Specification Unambiguous definition of components and interfaces Documentation Design Simulation verify performance prior to/after design implementation functional correctness timing Design Synthesis Automatic generation of a hardware design Component and Design Reuse Technology Independence 72

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