Solutions - Homework 4 (Due date: November 9:30 am) Presentation and clarity are very important!

Transcription

1 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 Solutions - Homework 4 (Due date: November 9:3 am) Presentation and clarity are very important! PROBLM ( PTS) Digital Stopwatch: The architecture of a digital stopwatch is provided. We require counters with an output ''. This output is asserted (for one clock cycle) when the counter reaches its maximum count. Counter (.s). It counts up to, asserting '' when the count reaches. For an input clock frequency of MH, '' is asserted every. s. BCD counter: It counts up to 9, asserting '' when the count reaches 9. Modulo-6 counter: It counts up to 5, asserting '' when the count reaches 5. NXYS3 implementation details: Only one 7-segment display can be used at a time we serialie the four BCD outputs. In order for each digit to appear bright and continuously illuminated, we illuminate each digit for only ms every 4 ms. This is taken care of feeding the output of the counter to.s to the enable input of the FSM. pause Counter (.s) resetn Counter modulo-6 BCD counter BCD counter BCD counter clock segment Decoder Counter (.s) N(3) N() N() N() N 4 -to-4 decoder s FSM Provide the Finite State Machine of the serialier in ASM (Algorithmic State Machine) form. Provide the VHDL description of the entire circuit: FSM + Datapath circuit. Tip: If you want to simulate your circuit, do not include the Counter to.s and the Counter to.s (instead, set the output signal to ). Otherwise, you might not be able to simulate your circuit.

2 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 FSM (ASM chart): S resetn= s S s S3 s S4 s VHDL code: 'dig_stopwatch.vhd' library I; use I.STD_LOGIC_64.ALL; use ieee.math_real.log; use ieee.math_real.ceil; entity dig_stopwatch is port (resetn, clock, pause: in std_logic; segs: out std_logic_vector (6 downto ); N: out std_logic_vector (3 downto )); end dig_stopwatch; architecture Behavioral of dig_stopwatch is component my_genpulse generic (COUNT: INTGR:= (**8)/); -- (**8)/ cycles of T = ns -->.5 s port (clock, resetn, : in std_logic; Q: out std_logic_vector ( integer(ceil(log(real(count)))) - downto ); : out std_logic); end component; component sevenseg port (bcd: in std_logic_vector (3 downto ); sevseg: out std_logic_vector (6 downto ); N: out std_logic_vector(3 downto )); end component; signal npause,, _, _, _, _3,_, _,_3: std_logic; signal omux, Q_, Q_, Q_, Q_3: std_logic_vector (3 downto ); signal s: std_logic_vector ( downto ); signal _fsm: std_logic; type state is (S, S, S3, S4); signal y: state; npause <= not (pause); Q_3(3) <= ''; -- Counter:.s g: my_genpulse generic map (COUNT => **6) port map (clock => clock, resetn => resetn, => npause, => ); -- Counter: g: my_genpulse generic map (COUNT => ) port map (clock => clock, resetn => resetn, =>, Q => Q_, => _);

3 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 -- Counter: g: my_genpulse generic map (COUNT => ) port map (clock => clock, resetn => resetn, => _, Q => Q_, => _); _ <= and _; -- Counter: g: my_genpulse generic map (COUNT => ) port map (clock => clock, resetn => resetn, => _, Q => Q_, => _); _ <= _ and _; -- Counter: 6 g3: my_genpulse generic map (COUNT => 6) port map (clock => clock, resetn => resetn, => _3, Q => Q_3 ( downto ), => _3); _3 <= _ and _; -- Multiplexor with s select omux <= Q_ when "", Q_ when "", Q_ when "", Q_3 when others; seg7: sevenseg port map (bcd => omux, sevseg => segs); -- -to-4 decoder with s select N <= "" when "", "" when "", "" when "", "" when "", "" when others; -- Counter:.s gfsm: my_genpulse generic map (COUNT => **5) port map (clock => clock, resetn => resetn, => '', => _fsm); Transitions: process (resetn, clock, _fsm) if resetn = '' then -- asynchronous signal y <= S; -- if resetn asserted, go to initial state: S elsif (clock'event and clock = '') then if _fsm = '' then case y is when S => y <= S; when S => y <= S3; when S3 => y <= S4; when S4 => y <= S; end case; end process; Outputs: process (y) case y is when S => s <= ""; when S => s <= ""; when S3 => s <= ""; when S4 => s <= ""; end case; end process; end Behavioral;

4 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 PROBLM (5 PTS) Design of a configurable lights pattern generator. sel: selects the pattern. stop: freees the pattern when stop=. Two 7-segment displays are used. The datapath circuit is provided. Input x : Selects the rate at which the lights pattern change (every.5,.,.5, or.5 seconds) sel segs[7..] : sel x stop resetn clock? 8 segs resetn clock Q?? counter (.5s) Q?? x stop sel FINIT STAT MACHIN dseg 8 sg D Q On the NXYS3, only one 7-segment display can be used at a time 7 counter (.s) 3 Counter (.s) Q?? FINIT STAT MACHIN s -to- decoder buf buf() buf() counter (.5s) Q?? x = Lights change every.5 s x = Lights change every. s x = Lights change every.5 s x = Lights change every.5 s counter (.5s) Provide both Finite State Machines in ASM form. ASM: Algorithmic State Machine. Provide the VHDL description of the entire circuit: FSMs + Datapath circuit.

5 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 Main FSM (ASM chart): S resetn= sel dseg, sg dseg, sg dseg, sg dseg, sg Sa Sb Sc Sd dseg, sg dseg, sg dseg, sg dseg, sg S3a S3b S3c S3d dseg, sg dseg, sg dseg, sg dseg, sg S4a S4b S4c S4d dseg, sg dseg, sg dseg, sg dseg, sg S5a S5d dseg, sg S6a dseg, sg dseg, sg S6d dseg, sg S8a S7a dseg, sg dseg, sg

6 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 FSM for 7-segment display control (ASM chart): S s resetn= S s VHDL code: 'lights_pattern.vhd' library I; use I.STD_LOGIC_64.ALL; use ieee.math_real.log; use ieee.math_real.ceil; entity lights_pattern is port (resetn, clock, stop: in std_logic; x, sel: in std_logic_vector ( downto ); segs: out std_logic_vector (6 downto ); N: out std_logic_vector (3 downto )); end lights_pattern; architecture Behavioral of lights_pattern is component my_genpulse generic (COUNT: INTGR:= (**8)/); -- (**8)/ cycles of T = ns -->.5 s port (clock, resetn, : in std_logic; Q: out std_logic_vector ( integer(ceil(log(real(count)))) - downto ); : out std_logic); end component; component my_rege generic (N: INTGR:= 4); port ( clock, resetn: in std_logic;, sclr: in std_logic; -- sclr: Synchronous clear D: in std_logic_vector (N- downto ); Q: out std_logic_vector (N- downto )); end component; type state is (S,Sa,S3a,S4a,S5a,S6a,S7a,S8a,Sb,S3b,S4b,Sc,S3c,S4c,Sd,S3d,S4d,S5d,S6d); signal y: state; type stateo is (S, S); signal yo: stateo; signal _fsm,, sg, a, b, c, d,, s: std_logic; signal dseg, seg: std_logic_vector (7 downto ); signal psegs: std_logic_vector (6 downto ); -- Counter:.5 s ga: my_genpulse generic map (COUNT => 3*((**8)/)) port map (clock => clock, resetn => resetn, => '', => a); -- Counter:. s gb: my_genpulse generic map (COUNT => **8) port map (clock => clock, resetn => resetn, => '', => b); -- Counter:.5 s gc: my_genpulse generic map (COUNT => (**8)/) port map (clock => clock, resetn => resetn, => '', => c); -- Counter:.5 s gd: my_genpulse generic map (COUNT => (**8)/4) port map (clock => clock, resetn => resetn, => '', => d);

7 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 -- Multiplexor for the counter outputs: with x select <= a when "", b when "", c when "", d when others; <= and not(stop); -- 8-bit register rp: my_rege generic map (N => 8) port map (clock => clock, resetn => resetn, => sg, sclr => '', D => dseg, Q => seg); -- Multiplexor for the 7-segment displays: with s select psegs <= seg(6 downto 3)&"" when '', seg(7)&""&seg( downto )&'' when others; -- segs: a b c d e f g segs <= not(psegs); -- Active-low outputs -- Counter:. s gfsm: my_genpulse generic map (COUNT => **5) port map (clock => clock, resetn => resetn, => '', => _fsm); -- -to- decoder with s select N <= "" when '', "" when others; -- Main FSM: Transitions: process (resetn, clock,, sel) if resetn = '' then -- asynchronous signal y <= S; -- if resetn asserted, go to initial state: S elsif (clock'event and clock = '') then case y is when S => if = '' then case sel is when "" => y <= Sa; when "" => y <= Sb; when "" => y <= Sc; when others => y <= Sd; end case; else y <= S; end process; when Sa => if = '' then y <= S3a; else y <= Sa; when S3a => if = '' then y <= S4a; else y <= S3a; when S4a => if = '' then y <= S5a; else y <= S4a; when S5a => if = '' then y <= S6a; else y <= S5a; when S6a => if = '' then y <= S7a; else y <= S6a; when S7a => if = '' then y <= S8a; else y <= S7a; when S8a => if = '' then y <= S; else y <= S8a; when Sb => if = '' then y <= S3b; else y <= Sb; when S3b => if = '' then y <= S4b; else y <= S3b; when S4b => if = '' then y <= S; else y <= S4b; when Sc => if = '' then y <= S3c; else y <= Sc; when S3c => if = '' then y <= S4c; else y <= S3c; when S4c => if = '' then y <= S; else y <= S4c; when Sd => if = '' then y <= S3d; else y <= Sd; when S3d => if = '' then y <= S4d; else y <= S3d; when S4d => if = '' then y <= S5d; else y <= S4d; when S5d => if = '' then y <= S6d; else y <= S5d; when S6d => if = '' then y <= S; else y <= S6d; end case;

8 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 Outputs: process (y,, sel) -- Initialiation of FSM outputs: dseg <= (others => ''); sg <= ''; case y is when S => if = '' then case sel is when "" => dseg <= ""; sg <= ''; when "" => dseg <= ""; sg <= ''; when "" => dseg <= ""; sg <= ''; when others => dseg <= ""; sg <= ''; end case; when Sa => if = '' then dseg <= ""; sg <= ''; when S3a => if = '' then dseg <= ""; sg <= ''; when S4a => if = '' then dseg <= ""; sg <= ''; when S5a => if = '' then dseg <= ""; sg <= ''; when S6a => if = '' then dseg <= ""; sg <= ''; when S7a => if = '' then dseg <= ""; sg <= ''; when S8a => if = '' then dseg <= ""; sg <= ''; when Sb => if = '' then dseg <= ""; sg <= ''; when S3b => if = '' then dseg <= ""; sg <= ''; when S4b => if = '' then dseg <= ""; sg <= ''; when Sc => if = '' then dseg <= ""; sg <= ''; when S3c => if = '' then dseg <= ""; sg <= ''; when S4c => if = '' then dseg <= ""; sg <= ''; when Sd => if = '' then dseg <= ""; sg <= ''; when S3d => if = '' then dseg <= ""; sg <= ''; when S4d => if = '' then dseg <= ""; sg <= ''; when S5d => if = '' then dseg <= ""; sg <= ''; when S6d => if = '' then dseg <= ""; sg <= ''; end case; end process; -- FSM: serialier for the 7-segment display Trans: process (resetn, clock, _fsm) if resetn = '' then -- asynchronous signal yo <= S; -- if resetn asserted, go to initial state: S elsif (clock'event and clock = '') then if _fsm = '' then case yo is when S => yo <= S; when S => yo <= S; end case; end process; Outps: process (yo) case yo is when S => s <= ''; when S => s <= ''; end case; end process; end Behavioral;

9 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 PROBLM 3 ( PTS) The figure depicts the architecture of a simple processor. Data_in n D Q n Data BUS R R R R3 A B _R O_R _R O_R _R O_R _R3 O_R3 _A op ALU s_l G din 4 left-shift _G L_G O_G _ext w fun 7 CONTROL CIRCUIT done Register G: Parallel Access left-shift register with enable. s_l = Load, s_l = Left-shift The figure below depicts the datapath and the FSM of the Control Circuit: funq = f f f Ry Ry Rx Rx fun _fun 7 D Q 7 Ry Rx funq so Rx Rx x o DCODR with enable DCODR with enable 3 3 _R _R _R _R3 O_R O_R O_R O_R3 w f 3 _fun x o so _A L_G _G FSM op 4 O_G _ext done

10 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 The following table specifies the behavior of the Arithmetic-Logic Unit (ALU). This ALU is purely combinatorial. op Operation Function Unit y <= A Transfer A y <= A + Increment A y <= A - Decrement A y <= B Transfer B y <= B + Increment B Arithmetic y <= B Decrement B y <= A + B Add A and B y <= A B Subtract B from 'A' y <= not A y <= not B y <= A AND B y <= A OR B y <= A NAND B y <= A NOR B y <= A XOR B y <= A XNOR B Complement A Complement B AND OR NAND NOR XOR XNOR Logic Operation: very time w = '', we store the input, then proceed to execute it. The 7 bits of the stored input, called, are arranged as: =. The first 3 bits specify the operation, while the other 4 bits specify the registers over which the operations are applied. f Operation Function Load Rx, Data Rx Data Add Rx, Data Rx Rx + Data Not Rx Rx NOT (Rx) Sub Rx, Ry Rx Rx - Ry Add Rx, Ry Rx Rx + Ry Move Rx, Ry Rx Ry sla Rx Rx left-shift Rx Addi Rx, Rx Rx + Design the Finite State Machine (provide it in ASM form) that can issue the correct set of signals for all the listed operations.

11 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 FSM (ASM chart): S resetn= w S _fun _ext, x done f o, so _A o, so _G,L_G op o, so _A o, so _A o, x done o, so _G,L_G op o, so _G,L_G op S3a _ext _G,L_G op S4a O_G, x done S5a o _G,L_G op S6a o _G,L_G op S7a _G L_G S8a _G,L_G O_G op S3b S5b S6b S7b S8b O_G, x done O_G, x done O_G, x done O_G, x done O_G, x done PROBLM 4 ( PTS) A B C For the following error-detection system, provide the truth table and sketch the circuits of i) the Odd Parity Generator, and ii) Odd parity checker. Transmitted bits A B C Odd Parity Generator TPB Odd Parity Checker RPB Odd parity generator: TPB is such that A B C TPB has an odd number of bits. Odd parity checker: Checks whether A B C TPB has an odd number of bits. If this is the case, RPB = '', otherwise RPB = '' (signaling an error).

12 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 Odd Parity Generator A B C A B C TPB TPB Odd Parity Checker A B C TPB RPB A B C TPB RPB Sketch the schematics of an n-bit comparator of two numbers represented in s complement. Required outputs: AgeB, AlB, AeB. If A >= B AgeB =. If A < B AlB =. If A = B AeB =. You can use adders (specify the number of bits) and XOR gates. Make sure that your circuit works in all circumstances (consider that A and B may cause overflow, you need to avoid it). A n- A B n n n+ n+ A n- B n- A n- B n-... A B A B A B B n- c out c n FA c n- FA c n-... c 3 FA c FA c FA c c in s n s n- s s s s n = A-B s n = A-B <... AlB AgeB AeB

13 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 PROBLM 5 (5 PTS) LUT connected to a bidirectional port: An LUT4-to- (also called LUT4) can implement a 4-input function. The VHDL code is provided below. Note that the values stored in the LUT are constant, hence those values are entered as a parameter in the VHDL code: library I; use I.STD_LOGIC_64.ALL; entity my4tolut is generic (data: std_logic_vector(5 downto ):=x"fab"); -- LUT 4-to- contents port ( ILUT: in std_logic_vector (3 downto ); OLUT: out std_logic); end my4tolut; architecture Behavioral of my4tolut is with ILUT select OLUT <= data() when "", data() when "", data() when "", data(3) when "", data(4) when "", data(5) when "", data(6) when "", data(7) when "", data(8) when "", data(9) when "", data() when "", data() when "", data() when "", data(3) when "", data(4) when "", data(5) when "", '' when others; end Behavioral; 4-to- Look-up Table (Read-only memory with 6 positions) ILUT address data() data() data() data(3) data(4) data(5) 4 data(6) OLUT data(7) data(8) data(9) data() data() data() data(3) data(4) data(5) LUTs with more than four inputs can be built by grouping several LUT 4-to- and MUXs. The figure below shows how an LUT 6-to- can be built. An LUT with more than one output can also be built. The figure below show how we can create an LUT 6-to-6 (we just use six LUT 6-to-). LI 6 MSBs 4 LSBs LI(3..) LUT4 LUT4 LUT4 LUT4 LI(4) MUX MUX LI(5) MUX LUT5-to- LUT6-to LUT 6 to LUT 6 to... LUT 6 to b 5 b 5 b b b 4 b LUT 6-to words of 6 bits column 5 6 bits column column LUT 6-to-6 6 You are asked to design a system with an LUT 6-to-6. This will be accomplished in a series of steps: Provide the VHDL code of an LUT 6-to-. You can built it by i) grouping four LUT4-to- and MUXs, or ii) using only one VHDL file (similar to my4tolut.vhd). The entity should look like this: entity my6tolut is generic (data: std_logic_vector(63 downto ):=x"fab97ca39cc"); values port ( ILUT: in std_logic_vector (5 downto ); OLUT: out std_logic); end my6tolut;

14 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 Write the VHDL code for an LUT 6-to-6. You must built it by grouping six LUT 6-to-. The entity should look like this: entity my6to6lut is generic (data5: std_logic_vector(63 downto ):=x"fab97ca39cc"; -- column 5 data4: std_logic_vector(63 downto ):=x"aabbccff9998a"; -- column 4 data3: std_logic_vector(63 downto ):=x"595bbcafdada"; -- column 3 data: std_logic_vector(63 downto ):=x"fac9933cab"; -- column data: std_logic_vector(63 downto ):=x"dcaffff9a3"; -- column data: std_logic_vector(63 downto ):=x"acad4baf5"); -- column port ( ILUT: in std_logic_vector (5 downto ); OLUT: out std_logic_vector (5 downto )); end my6to6lut; Important: When instantiating the my6tolut component, we use the port map instruction to make interconnections. Now, we also need to provide the correct parameter to each my6tolut component. This is done usually the generic map instruction. Final System: Provide the VHDL code of the circuit depicted below. Use the Structural Description by interconnecting the following components: i) LUT 6-to-6, ii) 6-bit register, and iii) Tri-state buffers. Important: The port 'DATA' can be input or output at different times. Use INOUT in your VHDL code. LUT6-to-6 contents: We want this LUT 6-to-6 to provide the following function: =. xample: =35 = 35. =3 Compute the contents of the LUT 6-to-6 and provide each column in hexadecimal format as: data5, data4, data3, data, data, data (generic input parameters) Complete the Timing diagram shown below. Note that the port DATA is input at some times, and output at other times. resetn clk DI 6 D Q 6 6 LUT 6-to-6 DO 6 DATA O clk resetn O DATA DI DO

15 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 LUT6-to-6 contents: LUT 6-to-6: hexadecimals converted in this direction b 5 b 4 b 3 b b b C A F C A F 8 6 F 9 5 C A F F F D F F C A F F 9 5 C B F F F 9 F F C F F 9 5 F C A F F data5 data4 data3 data data data VHDL code: 'syslut6to6.vhd' library I; use I.STD_LOGIC_64.ALL; entity syslut6to6 is generic (data5: std_logic_vector(63 downto ):=x"ffffffc"; -- column 5 data4: std_logic_vector(63 downto ):=x"fc3ffffc"; -- column 4 data3: std_logic_vector(63 downto ):=x"3ff3ff3ff"; -- column 3 data: std_logic_vector(63 downto ):=x"83ef83ef83ef"; -- column data: std_logic_vector(63 downto ):=x"639ce739ce7398cc"; -- column data: std_logic_vector(63 downto ):=x"5a596b5ad6a56aa"); -- column port (clk, resetn, O: in std_logic; data: inout std_logic_vector (5 downto )); end syslut6to6; architecture structure of syslut6to6 is component my_rege generic (N: INTGR:= 4); port ( clock, resetn: in std_logic;, sclr: in std_logic; -- sclr: Synchronous clear D: in std_logic_vector (N- downto ); Q: out std_logic_vector (N- downto )); end component; component my6to6lut generic (data5: std_logic_vector(63 downto ):=x"fab97ca39cc"; -- column 5 data4: std_logic_vector(63 downto ):=x"aabbccff9998a"; -- column 4 data3: std_logic_vector(63 downto ):=x"595bbcafdada"; -- column 3 data: std_logic_vector(63 downto ):=x"fac9933cab"; -- column data: std_logic_vector(63 downto ):=x"dcaffff9a3"; -- column data: std_logic_vector(63 downto ):=x"acad4baf5"); -- column port ( ILUT: in std_logic_vector (5 downto ); OLUT: out std_logic_vector (5 downto )); end component; signal DI, DO, QR: std_logic_vector (5 downto ); ri: my_rege generic map (N => 6) port map (clock => clk, resetn => resetn, => O, sclr => '', D => DI, Q => QR); LUT6to6: my6to6lut generic map (data5 => data5, data4 => data4, data3 => data3, data => data, data => data, data => data) port map (ILUT => QR, OLUT => DO); DATA <= DO when O = '' else (others => 'Z'); DI <= DATA when O = '' else (others => 'Z'); end structure;

16 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 VHDL code: 'my6to6lut' library I; use I.STD_LOGIC_64.ALL; entity my6to6lut is generic (data5: std_logic_vector(63 downto ):=x"fab97ca39cc"; -- column 5 data4: std_logic_vector(63 downto ):=x"aabbccff9998a"; -- column 4 data3: std_logic_vector(63 downto ):=x"595bbcafdada"; -- column 3 data: std_logic_vector(63 downto ):=x"fac9933cab"; -- column data: std_logic_vector(63 downto ):=x"dcaffff9a3"; -- column data: std_logic_vector(63 downto ):=x"acad4baf5"); -- column port ( ILUT: in std_logic_vector (5 downto ); OLUT: out std_logic_vector (5 downto )); end my6to6lut; architecture Behavioral of my6to6lut is component my6tolut generic (data: std_logic_vector(63 downto ):=x"accabbfacfab"); port ( ILUT: in std_logic_vector (5 downto ); OLUT: out std_logic); end component; signal OLUT_l, OLUT_h: std_logic; -- 6-to- LUT holding contents of column 5: r5: my6tolut generic map (data => data5) port map (ILUT => ILUT, OLUT => OLUT(5)); -- 6-to- LUT holding contents of column 4: r4: my6tolut generic map (data => data4) port map (ILUT => ILUT, OLUT => OLUT(4)); -- 6-to- LUT holding contents of column 3: r3: my6tolut generic map (data => data3) port map (ILUT => ILUT, OLUT => OLUT(3)); -- 6-to- LUT holding contents of column : r: my6tolut generic map (data => data) port map (ILUT => ILUT, OLUT => OLUT()); -- 6-to- LUT holding contents of column : r: my6tolut generic map (data => data) port map (ILUT => ILUT, OLUT => OLUT()); -- 6-to- LUT holding contents of column : r: my6tolut generic map (data => data) port map (ILUT => ILUT, OLUT => OLUT()); end Behavioral; VHDL code: 'my6tolut' library I; use I.STD_LOGIC_64.ALL; entity my6tolut is generic (data: std_logic_vector(63 downto ):=x"accabbfacfab"); port ( ILUT: in std_logic_vector (5 downto ); OLUT: out std_logic); end my6tolut; architecture Behavioral of my6tolut is component my5tolut generic (data: std_logic_vector(3 downto ):=x"facfab"); port ( ILUT: in std_logic_vector (4 downto ); OLUT: out std_logic); end component; signal OLUT_l, OLUT_h: std_logic; -- 5-to- LUT holding contents: data(3 downto ) rl: my5tolut generic map (data => data(3 downto )) port map (ILUT => ILUT(4 downto ), OLUT => OLUT_l); -- 5-to- LUT holding contents: data(63 downto 3) rh: my5tolut generic map (data => data (63 downto 3)) port map (ILUT => ILUT(4 downto ), OLUT => OLUT_h); with ILUT(5) select OLUT <= OLUT_l when '', OLUT_h when others; end Behavioral;

17 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 VHDL code: 'my5tolut' library I; use I.STD_LOGIC_64.ALL; entity my5tolut is generic (data: std_logic_vector(3 downto ):=x"facfab"); port ( ILUT: in std_logic_vector (4 downto ); OLUT: out std_logic); end my5tolut; architecture Behavioral of my5tolut is component my4tolut generic (data: std_logic_vector(5 downto ):=x"fab"); port ( ILUT: in std_logic_vector (3 downto ); OLUT: out std_logic); end component; signal OLUT_l, OLUT_h: std_logic; -- 4-to- LUT holding contents: data(5 downto ) rl: my4tolut generic map (data => data(5 downto )) port map (ILUT => ILUT(3 downto ), OLUT => OLUT_l); -- 4-to- LUT holding contents: data(3 downto 6) rh: my4tolut generic map (data => data (3 downto 6)) port map (ILUT => ILUT(3 downto ), OLUT => OLUT_h); with ILUT(4) select OLUT <= OLUT_l when '', OLUT_h when others; end Behavioral; VHDL Testbench LIBRARY ieee; US ieee.std_logic_64.all; use ieee.std_logic_arith.all; NTITY tb_syslut6to6 IS ND tb_syslut6to6; ARCHITCTUR behavior OF tb_syslut6to6 IS BGIN -- Component Declaration for the Unit Under Test (UUT) COMPONNT syslut6to6 PORT (clk : IN std_logic; resetn : IN std_logic; O : IN std_logic; data : INOUT std_logic_vector(5 downto )); ND COMPONNT; --Inputs signal clk : std_logic := ''; signal resetn : std_logic := ''; signal O : std_logic := ''; --BiDirs signal data : std_logic_vector(5 downto ); -- Clock period definitions constant clk_period : time := ns; -- Instantiate the Unit Under Test (UUT) uut: syslut6to6 PORT MAP (clk => clk, resetn => resetn, O => O, data => data); -- Clock process definitions clk_process :process clk <= ''; wait for clk_period/; clk <= ''; wait for clk_period/; end process;

18 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 ND; -- Stimulus process stim_proc: process -- hold reset state for ns. resetn <= ''; DATA <= "ZZZZZZ"; wait for ns; resetn <= ''; wait for clk_period; O <= ''; DATA <= ""; wait for *clk_period; O <= ''; DATA <= "ZZZZZZ"; wait for *clk_period; O <= ''; DATA <= ""; wait for *clk_period; O <= ''; DATA <= "ZZZZZZ"; wait for *clk_period; O <= ''; DATA <= ""; wait for *clk_period; O <= ''; DATA <= "ZZZZZZ"; wait for *clk_period; O <= ''; DATA <= ""; wait for *clk_period; O <= ''; DATA <= "ZZZZZZ"; wait for *clk_period; wait for 4*clk_period; O <= ''; lp: for i in to 63 loop DATA <= conv_std_logic_vector(i,6); wait for clk_period; end loop; end process; Timing diagram: clk resetn O DATA DI DO XTRA CRDIT (+ PTS) Demonstrate the circuits of Problems and working on the NXYS3 board. UCF File for Problem : 'dig_stopwatch.ucf' # Inputs NT "clock" LOC = "V"; NT "resetn" LOC = "T"; #SW NT "pause" LOC = "T9"; #SW # Outputs NT "N<3>" LOC = "P7"; # anode (st display from left to right) NT "N<>" LOC = "P8"; # anode (nd display from left to right) NT "N<>" LOC = "N5"; # anode (3rd display from left to right) NT "N<>" LOC = "N6"; # anode (4th display from left to right) NT "segs<6>" LOC = "T7"; # a NT "segs<5>" LOC = "T8"; # b NT "segs<4>" LOC = "U7"; # c NT "segs<3>" LOC = "U8"; # d NT "segs<>" LOC = "M4"; # e NT "segs<>" LOC = "N4"; # f NT "segs<>" LOC = "L4"; # g

19 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 UCF File for Problem : 'lights_pattern.ucf' # Inputs NT "clock" LOC = "V"; NT "resetn" LOC = "T5"; #SW7 NT "stop" LOC = "B8"; #BTNS (center) NT "x<>" LOC = "T9"; # SW NT "x<>" LOC = "T"; # SW NT "sel<>" LOC = "M8"; # SW3 NT "sel<>" LOC = "V9"; # SW # Outputs NT "N<3>" LOC = "P7"; # anode (st display from left to right) NT "N<>" LOC = "P8"; # anode (nd display from left to right) NT "N<>" LOC = "N5"; # anode (3rd display from left to right) NT "N<>" LOC = "N6"; # anode (4th display from left to right) NT "segs<6>" LOC = "T7"; # a NT "segs<5>" LOC = "T8"; # b NT "segs<4>" LOC = "U7"; # c NT "segs<3>" LOC = "U8"; # d NT "segs<>" LOC = "M4"; # e NT "segs<>" LOC = "N4"; # f NT "segs<>" LOC = "L4"; # g APPNDIX: XTRA VHDL FILS VHDL code: 'my_genpulse.vhd' library I; use I.STD_LOGIC_64.ALL; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.math_real.log; use ieee.math_real.ceil; entity my_genpulse is generic (COUNT: INTGR:= (**8)/); -- (**8)/ cycles of T = ns -->.5 s port (clock, resetn, : in std_logic; Q: out std_logic_vector ( integer(ceil(log(real(count)))) - downto ); : out std_logic); end my_genpulse; architecture Behavioral of my_genpulse is constant nbits: INTGR:= integer(ceil(log(real(count)))); signal Qt: std_logic_vector (nbits - downto ); process (resetn, clock) if resetn = '' then Qt <= (others => ''); elsif (clock'event and clock = '') then if = '' then if Qt = conv_std_logic_vector (COUNT-,nbits) then Qt <= (others => ''); else Qt <= Qt + conv_std_logic_vector (,nbits); end process; <= '' when Qt = conv_std_logic_vector (COUNT-,nbits) else ''; Q <= Qt; end Behavioral;

20 DPARTMNT OF LCTRICAL AND COMPUTR NGINRING, TH UNIVRSITY OF NW MXICO C-38L: Computer Logic Design Fall 3 VHDL code: 'my_rege' library I; use I.STD_LOGIC_64.ALL; -- N-bit Register -- = '', sclr = '' --> Input data 'D' is copied on Q -- = '', sclr = '' --> Q is cleared () entity my_rege is generic (N: INTGR:= 4); port ( clock, resetn: in std_logic;, sclr: in std_logic; -- sclr: Synchronous clear D: in std_logic_vector (N- downto ); Q: out std_logic_vector (N- downto )); end my_rege; architecture Behavioral of my_rege is signal Qt: std_logic_vector (N- downto ); process (resetn, clock) if resetn = '' then Qt <= (others => ''); elsif (clock'event and clock = '') then if = '' then if sclr = '' then Qt <= (others => ''); else Qt <= D; end process; Q <= Qt; end Behavioral; VHDL code: 'sevenseg.vhd' library I; use I.STD_LOGIC_64.ALL; entity sevenseg is port (bcd: in std_logic_vector (3 downto ); sevseg: out std_logic_vector (6 downto ); N: out std_logic_vector(3 downto )); end sevenseg; architecture structure of sevenseg is signal leds: std_logic_vector (6 downto ); -- a b c d e f g -- leds6 leds5 leds4 leds3 leds leds leds with bcd select leds <= "" when "", "" when "", "" when "", "" when "", "" when "", "" when "", "" when "", "" when "", "" when "", "" when "", " " when others; -- There are 4 7-seg displays that can be used. We will use only the first (from left to right): N <= ""; -- only the first 7-seg display is activated. -- N(3) goes to one 7-seg display. It goes to every LD anode. -- To provide a logic '' to the anode, we need N(3) to be ero (see circuit) sevseg <= not(leds); end structure;