Flexible ASIC: Shared Masking for Multiple Media Processors

Transcription

1 54.1 Flexble ASIC: Shared Maskng for Multple Meda Processors Jennfer L. Wong Unv. of Calf., Los Angeles Los Angeles, Calforna Farnaz Kourshanfar Unv. of Calf., Berkeley Berkeley, Calforna Modrag Potkonjak Unv. of Calf., Los Angeles Los Angeles, Calforna ABSTRACT ASIC provdes more than an order of magntude advantage n terms of densty, speed, and power requrement per gate. However, economc (cost of masks) and technologcal (deep mcron manufacturablty) trends favor FPGA as an mplementaton platform. In order to combne the advantages of both platforms and allevate ther dsadvantages, recently a number of approaches, such as structured ASIC/regular fabrcs, have been proposed. Our goal s to ntroduce an approach that has the same objectve, but s orthogonal to those already proposed. The dea s to mplement several ASIC desgns n such a way that they share the datapath, memory structure, and several bottom layers of nterconnect, whle each desgn has only a few unque metal layers. We dentfed and addressed two man problems n our quest to develop a CAD flow for realzaton of such desgns. They are: () the creaton of the datapath, and () the dentfcaton of common and unque nterconnects for each desgn. Both problems are solved optmally usng ILP formulatons. We assembled a desgn flow platform usng two new programs and the Trmaran and Shade tools. We quanttatvely analyzed the advantages and dsadvantages of the approach usng the Medabench benchmark sute. Categores and Subject Descrptors: B.5.1 [Desgn Ads]: Optmzaton General Terms: Desgn. Keywords: ASIC, nterconnect, optmzaton. 1. INTRODUCTION The tradtonal dlemma for many desgn teams has been ASIC or FPGA. FPGAs provde sgnfcant advantages over ASIC n terms of turn-around-tme, flexblty, testablty and sutablty for debuggng. However, for a gven technology ASIC provdes over 12 tmes hgher speed, almost 50 tmes hgher densty, and more than 500 tmes lower power per gate [18]. Exponental growth of mask cost and a more demandng manufacturablty process wth each new gener- Permsson to make dgtal or hard copes of all or part of ths work for personal or classroom use s granted wthout fee provded that copes are not made or dstrbuted for proft or commercal advantage and that copes bear ths notce and the full ctaton on the frst page. To copy otherwse, to republsh, to post on servers or to redstrbute to lsts, requres pror specfc permsson and/or a fee. DAC 2005, June 13 17, 2005, Anahem, Calforna, USA. Copyrght 2005 ACM /05/ $5.00. aton of deep submcron technology caused two major ramfcatons on mplementaton platforms. Specfcally, whle n 0.25 mcron the Non-Recurrng Engneerng (NRE) cost (mask set and probe card) was $100,000, t wll approach $2 mllon for 65 nm [18]. At the same tme prntablty and process varaton challenges favor regular desgns [13]. The frst consequence s that regardless of great delay, area, and ASIC advantages, the number of ASIC desgns has to be consstently decreasng. For example, over the last 15 years, the number of ASIC desgns has been reduced 6 tmes (from 15,000 to 2,500). ASIC s currently used only for very large volume desgns. If we consder a relatvely large half of mllon volume, n 65 nm, the NRE cost wll add $4 per desgn, whch s often unacceptable overhead. The second consequence s the emergence of a quest for new desgn mplementaton platforms and desgn methodologes to develop solutons that preserve some of the advantages of ASIC whle reducng NRE costs and ncreasng manufacturablty. A number of mplementaton platforms amed to reduce mask and therefore NRE costs and to brdge the gap between ASICs and FPGAs have recently been proposed. The new ndustral platform s commonly called structured ASIC or hybrd-fpga structures and s pursued by large semconductor companes, CAD houses, and start-ups [4, 5, 7, 9, 12, 15, 17, 18]. Academc researchers often refer to ths mplementaton platform as regular fabrcs and have focused ther efforts manly on ether defnng the structure of the fabrc or explorng how the physcal desgn s mpacted by the emergng mplementaton platforms [2, 6, 7, 8, 11, 13, 14]. Most often the new platform conssts of an array of logc cells bult usng dffuson and a few bottom metal layers. Logc cells contan programmable combnatoral logc and often storage elements. Therefore, the bottom mask layers are common to all desgns that wll be executed on ths platform. Note that n addton to logc cells that can be customzed, the nterconnect network on the top few layers s generated usng custom masks specfcally crafted for a specfc desgn. Therefore the approach sgnfcantly reduces the number of requred custom masks and preserves some of the advantages n terms of delay, power, and area of a standard cell-based ASIC mplementaton platform. It s estmated that performances of ths platform are nferor to fully custom ASIC by a factor of 2-4. However, specalzed structure ASIC CAD tools are requred. Although our approach explores exactly the same dvson of layers n terms of common and customzed, the approach s complementary to the ones already presented. Note that a few bottom layers n our case can be ether fully customzed 909

2 A 1 A 2 B 1 B 2 C 1 C 2 D 1 D 2 A B Fgure 1: Basc archtecture of meda applcatons. and mplemented usng cell-based ASIC, or can leverage on the bottom few layers of a structured ASIC. In the former case, we preserve all ASIC advantages n terms of area, delay, and power. In the later case, the emphass s on enhanced manufacturablty through regularty and reduced testng and debug costs. Furthermore, we focus on the regster transfer and behavoral levels for the development of CAD tools for the effectve use of new ASIC mplementaton platforms wth reduced cost and shared bottom layers. We dentfed two man aspects for developng CAD tools for flexble top layer ASIC mplementaton platforms. The frst problem s how to select functonal unts that wll address the needs of all applcatons. The second problem s how to assgn nterconnect to both the shared and customzed metal layers. We proved that both problems are NP-complete and can be optmally solved usng nteger lnear programmng (ILP) formulatons. Snce the sze of the nstances for realstc desgns are relatvely moderate, the runtme of the CPLEX ILP solver n all cases was less than 0.1 second. 1.1 Motvatonal Example The key dea behnd the flexble ASIC approach s to generate nterconnect assgnments for dfferent applcatons n such a way that all the applcatons have the same basc mask layers. The only dfference would be the nterconnect confguratons for the upper layers. The approach can be ntroduced and llustrated usng the followng example. Assume that we have fve dfferent applcaton-specfc meda processors, namely JPEG encoder, MPEG encoder, GSM encoder, G.721 encoder and Pegwt encoder. For the sake of clarty and smplcty, we show a very smplstc vew of these encoder archtectures. Assume that the basc archtecture shown n Fgure 1 should be used for buldng all the encoders and only the nterconnect requrements dffer. We have four dfferent functonal unts denoted by A, B, C, and D. Each unt has an output wth the same name as ts block. There are two nputs for each blocks denoted as A 1, A 2, B 1, B 2, C 1, C 2, D 1,andD 2 respectvely. Table 1, shows the nterconnect requrements for these fve dfferent meda processors. Each row of the table represents an nterconnect between the output of a block to the nput of another block. Each column of the table represents a desgn. Assume that the chp has nne layers and requres that each layer can only have a maxmum of two nterconnects. If we drectly mplement each desgn, we wll need fve ASICs each wth nne layers of nterconnect, for a total of 45 nterconnect masks. However, by usng the concept of flexble ASIC and analyzng the common nterconnects requred for all desgns, the nterconnect requrements can be organzed as n Table 2. The leftmost column of Table 2 shows the nputs to each block. Each column afterward shows the output that C D Applcaton IC JPEG MPEG GSM P.721 Pegwt AA 1 AA AB AB 2 AC 1 AD BA 2 BB 1 BC BC 2 BD BD CA CB 1 CB 2 CD 1 DA 1 DB 2 DC 1 DC DD 1 DD 2 Table 1: Interconnects requred for each of the meda processors. Input Basc JPEG MPEG GSM P.721 Pegwt A 1 A,D C C - - C A 2 B A A B 1 B,C A A - - A B 2 A,C,D C 1 A,D B B B - - C 2 B - - B B - D 1 C,D B B D 2 D - A A,B B - Table 2: The nput/output relatonshp for the encoder applcatons. enters the correspondng nput. The second column shows the basc archtecture nterconnecton that s the same for all fve dfferent applcatons. Columns 3 through 6 ndcate the outputs per meda applcaton that are the requred nterconnects wth each of the nputs on each row, n addton to the basc nterconnects. Therefore, the frst seven layers are completely dedcated to the 14 nterconnects ncluded n the basc archtecture (column 2 of Table 2). The remanng nterconnects are assgned to the remanng two layers n such a way that we have the mnmum number of varants per layer and completely mplement each of the meda processors. We fnd the followng four varants (nstantaton for the nterconnects on one layer) for our fve encoders: v 1: CA 1, AB 1, v 2: CA 1, AB 1, v 3: BD 2, DC 2, v 4: BD 1, AA 2. By lookng at the nterconnect requrements from Table 2, we see that varants v 1 and v 2 can be used for realzng the MPEG and the JPEG decoders. Varants v 2 and v 3 can realze the GSM encoder. Varants v 3 and v 4 can realze the G.721 encoder, whle varants v 1 and v 4 can realze the Pegwt encoder. Therefore, the addton of only two layers to the basc layers can realze the full archtecture for all fve encoders. For each archtecture the frst seven layers are dentcal n terms of masks, whle the last two layers are realzed by two of the four varants correspondng to each archtecture and are hence dfferent. Therefore, usng flexble ASIC only eleven unque metal layers are necessary to realze all fve meda processors. 910

3 Lbrary Programs CDFG Profler Archtectural Profle Logc Level Defnton DP & Interconnect Archtecture Fgure 2: Global Flow. Interconnect Assgnment Layer Identfcaton & Assgnment In the followng secton we brefly dscuss the related work. In Secton 2 we dentfy the overall flow of the approach for realzaton of multple applcatons on a sngle chp. We ntroduce our ILP approach for determnng the basc layers of the chp n Secton 3. We formulate the nterconnect assgnment problem usng nteger lnear programmng (ILP) for two optmzatons: mnmal varant layers and mnmal desgn and manufacturng cost. Before concludng the work we present the expermental analyss of the technque. 2. DESIGN FLOW Fgure 2 shows the flow of our flexble ASIC approach. The nput to the CAD system s a set of applcatons specfed usng C or VHDL programs. In our expermentaton, we focused on the mplementaton of large meda applcatons that have been specfed and smulated for ther functonalty correctness usng C programs. Specfcally, we consdered all Medabench applcatons [10] and the Vterb convoluton encoder. All programs have been profled for the dentfcaton of the number of operatons and transfers of each type. Proflng s accomplshed through a relatvely smple wrapper around the Trmaran [16] and Shade tools [1]. The output of the CDFG profler s the requred datapath and nterconnect requrements of each applcaton specfed at the behavoral level. Ths profle s an nput, together wth a lbrary of the avalable functonal unts, to a program that dentfes the best unts for ncluson n the datapath n such a way the the lkelhood that all tmng constrants for all applcatons are satsfed and the area of the desgn mnmzed. Note that we do not specfcally optmze the memory structure. In practce we observed that t s suffcent to allocate memory requrements of the most ntensve applcaton for all others. The result of the datapath defnton module has two components. The frst s a set of mult-functonal unts that satsfy the specfed clock cycle tme. The second s the set of requred nterconnects for each applcaton. The second component s the nput nto the layer dentfcaton and assgnment program that mnmzes the total number of unque layers requred for all applcatons. We consdered two varants of the layer dentfcaton assgnment problem: () where the goal s to solely mnmze the number of unque layers, and () where the layers are dentfed and assgned n such a way that the sum of the NRE and manufacturng cost s mnmzed. Both the datapath and layer dentfcaton assgnment programs are solved usng ILP. For ths purpose we used the CPLEX solver. 3. DATAPATH DEFINITION In ths secton, we frst formulate the datapath defnton problem and ts complexty. We present the ILP formulaton of the problem whch can be solved usng any ILP solver. We assume that a set of applcatons s gven. The goal s to allocate a datapath for these applcatons usng the avalable lbrary of functonal unts. The lbrary contans specfcatons for a number of unt types. The goal s to fnd a mappng whch mnmzes the total area used by the logcal level defnton (actual functonal unts) of our applcatons. The problem can be more formally stated as follows. Note that, we defne the problem nstance n such a way that we can drectly use t as the nput to our ILP formulaton n the next subsecton. Problem: Datapath Defnton Problem Instance: A set of applcatons MP k, k =1,..., N k. AnumberofoperatonsOP j, j =1,..., N j. A set of requred operatons RO kj, that defne f the operaton OP j s requred by the applcaton MP k, j =1,..., N j, k =1,..., N k : 1, f operaton OPj s requred by MP RO kj = k, The archtectural profles P kj, that defnes the number of operatons of type OP j n the applcatons MP k, j = 1,..., N j, k =1,..., N k. A number of for functonal unt types (famles) TFU, =1, 2,..., N. A lbrary wth elements L j such that each type of functonal unts TFU can perform the operatons OP j, = 1, 2,..., N, j =1,..., N j: 1, f TFU can perform operatons of type OP L j = j, An actual set of functonal unts FU a, a =1,..., N a; An area cost A, for each functonal unt type TFU, =1, 2,..., N. A throughput constrant T k correspondng to each applcaton MP k, k =1,..., N k. Queston: Is there a subset of functonal unts FU a, a = 1,..., N a, such that the subset has the cardnalty N sub and all applcatons are realzable (functonal unts and transfers) and the total cost s mnmzed? 3.1 NP-Completeness The datapath defnton problem s NP-complete. It s a specal case of the mnmum cover problem. The mnmum cover problem s formulated as followng n Garey-Johnson format [3]. Problem: [SP5] Mnmum cover Instance: Collecton C of subsets of a fnte set S, postve nteger K C. Queston: Does C contan a cover for S of sze K or less,.e., a subset C C wth C K such that every element of S belongs to at least one member of C? We prove that the mnmum cover problem s a specal case of the datapath defnton problem. Each element n the set cover problem corresponds to a type of operaton n the specfcaton of the desgns. Each collecton corresponds to a functonal unt n the lbrary that can execute a set of operatons that correspond to the elements of the set cover problem. The goal s to select at most K collectons, or 911

4 functonal unts, whch mplement all the operatons. Note that the throughput constrant on the functonal unts s not enforced n the case of the mnmum cover problem. 3.2 ILP Formulaton of the Problem In order to solve ths problem usng ILP, a number of varables are defned. The frst set of varables are denoted by x a and relate the actual functonal unts FU a to the type of functonal unts TFU, a =1,..., N a, =1, 2,..., N : 1, f functonal unts FUa s of type TFU x a =, (1) The second set of varables are denoted by t kja and are defned for each applcaton MP k, and determne the number of operatons of type OP j assgned to the functonal unt FU a,,k =1,..., N k, j =1,..., N j, a =1,..., N a. The objectve functon s to mnmze the total cost of the mplementaton area requred for mplementaton of the applcatons (actual functonal unts): mn A x a We ntroduce four sets of constrants for the problem. The frst set of constrants (C 1), ensures that each functonal unt FU a s only of one specfc type TFU. The second set of constrants (C 2), enforces each applcaton to be realzable by the selected functonal unts. Thus, for each applcaton MP k, all operatons of type OP j, must be mplemented by at least one selected functonal unt FU a: C 1 : a, x a =1 C 2 : k, j, a O kj L jx a 1 a Not only must each of the applcatons be realzable, but the throughput constrant for each applcaton should be met. The thrd and fourth sets of constrants enforce the throughput constrants for each applcaton and each type of operaton. The thrd set of constrants (C 3) ensures that all nstances of the operaton are assgned to a selected functonal unt whch can perform the operaton. C 3 conssts of two notons, the frst of whch specfes f the selected functonal unt FU a of type TFU can perform the operaton OP j. If so, then ths functonal unt can be assgned the operaton of type OP j. Secondly, the sum of all operatons of type TFU j assgned to all selected functonal unts must equal the total number of operatons requred for MP k.we mplement these requrements usng the logcal AND ( ) functon. AND s mplemented n terms of ILP constrants by ntroducng a new varable and addng three constrants for each AND operaton. Specfcally, a b = c s mplemented n the followng way where c s a bnary varable. a + b c 1 a c 0 b c 0 The fourth and last set of constrants (C 4), ensures that all the assgned operatons to an actual functonal unt for a gven applcaton do not exceed the throughput lmtatons of that applcaton. For each applcaton MP k,andforeach selected functonal unt FU a, for any type of operaton OP j that the functonal unt of a certan type can perform, the sum must be less than the throughput specfed for the operaton: C 3 : O kj =1, C 4 : k, a, (L jx a t kja )=P kj a (L jx a t kja ) T k 4. INTERCONNECT ASSIGNMENT j Once the datapath for each of the processors s defned (.e. the soluton from the datapath defnton problem), the next step s to determne the nterconnect assgnments for each of the processors. In ths secton, we frst formulate the nterconnect assgnment problem and the complexty of the problem. Next, we present the ILP formulaton of the problem. Fnally, we ntroduce a varant on the orgnal problem formulaton whch addresses the mnmzaton of the total mplementaton cost of all layers. Assume the nterconnect specfcatons for a number of applcaton-specfc meda processors MPs s known. In addton, the specfc nterconnects for each of the meda processors are gven. The fabrcaton process has a constrant on the number of nterconnects per layer. The goal s to assgn nterconnects to the dfferent layers for each applcaton n such a way that the maxmum number of layers can be shared between the applcatons, only a few layers vary for dfferent applcatons, and the constrants on the number of nterconnects on one layer are satsfed. More formally the problem can defned as follows. Problem: Interconnect Assgnment Problem Instance: Applcaton-specfc meda processors (MP k ) wth specfed nterconnects, number of layers (S), number of nterconnects per layer (M), number of allowable varatons for each layer (R). Queston: Is there an assgnment of nterconnects to each layer s.t. the total number of created varatons are for all layers are mnmal, and each MP k s created? 4.1 NP-Completeness The nterconnect assgnment problem s NP-complete. It s a specal case of the Largest Common Subgraph problem. The Largest Common Subgraph problem s formulated n the Garey-Johnson format [3] as: Problem: [GT49] Largest Common Subgraph Instance: Graph G = (V 1,E 1), H = (V 2,E 2), postve nteger K. Queston: Do there exst subsets E 1 E 1 and E 2 E 2 wth E 1 = E 2 K such that the two subgraphs G = (V 1,E 1) and H =(V 2,E 2) are somorphc? Note that the nterconnect requrements for each applcaton form a graph, where the vertces of the graphs are the functonal blocks of the MPs and the edges are the nterconnects between the blocks. When we have only two applcatons, the selected subset of edges s the set of nterconnects whch are shared by the meda processors. In ths case the goal s to fnd the maxmal set. 4.2 ILP Formulaton We now show the notatons and the varables that are used for formulatng the nterconnect assgnment problem n 912

5 ILP. We assume that the total number of layers s specfed s = 1,...,S}, aswellasthemaxmumnumberofvarants per layer r = 1,...,R}. The maxmum number of nterconnects on one layer s denoted by a constant M and s an nput to the problem. The three dmensonal matrx W jk s an nput to the problem and ndcates the data flow edges (nterconnects) for each applcaton k. More specfcally, 1, f the edge (,j) exst n applcaton k, W jk = The soluton to the problem fnds dfferent varants (nstantatons) for each of the layers. The four dmensonal varable x jrs s used to denote the nterconnect assgnment for each layer n each of the varants. More formally, 1, f the edge (,j) exst n varant r on layer s, x jrs = Addtonally, we defne a three dmensonal varable, u krs, that lnks each applcaton to the layers and the varant on that layer on whch ts nterconnect requrements are mplemented. 1, f the applcaton k uses varant r on layer s, u krs = Lastly, we defne a varable to denote f a possble varant s used on each layer. The two dmensonal varable y rs s such a varable and s defned below. 1, f varant r s used on layer s, y rs = Note that the varables x jrs, u krs,andy rs are not ndependent of each other and we wll defne a set of constrants n the problem formulaton that relates these three varables. The objectve functon of the problem s to mnmze the total number of varants on all of the chp layers. Ths objectve functon can be formally wrtten as: mn There are fve constrants to the formulaton whch relate the above varables together and specfy the lmtatons on the varables. The frst constrant of the problem (C 5)ensures that each of the requred nterconnects for all the applcatons are mplemented on at least one varant on any of the layers of the chp. Ths ensure that each of the meda applcatons can be realzed on the chp. More formally, C 5 : k [1,K], (,j) W jk x jrs r s C 6 : s, r, x jrs M C 7 : k [1,K], layers s, r s y rs j u krs 1 The second constrant of the problem (C 6) s to ensure that each layer has at most the maxmum number of M nterconnects at each layer,.e., When realzng each of the applcatons the requred nterconnects must all be mplemented on only one varant per layer. To ensure ths, the thrd constrant (C 7) specfes that each applcaton can only be assgned at most one varant at each layer. In other words, The two fnal constrants (C 8 and C 9)relateallthevarables to each other. In partcular, the constrant C 8 determnes r the relatonshp between the overall used layers, y rs, and the layers used by each specfc applcaton, u krs. The relatonshp s straghtforward from the defnton of the two varables. If an applcaton k uses varant r on layer s (e. u krs = 1), then the varant r on layer s must be used. Ths relatonshp s shown as follows. C 8 : k [1,K] y rs u krs C 9 :, j u krs W jk x jrs Constrant C 9 specfes the relatonshp between the nterconnects on each varant of each layer, x jrs, andthevarant layers whch are used for each applcaton, u krs. Ths relatonshp s also drectly concluded from the defntons. If the edge (,j) exsts n varant r on layer s, and also the edge (,j) s requred for realzaton of applcaton k, thenx jrs and W jk are one. In such a stuaton, the applcaton k can use the varant r on layer s,.e. u krs = Interconnect Assgnment for Cost In ths Subsecton the focus of the optmzaton swtches from mnmzng the number of total varant layers to mnmzng the monetary cost for mplementaton of the layers, both desgn and manufacturng. We assume that the cost of desgnng each of the layers s known along wth the amount of each meda processor to be manufactured. Consderng these new nputs the problem can be formally defned as follows. Problem: Cost Mnmzaton wth Interconnect Assgnment Instance: Applcaton-specfc meda processors (MP k ) wth specfed nterconnects, number of layers (S), number of nterconnects per layer (M), number of allowable varatons for each layer (R), cost for desgn for each layer (D), volume of manufacturng each meda processors (V k ). Queston: Is there an assgnment of nterconnects to each layer s.t. the total cost of desgn and manufacturng all desgns s mnmal and each MP k s created? In order to address ths problem whch s an extenson of the nterconnect assgnment problem, we reformulate the objectve functon to focus on the total cost rather than the number of layers. The total cost s the cost to desgn each of the necessary layers, plus for each layer the volume of manufacturng necessary for each of the meda processors. Therefore, usng the same formulaton varables from the nterconnect assgnment problem we formulate the objectve functon as: mn D ( y rs)+ (V k ( u krs )) r s k r s All constrants of the problem are dentcal to the nterconnect assgnment problem. 5. EXPERIMENTAL RESULTS Flexble ASIC s partcularly well suted for computatonal ntensve applcatons such as meda processors. Therefore, for evaluaton purposes we used 21 applcatons from the Medabench benchmark sute [10] and the Vterb decoder that s wdely used n both wreless and optcal communcatons. The Vterb decoder was obtaned from the LSI Logc corporaton and s denoted n Table 3 by V. The Medabench 913

6 desgns # ofdesgns # ofntal # ofcustom # of fnal reducton ntal fnal cost layers layers layers cost ($M) cost ($M) reduct A,B,C,D,V % % G,H,I,J,V % % A,B,L,M,N % % A,B,C,D,I,J % % G,H,I,J,M,N % % O,P,Q,R,S,T % % A,B,C,D,G,H,I,J % % A,B,E,F,G,H,I,J % % A,B,G,H,I,J,L,M,N,V % % A,B,C,D,G,H,I,J,K,L % % Table 3: Analyss of the new flexble ASCI scheme n terms of technologcal complexty (number of layers) and estmated cost for the case where on manufacturng of each desgn $1M s spent per desgn. desgns have been denoted usng the followng notaton : Cjpeg (A), Djpeg (B), MPEG2encode (C), MPEG2decode (D), toast (E), untoast (F), rawcaudo (G), rawdaudo (H), G.721 encode (I), G.721 decode (J), PGPencode (K), PG- Pdecode (L), PEGWITencode (M), PEGWITdecode (N), Ghostscrpt(O),mpmap(P),osdemo(Q),texgen(R),rasta (S), EPIC (T), and unepic (U). We organzed all the desgns nto ten groups by smlartes of ther applcatons and smlarty n ther type of datapath and nterconnect requrements. The smallest group conssted of fve desgns and the largest contaned ten desgns. For all desgns we assumed the total number of avalable layers was ten and that each metal layer can be used to mplement at most fve global nterconnect between dfferent functonal unts. In all examples, the datapath conssted of eght unts. Table 3 shows characterstcs of the desgns when mplemented usng the tradtonal ASIC where each desgn s mplemented separately and after applcaton of the new flexble ASIC desgn methodology and platform. The frst column ndcates whch desgns were consdered for smultaneous mplementaton on a sngle platform usng the flexble ASIC methodology. The second column shows the total number of layers requred for all desgn when the tradtonal ASIC approach s used. The fourth column ndcates the number of customzed layers used by the flexble ASIC approach. The next two columns show the total number of layers requred by the flexble ASIC approach and the total reducton n percentage of layers requred for mplementaton. The last three columns are used to estmate the economc advantage of flexble ASIC under the assumpton that the cost of a layer s $100,000 and that the manufacturng cost for each type of desgn n $1M. Note that the reducton n number of layers s equvalent to the reducton n NRE cost. The average NRE cost was reduced by 74% and the average overall cost reducton by 34%. Note that n all cases, the cost reducton ncreases as the number of desgns targeted to share the common bottom layers ncreases. 6. CONCLUSION In order to reduce NRE cost and enhance the applcablty of ASIC mplementaton platforms, we ntroduced a common bottom - customzed top layers flexble ASIC approach. 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