Power-Aware Mapping for Network-on-Chip Architectures under Bandwidth and Latency Constraints

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1 Power-Aware Mappng for Network-on-Chp Archtectures under Bandwdth and Latency Constrants Xaohang Wang 1,2, Me Yang 2, Yngtao Jang 2, and Peng Lu 1 1 Department of Informaton Scence and Electronc Engneerng, Zheang Unversty, Hangzhou, Chna, Department of Electrcal and Computer Engneerng, Unversty of Nevada, Las Vegas, Las Vegas, NV Emals: 1 bakena@yahoo.com.cn, lupeng@see.zu.edu.cn, 2 meyang, yngtao@egr.unlv.edu Abstract Ths paper nvestgates the bandwdth- and latencyconstraned IP mappng problem that maps a gven set of IP cores onto the tles of a mesh-based Network-on-Chp (NoC archtecture to mnmze the power consumpton due to ntercore communcatons. By examnng varous applcatons communcaton characterstcs shown n ther communcaton trace graphs, two dstngushable connectvty templates are realzed: the graphs wth tghtly coupled vertces and those wth dstrbuted vertces. Dfferent mappng heurstcs are developed for these templates: tghtly coupled vertces are mapped onto tles that are close to each other whle the dstrbuted vertces are mapped followng a graph partton scheme. The proposed template-based mappng algorthm acheves on average 15% power savng compared wth MOCA, a fast greedy-based algorthm. Compared wth a branch-and-bound algorthm, the proposed algorthm can generate results of almost the same qualty but requre much less CPU tme. Keywords-Network-on-Chp (NoC; power-aware; IP mappng; Template-based Effcent Mappng (TEM. I. INTRODUCTION Wth the contnuous scalng of CMOS technologes, nterconnects domnate both performance and power dsspaton n future System-on-Chp (SoC desgns. Multprocessor System on Chp (MPSoC [2] desgns have emerged and shown to delver hgh performance yet reasonably low power consumpton. Networks-on-chp (NoC has been consdered as a vable communcaton nfrastructure n MPSoC [9]. Regular mesh remans the domnant NoC archtecture of choce due to ts dstnct features: structured network wrng, modularty, and standard nterfaces [8]. Ths paper focuses on mappng the IP cores onto a regular tle-based NoC archtecture and the mappng s subected to the latency and bandwdth constrants as mposed by many real-tme multmeda applcatons. In the lterature, a number of algorthms have been proposed to solve ths IP mappng problem, and they fall nto four general categores: Branch-and-bound algorthms [8], whch can generate very hgh qualty results. Wth large queue sze, however, ths algorthm demands hgh memory depth and suffers from long CPU tme. Framework-based approaches, such as the ones usng smulated annealng (SA/genetcs algorthm (GA/tabu search (TS [1, 6, 10, 11]. These algorthms typcally requre consderably longer tme than a greedy-based mappng algorthm. Lnear programmng based schemes [13]. Computaton s tme-consumng and there s no guarantee that hghqualty solutons can be always found. Greedy-based heurstcs [5, 12, 15], whch requre sgnfcantly low CPU tme. The followng greedy algorthms are based on dfferent observatons. The algorthm MOCA [15] acheves a sound balance between the run tme and the qualty of solutons. The problem of ths algorthm s that the graph partton algorthm may separate some tghtly coupled regons (.e. the regons made of IP cores wth large degrees and strongly connected nto dfferent sets, makng the vertces n a tghtly coupled regon adversely mapped onto tles physcally far apart. Partcularly, the power performance of MOCA deterorates drastcally when latency constrants are appled. In ths paper, we propose a Template-based Effcent Mappng (TEM algorthm whch generates hgh-qualty mappng results wth low run tme. Ths algorthm s desgned based on two dstngushable connectvty templates extracted from varous applcatons communcaton trace graphs: the graphs wth tghtly coupled vertces and those wth dstrbuted vertces. Correspondngly, dfferent mappng strateges are proposed for these two templates. Smulaton results show that the proposed TEM algorthm acheves better result than MOCA [15]. The rest of the paper s organzed as follows. Secton II formally defnes the mappng problem. Secton III ntroduces the two templates derved from varous applcatons communcaton trace graphs. The mappng algorthm based on the two templates s presented n Secton IV. Secton V presents and dscusses the smulaton results, and fnally, Secton VI concludes the paper. Ths work s n part supported by NSF under grant no. ECCS and NSF of Chna under grant no

2 II. PROBLEM FORMULATION A. Archtecture descrpton and power model Wthout loss of generalty, the NoC system under consderaton s composed of NxN tles nterconnected by a 2- D mesh network. The power model used n [8] s followed n ths study. The average power consumpton for sendng one bt of data from tle t to tle t can be represented as t, t E bt = ηhops ESbt + ( ηhops 1 ELbt (2 where η hops s the number of routers traversed from tle t to tle t, E Sbt s the power consumed by the swtch, and E Lbt s the power consumed on the lnks between tles t and t. B. Problem Descrpton We assume that before IP mappng s performed, a gven applcaton descrbed by a set of concurrent tasks s already bounded and scheduled onto a lst of selected IP cores. As defned below, the communcaton patterns between any par of IP cores of an applcaton are descrbed by ts Communcaton Trace Graph, whereas the NoC archtecture s modeled by ts Archtecture Characterzaton Graph. Defnton 1 A Communcaton Trace Graph (CTG G=(P, E s an undrected graph, where a vertex/node p k P represents an IP core (a processor, an ASIC devce or a memory unt, etc., and an edge e =(p k, p E represents the communcaton trace between vertces p k and p. For each edge e, ω(e defnes the communcaton bandwdth request between vertces p and p gven n bts per second (bps. ω(e sets the mnmum bandwdth that should be allocated by the network n order to meet the performance constrants. σ(e represents the latency constrant, whch s gven n number of hops nstead of an absolute number n cycles [15]. W(e represents the weght of edge e. The weght s defned n the same way as that n [15]. Among all the traces n the graph, let e be the trace wth the hghest bandwdth requrement, and e be the trace wth the tghtest (lowest latency constrant. An nteger K s defned as the mnmum value requred to ensure that ω( e ω( e among all the traces n the graph,. Once K K σ( e σ( e K s determned, each edge s assgned a weght ω( e We= (. σ ( e K Defnton 2 An Archtecture Characterzaton Graph (ACG Ğ=(T, L s an undrected graph, where each vertex t T represents a tle and each edge l L=(t k, t represents the lnk between tles t k and t. For each lnk l, bw(l defnes the bandwdth provded between tles t k and t. c(l defnes the lnk cost of l,.e., power consumpton for transmttng one bt data from t k to t. In ths paper, we focus on regular NoC archtectures whch have bw(l =B, c(l = C for each l L, where B and C are constants. h k, s the set of lnks formng one of the shortest paths from tle t k to tle t (h k, L. dst(h k, determnes the number of elements n h k, (.e. t s the hop count of the shortest path between tle t k and tle t. Defnton 3 A mappng algorthm M: P T maps each vertex n CTG onto an avalable tle n ACG. M(p represents the mapped tle n ACG, where p P and M(p T. Defnton 4 A routng algorthm R: E H, fnds one of the shortest routng path between M(p k and M(p for each edge e =(p k, p E. The lnks of formng ths path belongs to set h M ( pk, M( p. The IP mappng problem s formulated as follows. Gven a CTG(P, E representng the communcaton pattern of an applcaton and an ACG(T, L representng the target NoC archtecture, where P T, fnd a mappng M:P T whch maps all the vertces n CTG onto avalable tles n ACG and generates a deadlock-free and mnmal routng paths for all edges n CTG, such that the total power consumpton s mnmzed,.e., satsfyng E hm ( p, M ( p k (3 Mn ω( e C = 0 m= 0 e= ( pk, p E lm hm ( pk, M ( p p P, M( p, p P and p T, (4 p p, M( p M( p, (5 ω( e f( l, hm p M p (6 l, B (, ( e= ( pk, p e =(p k, p, σ ( e dst ( h M( p, ( k M p (7 1 f l h M( pk, M( p where f( l, h M( p, ( k M p = 0 f l h M ( pk, M ( p Smlar to the defnton adopted n [8], condtons gven by (4 and (5 ensure that each IP should be mapped exactly to one tle and no tle can host more than one IP. Eqn. (6 specfes the bandwdth constrant for every lnk set by the communcaton bandwdth requrement, and Eqn. (7 ensures that the latency constrant (n terms of the number of hops between two communcatng IPs s satsfed on the mapped tles. III. DERIVATION OF MAPPING TEMPLATES As alluded n Secton 1, MOCA [15] does not perform well when the latency constrants are consdered. Ths problem s llustrated n the mappng of the MPEG4 decoder, wth ts CTG shown n Fgure 1. k

3 Fgure 1 The CTG of MPEG4 decoder [15]. The BW request (Mbps and latency constrant (number of hops of each edge s labeled on the edge. A communcaton path wth hgher bandwdth request should be mapped to lnks wth fewer hop counts to reduce power consumpton as Eqn. (3 ndcates. When the latency constrant s appled, the result of MOCA deterorates. For example, n Fgure 2(a, the hop counts of edges (1,7, (8,9, (8,10 are greater than 1, whch results n hgher power consumpton. As a matter of fact, as shown n Fgure 2(b, there s a better mappng by reducng the number of hops for these edges. In Fgure 1, vertces 1 and 8 have many edges requestng hgh bandwdths or tght latency. In Fgure 2(b, these two vertces are mapped onto the two tles wth the largest degree or maxmal number of neghbor tles (.e., 4. In ths soluton, edges wth hgher weghts are mapped wth fewer hop counts than those edges wth smaller weghts. (a (b Fgure 2 (a The mappng result of MOCA on the CTG of MPEG4dec w/ latency constrants (b A better mappng soluton on the same CTG w/ latency constrant. The square boxes are tles and the crcles are IP cores. From the above example, one can see that dfferent mappng strateges shall be adopted for CTGs wth dfferent features. Here, we present two dstnct templates derved from varous CTGs. Gven a CTG(P, E, and a sorted lst of edges n decreasng order of edge weght denoted as Ê: Defnton 5 A vertex p P s a hot node f a p has a degree greater than or equal to 4, and b of the frst 50% edges n the edge lst Ê, there are at least one edges that are connected to p. Template 1: An applcaton s CTG falls nto Template 1 (tghtly coupled f there s at least one hot node n the CTG. Template 2: An applcaton falls nto Template 2 (dstrbuted f there s no hot node n the applcaton s CTG. IV. ALGORITHM DESCRIPTION The overall structure of the TEM algorthm s shown below. Before the template-based mappng takes place, the edges have to be sorted n non-ncreasng order n terms of the edge weght. After all the vertces are mapped, a routng allocaton routne s called to fnd routng paths for all pars of communcatng vertces. TEM (G(P,E, Ğ(T,L Input: (1 G: CTG of an applcaton. (2 Ğ: ACG of an NoC archtecture Functon: Map the applcaton on the NoC archtecture and allocate routng paths Sort_Edge(E; // E G. Let the sorted lst be Ê =e π(1, e π(2,,e π( E,.e., // W(e π(1 W(e π(2 W(e π(( E. // Fnd the hot nodes f any. Check whch template the applcaton belongs to for each vertex p // Defnton 5 f (vertex p has degree α and p has γ edges n the frst β edges n E mark p as a hot node an place nto set Ĥ // If G has hot nodes, t belongs to Template 1, otherwse Template 2 // Template specfc algorthm case 1: Template 1 // Tghtly coupled TEM_Template1(G, Ğ, Ĥ; break; case 2: Template 2 // Dstrbuted TEM_Template2(G, Ğ; break; Route_Alloc(G, Ğ; // Fnd routng paths A. Mappng Algorthm for Template 1 An applcaton of template 1 (CTG has at least one hot node s mapped based on the followng observatons. a Hot nodes should be gven a hgher mappng prorty; that s, they shall be mapped before any other nodes are mapped. All the hot nodes n a CTG wll be frst mapped along wth ther α most sgnfcant neghbor vertces. A hot node s better mapped onto a tle n an NoC that has the maxmum number of neghbor tles. b Once all the hot nodes are mapped, the mappng sequence of remanng unmapped non-hot nodes wll be performed based on the decreasng order of weght of edges connectng them. As such, TEM_Template1 procedure conssts of two maor steps: (1 map hot nodes n CTG, (2 map other vertces. TEM_Template1 (G(P,E, Ğ(T,L, Ĥ Input: (1 G: CTG of an applcaton (2 Ğ: ACG of an NoC archtecture (3 Ĥ: The set of hot nodes Functon: Map the Template 1 applcaton onto the NoC archtecture // Step 1: fnd and map the hot nodes wth ther 4 most sgnfcant // neghbors for each edge e π(=(p k, p ncrease the counter of p k,, p f they are hot nodes (belong to Ĥ f one of the vertex s counter equals α // suppose p k s counter s α Map_Hot_Node(p k, Ê, T; // Step 2: map the remanng unmapped vertces update the hop counts of edges whose termnal vertces are already mapped; // re-scan the edge lst for each edge e π(=(p k, p Map_Edge(e π(, Ê, T; // T s the avalable tle set

4 Before we dscuss each step n detal, the followng defntons are ntroduced. Defnton 6 Vertex p n s a sgnfcant neghbor of vertex p f there exsts an edge (p, p n E and edge (p, p n s wthn the frst 50% edges n the edge lst Ê. Defnton 7 Snce n a mesh structure, the maxmal degree of a tle s four, here the four most sgnfcant neghbors p n1,, p n4 of a hot node p are the four neghbors of p that have the hghest bandwdth/tghtest latency requrements among all the neghbors of p. Defnton 8 A center tle n a 2-D topology lke mesh s a tle that has maxmal number (.e. 4 of unmapped neghbor tles. Defnton 9 Two vertces p k, p are close f (1 edge (p k, p s among the frst 50% edges n the edge lst or (2 a neghbor vertex of p k (or p s connected wth p (or p k, and ths edge s among the frst 50% edges n the edge lst. 1 Map hot nodes. Procedure Map_Hot_Node maps each hot node and ts four most sgnfcant neghbor vertces. Each hot node p s assocated wth a counter ctr that counts the number of tmes that vertex p appears as a termnal vertex of the edges n the sorted edge lst. Case 1: the current hot node p s not mapped yet. Check whether ths hot node s close (Defnton 9 to any of those mapped hot nodes. If yes, ths hot node s mapped to a tle wth mnmum hops to an already mapped hot node. Otherwse, a center tle s selected and t s allocated to ths hot node. Next ts four most sgnfcant neghbors are mapped to the neghborng tles f they have not been mapped. Case 2: the current hot node has already been mapped because t belongs to the frst α neghbors of a prevously mapped hot node. In ths case, only the four most sgnfcant neghbor vertces need to be mapped. The procedure Improve_Edge can be called for optmzaton. 2 Map other nodes. In ths step, all the remanng unmapped vertces are mapped. Procedure Map_Edge maps the remanng unmapped vertex/vertces. There are three cases to consder. Case 1: Nether of the two termnal vertces p k, p of edge e π( = (p k, p s mapped. Search the edges from e π(+1 to e π( E. If one of the neghbors of the two termnal vertces s found and s mapped, then the vertex wth a mapped neghbor s mapped onto a tle that has the mnmum hop count to ts mapped neghbor. On the other hand, f none of the two termnal vertces neghbors s mapped, an avalable tle s selected and mmedately allocated to one of the vertces, after whch the other vertex s mapped onto a tle wth a mnmum hop count to the ust mapped tle. Case 2: One of the two termnal vertces s mapped, but the other one s not. In ths case, only the unmapped vertex needs to be mapped onto a tle wth mnmum hop count to the mapped tle. The Map_Hot_Node procedure s lsted below Map_Hot_Node(p h, Ê, T Input: (1 p h: A hot node (2 Ê: The sorted edge lst (3 T: The avalable tle set n NoC archtecture Functon: Map hot node p h and ts neghbors // Case 1 f (p h s unmapped // 1 Map the hot node p h check f other mapped hot nodes are close to p h ; // Defnton 9 f (there s a mapped hot node p hk close to hot node p h map p h to a tle wth mnmum hop count to p h s tle; else map p h to t l = Fnd_Center_Tle(; // 2 Map the four most sgnfcant neghbors for each of p h s four most sgnfcant neghbors // suppose p n s one of such neghbors f (p n s unmapped // Two crtera should be observed n mappng neghbors as // descrbed n text map p n to a tle wth mnmum hops to p h s tle; // Case 2 else f (p h s mapped for each of p h s four most sgnfcant neghbors // suppose p n s one of such neghbors f (p n s not mapped map p n to a tle wth mnmum hop count to p h s tle ; Fgure 2(b shows the mappng result of the CTG of MPEG4 decoder. The complexty of TEM_Template1 s O( Ĥ ( E + T + E ( E + T, whch can be further smplfed as O(( E + T 2 snce Ĥ P T. B. TEM Algorthm for Template 2 For a Template 2 CTG, the graph partton algorthm proposed n [4] s followed to partton both CTG and ACG nto four smaller regons so that each regon n CTG can be mapped onto a regon n ACG n a dvde-and-conquer manner. Defnton 10 A Block Trace Graph (BTG s denoted as G'=(B, BE, where each vertex b B s a parttoned block and b P (P s the vertex set of CTG(P, E, and an edge be =(b k, b BE exsts f p kl b k and p m b, (p kl, p m E. For an edge be =(b k, b BE, W(be represents the weght of be. The calculaton s the same as the weght of edges n CTG. An CTG edge (p, p E belongs to a block b k f p b k or p b k. E represents the set of edges belongng to b. The vertces n each block are classfed nto two types and they are mapped dfferently: 1 Internal vertces. An nternal vertex p ntern has all ts neghbors n the same block of p ntern. 2 External vertces. An external vertex p extern has at least one of ts neghbors not n the same block of p extern. Defnton 11 A Vrtual ACG (VACG s denoted as Ğ'=(R, CH, where a vertex r R represents a parttoned regon and r T (T s the tle set of ACG(T, L. Each edge ch =(r k,

5 r CH represents that there exsts drect lnks between tles n r k and r. For each edge ch CH, The TEM_Template 2 algorthm works as follows. TEM_Template2(G(P,E, Ğ(T,L Input: (1 G: The CTG of an applcaton. (2 Ğ: The ACG of an NoC archtecture Functon: Map the Template 2 applcaton onto the NoC archtecture // Step 1. Obtan the BTG and VACG by parttonng the CTG nto blocks // and ACG nto default regons, respectvely. Map the blocks n BTG to // the regons n VACG. obtan BTG (G' usng the graph partton algorthm to partton CTG nto 4 blocks; obtan VACG (Ğ' wth default four square regons; map the four blocks n BTG to four default regons of VACG usng Map_Edge; Partton_VACG(G', Ğ'; // Step 2. Insde each block, map the vertces to the tles of the // correspondng regon. for each block b n BTG mapped to regon r x n VACG // 1 Map the external vertces. // Let PE be set of external vertces n b ; sort external vertces n PE n the non-ncreasng order of the total weght of the external vertces. Let p Φ(1, p Φ (2,, p Φ ( PE be the sorted lst; for each external vertex p Φ( Map_External_Vertex(p Φ(, G', Ğ'; // 2 Map the nternal vertces sort the edges n b nto Ê usng Sort_Edge; for each edge e ψ ( = (p k, p Ê Map_Edge (e ψ(, b, r x; // descrbed n Secton Partton. In ths step, the BTG s formed usng a graph partton algorthm [4] to partton the CTG nto four blocks. The VACG s formed by parttonng the ACG nto four default regons (e.g., square regons n Fgure 4. The blocks n the BTG are mapped to the default regons n the VACG. Based on the mappng result of BTG onto VACG, the actual regons n the VACG are parttoned n a top-down manner. The sze of each parttoned regon needs to be set equal to the sze of the correspondng block n the BTG. 2 Map nsde blocks. In ths step, the vertces n each block are mapped to the tles wthn ts regon. The external vertces are frst mapped to the border of each NoC regon, after whch the nternal vertces are mapped wth larger weght edge frst crteron. The overall complexty of TEM_Template2 can be approxmated by O(( E + T 2 as blk < P T, E < E, T < T. V. PERFORMANCE EVALUATION To evaluate the performance of the TEM algorthm, both TEM_Template 1 and TEM_Template2 are mplemented and smulated. The brand-and-bound (BNB [8] and MOCA [15] algorthms are also mplemented and the mappng results of all three algorthms are compared. To solate the effects of dfferent routng algorthms, the XY routng and odd-even routng algorthms are selected. Multmeda benchmarks from [7] and [15]. The Noxm smulator [14] s modfed and used n our smulatons to obtan the total communcaton power after the mappng and the routng path allocaton steps. The smulatons are performed on a PC wth one Intel Core2 P GHz processor and 2GB RAM. The run tmes of both TEM and MOCA range from 0.01sec~1sec for dfferent network szes. Multmeda benchmarks of both Template 1 and Template 2 are tested on a mesh-based NoC. Table I lsts these benchmarks. For benchmarks of both templates, we compare the degradaton of TEM compared to BNB (.e. the ncrease n power consumpton of mappng results from the TEM compared to that from BNB and the degradaton of MOCA compared to BNB. The power consumpton s normalzed. TABLE I. MULTIMEDIA BENCHMARKS AND THEIR TEMPLATES. Benchmark Template MPEG enc 1 263enc+MP3enc 1 263enc+MP3dec 1 263enc+263dec 1 Multmeda Systems (MMS 1 VOPD 2 MP3enc 2 MP3enc+MP3dec 2 Table II shows the result of benchmarks of Template 1 wth and wthout latency constrants. When the latency constrants are not consdered, the result of TEM s comparable wth that of MOCA. When the latency constrants are consdered, the TEM algorthm outperforms MOCA for most meda programs. The degradaton of TEM vs. BNB s wthn 10% wth odd-even routng. The reducton n power consumpton of TEM compared to MOCA s over 15%. For MPEG4dec, the degradaton of TEM s only 6% compared to that of MOCA 45%. The Mult-Meda System (MMS benchmark [8] s also smulated on a 5x5 mesh-based NoC. Table III shows the reducton n power consumpton of TEM over MOCA (normalzed. Table IV shows the result of benchmarks of Template 2 wth and wthout latency constrants. Wthout latency constrants, the result of TEM s comparable wth that of MOCA. On average, the degradaton of TEM over BNB s wthn 10% for both XY routng and odd-even routng. Wth latency constrants, the power consumpton of mappng result from TEM s slghtly lower than that from MOCA for VOPD and MP3enc. For MP3enc+MP3dec, TEM acheves sgnfcant reducton n power consumpton compared to MOCA. Ths s due to the fact that the TEM algorthm for applcatons of Template 2 uses a dvde-and-conquer approach. Insde each parttoned block, TEM frst maps external vertces to the border of the block and the remanng edges wth larger weght frst crteron. Thus larger weght edges are mapped frst nsde each block. Evaluaton of TEM on random applcatons s also conducted. Detaled results are presented n [16].

6 TABLE II. COMPARISON OF POWER CONSUMPTION (NORMALIZED OF TEM AND MOCA OVER BNB ON BENCHMARKS OF TEMPLATE 1. Benchmarks Wth latency constrant Wthout latency constrant TEM MOCA BNB TEM MOCA BNB XY Odd-even XY Odd-even MPEG enc enc+MP3enc enc+MP3dec enc+263dec TABLE III. COMPARISON OF POWER CONSUMPTION (NORMALIZED OF TEM OVER MOCA ON MMS (TEMPLATE 1. Benchmarks Wth latency constrant Wthout latency constrant TEM MOCA TEM MOCA XY Odd-even XY Odd-even MMS TABLE IV. COMPARISON OF POWER CONSUMPTION (NORMALIZED TEM AND MOCA OVER BNB ON BENCHMARKS OF TEMPLATE 2. Benchmarks Wth latency constrant Wthout latency constrant TEM MOCA BNB TEM MOCA BNB XY Odd-even XY Odd-even VOPD MP3enc MP3enc+MP3dec VI. CONCLUSION Ths paper presented a template-based greedy algorthm to address the IP mappng problem under the bandwdth and latency constrants. An applcaton falls nto Template 1, f there are one or more hot nodes whch demand ether hgher communcatons bandwdths or tghter latency. In ths case, TEM maps the hot nodes frst along wth ther four most sgnfcant neghbors, after whch the remanng IP cores are mapped n descendng order based on the edge weghts. On the other hand, an applcaton s categorzed as Template 2, f the communcatons are nearly evenly dstrbuted among the vertces. In ths case, TEM dvdes the NoC nto regons and CTG nto blocks; then t maps the IP cores nsde each block n a dvde-and-conquer manner. The experments on multmeda and random benchmarks show that TEM generates hgh qualty mappng results wth low run tmes. VII. REFERENCES [1] G. Asca, V. Catana, and M. Pales, "Mult-obectve mappng for meshbased NoC archtectures," n Proc. 2nd IEEE/ACM/IFIP Int'l Conf Hardware/Software Codesgn and System Synthess, 2004, pp [2] D. Bertozz, A. Jalabert, S. Mural, R. Tamhankar, S. Stergou, L. Benn, and G. De Mchel, "NoC synthess flow for customzed doman specfc multprocessor Systems-on-Chp," IEEE Trans. Parallel And Dstrbuted Systems, pp , [3] R. P. Dck, D. L. Rhodes, and W. Wolf, "TGFF: task graphs for free," n Proc. 6th Int'l workshop on Hardware/software Codesgn, 1998, pp [4] C. M. Fducca and R. M. Mattheyses, "A Lnear-tme heurstc for mprovng network parttons," n Proc. 19th IEEE Conf. Desgn Automaton, 1982, pp [5] A. Hansson, K. Goossens, and A. Rǎ dulescu, "A unfed approach to constraned mappng and routng on network-on-chp archtectures," n Proc. 3rd IEEE/ACM/IFIP Int'l Conf Hardware/Software Codesgn and System Synthess, 2005, pp [6] H. M. Harmanan and R. Farah, "A method for effcent mappng and relable routng for NoC archtectures wth mnmum bandwdth and area," n Proc. Conf. Crcuts and Systems and TAISA, 2008, pp [7] J. Hu and R. Marculescu, "Energy-aware mappng for tle-based NoC archtectures under performance constrants," n Proc Conf. Asa South Pacfc Desgn Automaton, 2003, pp [8] J. Hu and R. Marculescu, "Energy-and performance-aware mappng for regular NoC archtectures," IEEE Trans. Computer-Aded Desgn of Integrated Crcuts and Systems, vol. 24, pp , [9] A. Jantsch and H. Tenhunen, Networks on Chp. New York, NY: Kluwer Academc Publshers, [10] Z. Lu, L. Xa, and A. Jantsch, "Cluster-based smulated annealng for mappng cores onto 2D mesh networks on chp," n Proc. Desgn and Dagnostcs of Electronc Crcuts and Systems (DDECS, 2008, pp [11] C. A. M. Marcon, E. I. Moreno, N. L. V. Calazans, and F. G. Moraes, "Evaluaton of algorthms for low energy mappng onto NoCs," n Proc. IEEE Int'l Symp. Crcuts and Systems(ISCAS, 2007, pp [12] A. Mehran, S. Saed, A. Khademzadeh, and A. Afzal-Kusha, "Spral: a heurstc mappng algorthm for network on chp," J. IEICE Electroncs Express, vol. 4, pp , [13] S. Mural and G. De Mchel, "Bandwdth-constraned mappng of cores onto NoC archtectures," n Proc. Desgn, Automaton and Test n Europe Conference and Exhbton (DATE, 2004, pp [14] Noxm, Avalable at: [15] K. Srnvasan and K. S. Chatha, "A technque for low energy mappng and routng n network-on-chp archtectures," n Proc Int'l Symp. Low Power Electroncs and Desgn, 2005, pp [16] X. Wang, M. Yang, Y. Jang and P. Lu, "A power-aware mappng approach to map IP cores onto NoCs under bandwdth and latency constrants," to appear n ACM Trans. Archtecture and Code Optmzaton.