A Dual-MST Approach for Clock Network Synthesis

Transcription

1 A Dual-MST Approach for Clock Network Synthess Jngwe Lu Wng-Ka Chow Chu-Wng Sham Evangelne F.Y. Young Electronc and Electronc and Electronc and Computer Scence Informaton Engneerng Informaton Engneerng Informaton Engneerng and Engneerng The Hong Kong The Hong Kong The Hong Kong The Chnese Polytechnc Unversty Polytechnc Unversty Polytechnc Unversty Unversty of Hong Kong Abstract In nanometer-scale VLSI physcal desgn, clock network becomes a major concern on determnng the total performance of dgtal crcut. Clock skew and PVT (Process, Voltage and Temperature) varatons contrbute a lot to ts behavor. Prevous works manly focused on skew and wrelength mnmzaton. It may lead to negatve nfluence towards these process varaton factors. In ths paper, a novel clock network syntheszer s proposed and several algorthms are ntroduced for performance mprovement. A dual-mst (DMST) geometrc matchng approach s proposed for topology constructon. It can help balancng the tree structure to reduce the varaton effect. A recursve buffer nserton technque and a blockage handlng method are also presented, and they are developed for proper dstrbuton of buffers and savng of capactance. Expermental results show that our matchng approach s better than the tradtonal methods, and n partcular our syntheszer has better performance compared to the results of the wnner n the ISPD 2009 contest. I. INTRODUCTION In the procedure of VLSI desgn, the dstrbuton and placement of clock nets play an mportant role. Wth the contnuous reducton of transstor sze, the sgnal delay of nterconnecton becomes a domnant factor compared wth nternal delays of logc cells and macro cells. In modern synchronous dgtal devces, system performance s greatly determned by crcut phase delay, clock skew and PVT varatons. It s thus necessary to pay more attenton to clock network synthess (CNS) from the very begnnng of the physcal desgn stage. Clock skew represents the tmng varaton of dfferent termnals n the clock net. In order to synchronze one crcut, each termnal or snk must be reached wthn a specfed small tme range. Otherwse, the extent of synchronzaton would become unacceptable. There were plenty of researches focusng on clock skew mnmzaton. Some earler proposed works concentrated on the dstrbuton of wrelengths between source and termnals to acheve delay equalzaton. Jackson [1] frstly presented a clock routng algorthm based on a suboptmal equdstant network wth recursve horzontal-vertcal parttonng. Later, more mprovements were made to reach exact equdstant tree [2] for clock net, and a pathlength skew balancng approach s proposed n [3]. Afterwards, delay balancng usng Elmore delay model [4] became prevalent to acqure more accurate nformaton on tme delay. Clock network wth exact zero skew [5] s proposed by applyng balancng method based on the Elmore model. Chao [6] used segment nstead of pont to represent the set of best mergng locatons and deferred embeddng s appled to reduce the total wrelength. Edahro mentoned n hs work [7] that unbalanced trees would have shorter total wrelength. To supply suffcent drvng power, buffer nserton s also commonly nvolved, especally n multlevel networks [8, 9]. Recently, process varaton becomes a focus of attenton besdes the skew and clock delay problems. It s manly due to the uncertanty of varous factors nsde a crcut, such as process [10], voltage and temperature [11]. In order to keep a chp stable and functonng well, methods wth better adaptablty are wdely favored. Many researchers focused on robust algorthms for varaton mnmzaton. Technques such as wre szng [12], buffer szng [13] and lnk nserton [14, 15] are appled. Other researchers proposed related works on chplevel synthess [16] and logc gates matchng [17], etc. In ISPD 2009 [18], a CNS contest was held n whch a process varaton related objectve, called Clock Latency Range (CLR), was formulated and several benchmarks were released, and ths brought n more research nterests on ths CNS problem and ncreased the comparablty of dfferent works on the varaton factor. In ths paper, we propose a new clock network syntheszer. Some heurstcs are proposed to optmze CLR as well as clock skew and wrelength. It contans three man features: (1) An approach to construct dual-mst (DMST) for geometrc matchng. (2) A recursve buffer nserton technque for drvng power afford and capactance reducton. (3) A blockage handler to deal wth buffer locaton volaton. The remander of ths paper s organzed as follows. Secton II ncludes the problem formulaton. Secton III s composed of our three man contrbutons, topology constructon, buffer nserton and blockage handlng. In secton IV, we present our results based on the ISPD09 benchmarks. Fnally, we gve our concluson n secton V. II. PROBLEM FORMULATION VLSI physcal desgn can be bascally dvded nto two stages: placement and routng. After placement, all the clock pns are fxed, ncludng the source and a set of termnals. Because of the mportance of clock synchronzaton, CNS s usually performed before routng other nets. Hence, wre resources are fully avalable for the clock nets to utlze all over the cr /10/$ IEEE 467

2 Notaton Descrpton C s clock skew of a clock network S a set of snks s the th snk n S d s delay of snk s D b buffer delay D w wre delay C d downstream capactance C b nput capactance of a buffer d b nternal delay of a buffer R b output resstance of a buffer R w resstance of a wre C w capactance of a wre ρ R unt resstance of a wre ρ C unt capactance of a wre N a set of nodes at the th teraton n j the jth node at the th teraton M matchng result of the th teraton c j,k the cost of the jth and kth nodes ds(, ) Manhattan dstance between and C n1,c n2 downstream capactance of and D n1,d n2 accumulated subtree delays of and TABLE I NOTATIONS. cut. Detaled nformaton of the defntons below can be found n the ISPD 2009 Contest webste [18]. A. Clock Slew Rate The restrcton on clock slew descrbes the requrement on the rsng and fallng sgnal rate, so as to mantan the sgnal ntegralty. It s defned to be the lastng tme from 10% to 90% of the sgnal strength, and the upper lmt s assumed to be 100ps. Durng the smulaton of CNS, t s necessary to mantan the sgnal rsng tme under ths upper lmt throughout the whole clock network. B. Clock Skew The skew of a clock network means the dfference of the source-to-snk delay among all the snks. S s used to denote the set of snks whch s {s 1,...,s S }. d s represents the nternal delay between the source and the snk s. To mnmze the skew, we need to buld a clock network wth all d s as close as to each other as possble. Notce that the skew s not determned by the average delay of the snks, but by the dfference between the maxmum and the mnmum. The equaton for clock skew (C s ) calculaton s shown below. C. CLR C s =max{d s s S} mn{d s s S} Owng to the uncertanty of the manufacturng process, there may be voltage uncertanty at each drvng node. The suppled voltage at each drvng node may vary from V dd1 to V dd2.ths wll affect the accuracy of the buffer delay calculaton. SPICE smulatons wth these two dfferent voltage sources V dd1 and V dd2 are used n ths case to smulate the voltage uncertanty. CLR s the man crteron for evaluaton. It s determned by the dfference between the maxmal and mnmal clock skew values under the two gven voltage sources. p 1max =max{d s s S, V dd1 } p 1mn =mn{d s s S, V dd1 } p 2max =max{d s s S, V dd2 } p 2mn =mn{d s s S, V dd2 } CLR =max{p 1max,p 2max } mn{p 1mn,p 2mn } From the above equatons, we can see that CLR, to a certan extent, represents both the pure clock skew and the clock skew due to voltage varaton. We wll use t together wth the pure clock skew for CNS performance evaluaton. D. Resources of Wres and Buffers We assume two types of buffers and two types of wres. The unt capactance and resstance cost of wres are predefned as ρ C and ρ R. The two types of buffers are both nverted, so the sgns of the two sgnals at a mergng pont should be the same. The upper lmt of the total capactance s also set to lmt the total power consumpton. In the rest of ths paper, we wll use party check of the number of downstream buffer levels to represent sgnal sgn check. We wll also use the capactance cost to represent the power usage of the network. Based on the buffer and wre types, we construct a lookup table for slew checkng. We run SPICE smulatons to fnd out the maxmum dstance between two successve buffers wth one specfed wre type n order not to volate the slew constrant. These two successve buffers may have dfferent szes (dfferent number of buffers connected n parallel). The nput parameters of ths table are the buffer type, the sze of the frst buffer, the sze of the second buffer and the wre type. The output of ths table s the maxmum dstance allowed between these two buffers. The procedure of buffer nserton can be smplfed wth ths look-up table. III. METHODOLOGY In ths paper, we propose two clock network syntheszers applyng our dual-mst for geometrc matchng. DMST s the approach that calculates the delay by Elmore model only. DM- STSS s the approach that also performs SPICE smulatons n order to adjust the locaton of each mergng pont. The desgn flow of these two approaches s shown n fgure 1. Based on the approach of DMST, dual-mst s used frst for geometrc matchng wth the clock termnals. A new recursve buffer nserton method s developed together wth blockage handlng to deal wth the buffer dstrbuton problem for each matchng par. After matchng and buffer nserton, the locatons of the mergng nodes at the bottom level of the tree can be decded. Ths procedure s performed agan wth the mergng nodes nstead of the clock termnals. The locatons of the mergng nodes at the next level can then be decded smlarly. 468

3 A set of clock termnals A set of clock termnals v v 2 0 v1 v 2 L = bottom level A set of nodes v 1 Buffer nserton wth blockage handlng Buldng dual-mst for geometrc matchng Yes No Blockages exst along the paths of edges Recursve buffer nserton L=L-1 A set of nodes at tree level L Buldng clock network wth DMST approach Spce smulaton of the clock network (a) T 1 (b) T 2 Fg. 2. Comparson of (a) an unbalanced tree and (b) a fully-balanced tree. Decdng the mergng nodes based on Elmore delay model (a) DMST approach Adjustng the postons of the mergng nodes at tree level L based on Spce smulaton (b) DMSTSS approach Fg. 1. Desgn flow of (a) DMST approach and (b) DMSTSS approach Ths procedure s performed teratvely untl a clock tree s constructed. For the approach of DMSTSS, SPICE smulaton s appled. A clock network s bult frst accordng to the approach of DMST. The computed clock skew at the mergng nodes s zero but the actually clock skew may not be zero based on the SPICE smulaton. Accordng to the smulated clock skew, the locatons of the mergng nodes at the bottom level are adjusted, or some snakng wres are nserted. The clock network s then re-bult based on the mergng nodes at the bottom level nstead of the clock termnals. The clock network wll thus be re-bult at each level untl the locaton of the fnal mergng node at the top level of tree s fxed. DME technque [6] s also appled. Thus, segment s used nstead of ponts to represent the set of best mergng locatons and deferred embeddng s appled to reduce the total wrelength. The total capactance of the ntal clock network s a good ndcaton for buffer szng. To determne the sze of buffer, one ntal tree wthout parallel buffers s frst bult for the estmaton of the total capactance. If the estmated total capactance of the ntal clock network s too small, larger buffers (more buffers connected n parallel) can be nserted. A. Iteratve Geometrc Matchng An teratve geometrc matchng technque s developed for topology constructon. In the th teraton, let N denote the group of nodes, n j denote the jth node, and M denote the matchng result (a specfc defnton of a geometrc matchng of one teraton can be found n [3]). The cost of the mergng of two nodes n j and n k s denoted as f c(n j,n k ), and t s calculated and stored at the begnnng of the th teraton. The Manhattan dstance of two nodes s used as the cost n our mplementaton. The maxmal cost of the th teraton Cmax s denoted as below, and we can get Cmn accordngly. Cmax = max ( {f c n j,n ) ( (n j,n k ) k : n j,n ) k M } Unlke tradtonal matchng algorthms whch focused on wrelength mnmzaton [1, 7], our approach wants to buld a topology whch s close to a fully-balanced tree. In each level, all the connecton paths of a fully-balanced tree have dentcal Manhattan dstance, despte ther correspondng parents and chldren nodes are dfferent. An example s shown n fgure 2. In T 1, {,... } s the group of termnals, and v 1 are the mergng nodes at the frst level and v 2 s the root. The same namng rule s also appled n T 2. In both T 1 and T 2, all the root-to-leaf paths are equdstant, and the total wrelength of T 1 s shorter than that of T 2.However,T 2 s fully-balanced and T 1 s unbalanced wth ds (v 2, ) ds (v 2,v 1 ). Therefore, the clock skew of T 1 s more senstve towards process varaton factors. Meanwhle, the real tme delay s not of lnear relatonshp wth wrelength, and asymmetrc buffer nserton n T 1 wll ncrease the delay varatons. As a matter of fact, fully-balanced trees such as T 2 s preferable n CNS. In our approach, we wll get close to ths target by means of reducng C max. Procedure 1 partton(n ) Requre: N the group of nodes to be merged n the th teraton f N =2then merge ( ) n 1,n 2 else f N 1then return else Buld dual-mst wth N 2 edges nserted. Two groups of nodes N and N are formed respectvely. f N ( s odd ) and N s odd then ( ) n a,n b =arg(n u,n v ) mn{f c n u,n v n u N, n v N } merge ( ) n a,n b remove n a from N remove n b from N end f partton(n ) partton(n ) end f To acheve ths target, a novel method to buld the dual-mst s developed. It s an teratve approach, therefore we only need to descrbe ts functonalty n one teraton. Based on the Kruskal s MST algorthm, our method s made up of a se- 469

4 stage 1 stage 2 a.) L C n1,d n1 C n2,d n2 stage 3 stage 4 b.) C n1,d n1 l d 1 l d 2 n B 1 C n2,d n2 c.) n B 1 stage 5 stage 6 n1 n1 d.) n B 1 Fg. 4. Desgn flow of recursve buffer nserton. Fg. 3. An example of teratve geometrc matchng. quence of recursve bparttonng processes. The detaled descrpton of constructng a dual-mst s shown n procedure 1. Generally, durng the generaton of the Kruskal s MST of N, we only nserted N 2 edges (wthout any cycles nvolved). As a matter of fact, two subtrees N and N are generated to form a bpartton. A specfc case s llustrated n fgure 3, n whch N =6.Lete j,k represent the edge connectng n j and n k. The edges are sorted n ascendng order accordng to ther costs, and n ths case the sorted edge lst would be e 1,3,e 1,2,e 4,5,e 4,6,e 3,4,e 2,3,e 5,6,... At frst, N 2=4edges {e 1,3,e 1,2,e 4,5,e 4,6 } are sequentally added, N = {,, } and N = {,, }.Because N and N are both odd numbers, we contnue to add one more edge from the lst (stll no cycles nvolved), whch s e 3,4. Therefore, and form a match, N = {, } and N = {, }. The bpartton procedure contnues on N and N.Here N = N =2, so the recurson of bpartton s termnated accordng to procedure 1, and two more pars {, }, {, } are formed. Fnally, the matchng result at teraton, M,s{(, ), (, ), (, )} and Cmax s f c (, ). Durng each teraton of the matchng, every node should be pared accordng to our dual-mst algorthm (one node s left when N s odd), so log 2 S teratons are performed. At the th( teraton, the tme complexty of cost calculatons equals O N 2). On average, the number of parttonng ( ) 2 stages s log 2 ( N ), and the complexty s N 2 for the j 1 jth stage. Therefore, the total complexty of the th teraton s stll O ( N 2),and N = S 2. Fnally, the tme complexty on average for the whole geometrc matchng s shown 1 below. log 2 S =1 ( S ) = O ( S 2) Our approach ams at constructng a clock tree topology that s close to a fully-balanced tree. It s only a heurstc wth proxmty to the optmal soluton. Compared to other geometrc matchng methods, ours mght generate longer wre length but would help to boost the performance of the clock net. Specfc comparson can be found n the secton of the expermental results. B. Recursve Buffer Inserton After the step of geometrc matchng, a set of node pars are obtaned. In order to reduce the skew and satsfy the slew lmtaton, the locaton of the mergng pont between a node par should be determned approprately. In addton, buffers are nserted f necessary. Elmore RC model s appled for delay estmaton. The buffer delay and wre delay are computed by D b = d b + R b C d and D w = R w ( 1 2 C ) w + C d respectvely. Real-tme smulaton of sgnal slew rate costs much more tme. Thus, we buld a look-up table (T slew )n advance. Ths table can provde respectve drvng length for dfferent combnatons of buffer and wre types. Reducng the total amount of capactance s also one of our major targets. Our approach s mplemented to cut down the usage of buffer nserton and wre snakng. An example s llustrated n fgure 4 to demonstrate our approach for the constructon of clock network. and are the two nodes to be merged. The dstance between and s denoted by L. Ther downstream capactances and sub-tree delays are denoted by C n1 and C n2,andd n1 and D n2 respectvely. Based on ther downstream capactances and the dfference of ther sub-tree delays, the locaton of the mergng pont, can be determned. The mergng process of these two nodes can be completed f and only f both of the followng two condtons are satsfed: (1) A buffer at can drve and drectly wthout causng any slew volaton. In fgure 4a, f a buffer s nserted at, the correspondng drvng capactance should be C n1 + C n2 + L ρ C. If the drvng capactance s larger than the value obtaned from the look-up table (T slew ), the clock slew wll be larger than the lmtaton. (2) The partes of downstream buffer levels of and are the same. Whle any of these two condtons s not satsfed, a recursve buffer nserton technque s appled. Whle ether one condton s not satsfed, buffer nserton should be performed. We assume that the dstance between the mergng node and s X 1. The dstance between and s X 2. The maxmal drvng length of and are 470

5 denoted by l1 d and ld 2 respectvely. The maxmal drvng length means that f a buffer s nserted further away from l1 d or l2,the d correspondng clock slew wll be larger than the lmtaton. If X 1 l1 d s greater than X 2 l2 d, a buffer wll be nserted to drve. The maxmal drvng length l1 d of s obtaned from the look-up table (T slew ) based on C n1. A buffer wll be nserted at n B 1 n ths case. An example s shown n fgure 4b. The locaton of the mergng pont, should then be re-computed based on the Elmore RC model such as n fgure 4c. If s not located between n B 1 and such as n fgure 4d, the mergng pont should be located at. In ths case, delay balancng can be obtaned by nsertng snakng wres. Ths step wll be repeated untl condto and 2 are satsfed. (a) Blockage for buffer nserton 6A-1 C. Blockage Handlng There may be pre-assgned blockages n the routng regon. The connecton of two nodes and may thus be constraned to avod buffer nserton on blockages. Complete wre detour followed by post-buffer-nserton wll work, but t wll cost a lot of resources. Instead, we develop a blockage handlng method wth free wre propagaton and concurrent buffer nserton. It s based on the maze routng technque n global routng. However, we develop several technques to adapt t to satsfy CNS constrants. We frst mpose a m n grd on the whole routng regon, and and ( and are stll the segments due to the applcaton of DME approach) are then mapped to two groups of the closest grd ponts. Two ndependent maze routers mz 1 and mz 2 wth prorty queues are utlzed for and, and each queue s sorted by the downstream delay values of ts elements. Let D 1 and D 2 denote the downstream delay value of the frst element of the two queues. We assume that D 1 <D 2 at the begnnng, so mz 1 s selected to be the prmary router, and t wll search the four adjacent grd ponts of the current poston. Durng the routng of mz 1, wre connecton together wth buffer nserton s concurrently consdered along the path of each node. The downstream delay s then ncreased, so D 1 wll be updated. When D 1 becomes bgger than D 2, mz 2 wll replace mz 1 to be the prmary router and contnue the routng job. In ths way, mz 1 and mz 2 functon n turns, and the values of D 1 and D 2 stay close to each other. When the two routers meet at the end, ther delays wll not dffer a lot. Ths method can result n less buffer nsertons and wre detours. An approxmate performance comparson s shown n fgure 5. We can see that our blockage handler can save buffers and wres, so t wll reduce the total capactance. Notce that the sze of the grd graph (m n) s manually determned n our algorthm, m and n can be scaled up or down n order to have ether better CPU tme cost or routng qualty. In the experments, m and n are set as IV. EXPERIMENTAL RESULTS In ths secton, our expermental results are presented. We mplement our clock network syntheszer n the C language and the program s executed on the Lnux operatng system wth an Intel Core2 Quad 2.4GHz CPU and 4GB memory. The benchmark crcuts used n the experments are released from the (b) : Node : Mergng pont Fg. 5. Outputs of dfferent blockage handlng technques: (a) complete connecton detour and (b) our approach. ISPD09 CNS contest [18]. Detaled nformaton of the benchmark crcuts s shown n table II. Accordng to the benchmark crcuts, two specfed types of wres and buffers can be used n the clock network. Crcuts No. of No. of Lmtaton on snks blockages total capactance nb nb TABLE II CIRCUIT INFORMATION OF THE BENCHMARKS FROM ISPD We mplement the technques of two wdely used matchng methods MMM [1] and CL [7] n our syntheszer to replace DMST (dual-mst), wth the other parts of our CNS unchanged. In CL, the cluster sze s mantaned to be 2 3 of the group of nodes (n [7], the rato s between ( 1 2, 1) so 2 3 s a proper settng). The average result n table III s obtaned from executon on the benchmarks n table II, and SPICE smulaton s nvolved n every case. In table III, CLR (ps), nomnal clock skew (ps), total capactance (ff), total wrelength (nm) and CPU tme (seconds) are shown for performance comparson, and the results are the average value of all the bench- 471

6 marks. Compared to the approach of MMM, the approach of CL can reduce the total wrelength of the clock network n sacrfce of the clock skew. Our DMST approach has a longer total wrelength compared to the approach of CL. However, DMST needs a smaller total capactance because less number of buffers are requred for delay balancng. In general, our matchng technque, DMST, can outperform MMM and CL n clock skew, CLR, total capactance and CPU tme. V. CONCLUSION In concluson, a dual-mst approach for clock network synthess has been proposed. Several novel technques are appled to solve the CNS problem. Our DMST approach can gve a tree structure that s close to a balanced tree. Ths can reduce the senstvty of clock skew aganst voltage varaton. Expermental results show that the CLR can be mproved sgnfcantly wth much shorter CPU tme by applyng our approach. CLR Skew Cap. wrelength CPU (ps) (ps) (ff) (mm) (s) MMM CL DMST TABLE III COMPARISON BETWEEN DIFFERENT MATCHING METHODS. A summary of the performance of our clock network syntheszer s shown n table IV. CLR, capactance percentage, total wrelength and CPU tme are lsted. We run our program wth two scenaros. DMST s the approach wthout usng SPICE. DMSTSS s the approach wth SPICE smulaton. By usng SPICE smulaton, the locatons of the mergng ponts are adjusted and the clock skew can be reduced. We compare our results wth those obtaned from the two wnners (T4 and T6) of the CNS contest n ISPD09 and the best CLR (the result wthout volaton of the slew and total capactance constrants) of each crcut among all the teams n the competton. Notce that the programs of the wnners n the contest are executed under the platform wth dual-core AMD Optero.8GHz CPU and 128 GB memory. Accordng to the results n table IV, we can see that the CLR obtaned from both DMSTSS and DMST are outstandng. Although SPICE smulaton s not appled n DMST, the CLR s stll comparable and s even better than for some cases the best result n the ISPD09 contest. In addton, the CPU tme used by DMST s extremely small (mostly less than one second). DMST has ths effcent performance because t uses a tree structure that s close to a balanced tree. On the other hand, the CLR can stll be mnmzed even though the Elmore delay model s not accurate to evaluate the locatons of the mergng ponts. For DMSTSS, the clock skew (based on partcular voltage source) can be further mnmzed by obtanng the delays of subtrees from the SPICE smulatons. Although the CPU tme used s ncreased, t s stll the fastest approach compared to the wnners of the contest. Generally, the average CLR of our approach s only 38.0% of T4, 34.9% of T6, and 51.3% of the best results n the contest. Meanwhle, the average CPU tme of our approach s only 1.8% of T4, 4.7% of T6 and 1.7% of the best results from dfferent teams n the contest. CLR s the frst crteron for evaluaton accordng to the ISPD 2009 contest, and the expermental result shows the effectveness of our approach. VI. ACKNOWLEDGMENTS The work descrbed n ths paper was partally supported by the Compettve Earmarked Research Grant from the Research Grants Councl of the Hong Kong Specal Admnstratve Regon, Chna (Project No. PolyU 5262/07E). REFERENCES [1] M. A. B. Jackson, A. Srnvasan, and E. S. Kuh. Clock routng for hgh-performance cs. In Proceedngs of IEEE/ACM Desgn Automaton Conference, pages , June [2] M. Edahro and T. Yoshmura. Mnmum path-length equ-dstant routng. In Proceedngs of IEEE Asa-Pacfc Conference on Crcuts and Systems, pages 41 46, [3] A. Kahng, J. Cong, and G. Robns. Hgh-performance clock routng based on recursve geometrc matchng. In Proceedngs of IEEE/ACM Desgn Automaton Conference, pages , July [4] W. C. Elmore. The transent response of damped lnear networks wth partcular regard to wde band amplfers. Journal of Appled Physcs, 19(1):55 63, January [5] R.-S. Tsay. Exact zero skew. In Proceedngs of IEEE/ACM Internatonal Conference on Computer Aded Desgn, pages , Nov [6] T. H. Chao, Y. C. Hsu, and J. M. Ho. Zero skew clock net routng. In Proceedngs of IEEE/ACM Desgn Automaton Conference, pages , July [7] M. Edahro. A clusterng-based optmzaton algorthm n zero-skew routngs. In Proceedngs of IEEE/ACM Desgn Automaton Conference, pages , July [8] L. P. P. P. and van Gnneken. Buffer placement n dstrbuted rc-tree networks for mnmal elmore delay. In Internatonal Symposum on Crcuts and Systems, pages , May [9] J. D. Cho and M. Sarrafzadeh. A buffer dstrbuton algorthm for hgh-speed clock routng. In Proceedngs of IEEE/ACM Desgn Automaton Conference, pages , June [10] S. Natarajan, S. L. Sam, D. Bonng, A. Chandrakasan, R. Vallshayee, and S. Nassf. A methodology for modelng the effects of systematc wthn-de nterconnect and 472

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