Vertical LOCOS Power Devices in Victory Process: From 3D Process and Electrical Optimisation to High Speed, Full Chip Process Emulation

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1 Engineered Excellence A Journal for Process and Device Engineers Vertical LOCOS Power Devices in Victory Process: From 3D Process and Electrical Optimisation to High Speed, Full Chip Process Emulation Introduction There is a constant demand to lower the on-state resistance of devices, improving their energy efficiency as well as increasing their current handling capabilities whilst maintaining the desired breakdown voltage. However, a trade-off relationship exists between the on-state resistance and breakdown voltage. This is referred to as the silicon limit [1]. Attempts have been made to break the silicon limit. One such method proposed by several authors is the Vertical LOCOS MOS (VLOCOS) [2,3]. Such structures are relatively easy to simulate in 2D. However, the layout designs are inherently 3D [4]. Therefore it is critical that accurate and robust 3D simulations are undertaken to understand and fully optimize the electrical characteristics. In this Simulation Standard article, a rigorous investigation is made into the effect that various different 3D corner designs have on device breakdown performance. The simulations are executed using Victory Process (VP), Silvaco s fully three dimensional process simulation tool with 3D physical oxidation. Firstly a simple introduction is given via means of a 2D structure. Large matrix simulations are then run on the 2D structure using Virtual Wafer Fab (VWF) to optimize the device. The same matrix simulations are then run on 6 different 3D corner designs. One of the biggest challenges for this type of simulation is the oxidation of inherently complex 3D geometry. The investigation demonstrates VP s ability to robustly handle the physical oxidation of complex 3D geometries. Discussion is also given to the physical operation of the structures considered. Once device optimization is achieved and the layout generated, it is useful for the designer to be able visualize the full chip layout. VP can be run in Cell Mode, this mode is optimized for large areas with a highly efficient meshing algorithm and geometric process steps to emulate physical steps. All of these factors mean that a full chip geometric emulation flow can be simulated in a few tens of seconds. The last part of this article looks at one such example. 2D Device Cell Design A simple 2D half-cell of a VLOCOS structure is shown in Figure 1. Typically [4] the device is formed by etching a deep trench into an N- substrate. The trench is then lined with a thermal oxide and refilled with polysilicon to form the gate. Subsequent P-, P+ and N+ implantations are made into the surface to form the P-Base channel region and the P+/N+ Source contacts. In the upper portion of the trench only a thin oxide is grown creating a conventional MOS type gate that forms a vertical channel. In the lower portion of the trench a thick oxide is formed. This thick oxide combined with the P-Base / N-Drift junction serves to deplete the N- Drift region when the device is blocking in a similar manner to a RESURF [5] or Super-Junction [6] type structures. Continued on page 2... INSIDE Optimizing Solar Cell Top Metal Contact Design Introduction...12 Radiant Hints, Tips and Solutions Volume 25, Number 2, April, May, June 2015 April, May, June 2015 Page 1 The Simulation Standard

2 Figure 1. Simple 2D VLOCOS structure for reference simulations. Figure 3. Split tree in VWF showing the different variables used. In the current investigation we are only concerned with the breakdown voltage, as such; the P+ and N+ source implants are not included. A single planarized deposition of polysilicon is made over the entire surface giving a single contact. With a contact on the backside of the structure, the structure simplifies to a two terminal diode. Furthermore, to simplify the process a geometric etch is used to form the trench prior to oxidation. This gives a square bottomed trench rather than a more physical rounded shape. A snapshot of the deck used for the 2D experiment inside VWF is shown in Figure 2. The deck is highly parameterized to enable easy investigation into the variability of device behaviour. The width of the thick grown field oxide, the width of the drift, the doping of the drift and the trench depth were used as the variable set. The width of the field oxide was varied between 0.4um and 0.8um in three steps. The width of the drift was also varied between 0.4um and 0.8um in 3 steps. The drift region doping was varied between 8E15cm -3 and 5E16cm -3 in 4 steps. Finally, the thick oxide trench depth was varied between 4.5um and 6.5um in 3 steps. This gives a total of 108 individual structures, process and device simulations. The tree generated from these splits in the VWF DOE is shown in Figure 3. An exportable worksheet is created from the split parameters. The EXTRACT command is used inside the deck to automate the extraction of the breakdown voltage from the electrical simulations. The extracted data is automatically appended to the worksheet thus enabling easy cross referencing between variables and device performance. Further, more detailed analysis can be undertaken through exporting the data into Silvaco s Statistical Parameter and Yield Analysis Tool (SPAYN) or to a third party data analysis tool. The worksheet complete with extracted breakdown voltages is shown in Figure 4. Classically there are three modes of failure with VLOCOS devices, similarly to RESURF structures. Firstly, when the amount of charge in the drift is too high, the drift region is not fully depleted before avalanche multiplication is induced. Breakdown then occurs at the P-Base / N-Drift junction. Secondly, if the charge in the drift region is too low then the drift is rapidly depleted, the dominating electric field spike will occur at the bottom of the trench, on the corner, inducing avalanche multiplication. Finally, an optimally designed device would breakdown with a Figure 2. Parameterized process / device deck inside VWF. Figure 4. Fully populated worksheet for the VWF VLOCOS DOE showing variables and extracted breakdown voltage data. The Simulation Standard Page 2 April, May, June 2015

3 Figure 5. Breakdown voltage versus N-Drift doping trade-off curves for three different drift widths. box shaped electric field profile running down the edge of the thick oxide with impact multiplication simultaneously induced at both the P-Base / N-Drift junction and the bottom corner of the thick field oxide. Shown in Figure 5 is a typical set of trade-off curves. The width of the field oxide is set at 0.6 um, the depth of the thick oxide is set at 5.5um. Three curves are shown representing three different drift region widths, 0.4um, 0.6um and 0.8um. The breakdown voltage is plotted against N-Drift doping. Shown in Figure 6 are 2D contour plots of impaction ionisation from three of the structures shown in Figure 5 with a drift width of 0.8um and doping of 8E15cm -3, 2E16 cm -3 and 5E16 cm-3. These three structures demonstrate the three failure modes discussed earlier. The N-Drift charge for structure on the left is too low, with the drift region depleted too rapidly. As such, breakdown occurs at the bottom of the thick trench. The N-Drift charge for the structure on the right is too high, with the drift region unable Figure 7. 1D cutlines of electric field taken vertically, close to the thick oxide for the structures shown in Figure 6 highlighting the electric field peaks for the different failure modes. to fully deplete, breakdown occurs at the P-Base / N-Drift junction. The optimal design for the parameters considered in this instance is in the middle, where breakdown simultaneously occurs at the P-Base / N-Drift junction and at the bottom corner of the thick trench. The different breakdown modes can be further understood from Figure 7. Figure 7 shows 1D cutlines of electric field for the three devices shown in Figure 6. The cutlines are taken vertically through the drift region close to the thick oxide. The breakdown modes can clearly been seen from these plots. Excessive depletion of the drift and therefore sub-optimal breakdown is shown by the red curve (N-Drift, 8E15cm-3), the electric field spike occurs at the bottom of the thick oxide. Retarded depletion, the spike moves to the P- Base / N-Drift junction (blue curve, N-Drift = 5E16cm -3 ). Finally, the optimally depleted drift with simultaneous peaks occurring at both the P-Base / N-Drift junction and at the thick field oxide bottom corner (green curve). The complete set of 2D breakdown data has now been logged. The next phase of the investigation is to expand the structure design out into 3D and consider different corner designs; the 2D data can then be used as a baseline reference. 3D Oxidation of Corner Designs Transitioning from a 2D process simulation to a 3D process simulation is an elementary task in Victory Process. The user simply needs to set the desired 3D workspace co-ordinates, all other statements are common. Figure 6. Impact ionisation contour plots showing the three different failure modes. (left) N-Drift charge too low, with breakdown at the trench bottom (centre) optimum drift charge with simultaneous breakdown at trench bottom and P-Base / N-Drift junction (right) excessive drift charge with breakdown at the P-Base / N- Drift junction. Three different corner designs are considered, a sharp 90 degree corner ( Right ), a 45 degree chamfered corner ( Cut ) and a rounded corner ( Round ). These layout designs are used on both internal and external silicon corners, giving a total of 6 corner design variations. The same split parameters used in the 2D simulations are used in the 3D simulations, subjecting each corner design to 108 different permutations. April, May, June 2015 Page 3 The Simulation Standard

4 Internal Corners The first set of three designs are based around the silicon N-Drift forming an internal corner. A sample Right structure is shown in Figure 8a. With the polysilicon gate contact and the grown oxide stripped away for visualization, this gives the structure shown in Figure 8b, showing just the silicon. Figure 9. A sample Cut structure on an internal corner with polysilicon and oxide stripped away for visualization. Figure 8a. Sample 3D Right structure on an internal silicon corner. Figure 10. A sample Round structure on an internal corner with polysilicon and oxide stripped away for visualization. Figure 8b. Polysilicon and grown thermal oxide stripped away for visualization from Figure 8a showing the internal corner formed by the silicon and the effect on the silicon consumed by the thermal oxidation. Stripping off the polysilicon and oxide for visualization purposes, a sample Cut structure is shown in Figure 9 and a sample Round structure is shown in Figure 10. The starting shape of the trench, before oxidation, is quite evident at the top surface of the structure (where the thin gate oxide resides and minimal silicon consumption via oxidation has occured). Taking a cutplane through each of the three structures as indicated in Figure 11 enables us to compare the resulting corner shapes pre and post field oxidation. Figure 11. Cutplane location through thick field oxide on sample 3D structure. The Simulation Standard Page 4 April, May, June 2015

5 Shown in Figure 14 is the Right corner design on an external silicon corner. Figure 15 shows the reverse side of the same structure yet with the polysilicon and oxide removed for visualization. Figure 16 and 17 show the stripped out view for the external Round and Cut corner layouts respectively. Figure 12. Pre-oxidation oxide / silicon material boundaries for the three corner designs. Figure 14. Sample 3D Right structure on an external silicon corner. Figure 13. Post-oxidation oxide / silicon material boundaries for the three corner designs. The pre-oxidation material boundaries for silicon and oxide (polysilicon boundary removed for clarity) from the cutplane location indicated in Figure 11 are shown in Figure 12. The post oxidation boundaries are shown in Figure 13. Figure 15. Polysilicon and grown thermal oxide stripped away from Figure 14 for visualization showing the external corner formed by the silicon and the effect on the silicon eaten by the thermal oxidation. Post oxidation, the corner shape definition is reduced somewhat due to the eating of the silicon. However the resulting oxide / silicon interfaces for the three different layouts still maintain uniqueness. The true effect can only be understood once electrical simulations are performed on the structures, as will be discussed later in this article. External Corners The previous designs all centred on structures where the silicon formed an internal corner. For many layout designs, such as those that use a racetrack type layout the external corner of the trench must also be considered. Inverting the designs yields structures where the silicon forms an external corner. The same corner design concepts have been applied to this layout. Figure 16. A sample Round structure on an external corner with polysilicon and oxide stripped away for visualization. April, May, June 2015 Page 5 The Simulation Standard

6 Figure 17. A sample Cut structure on an external corner with polysilicon and oxide stripped away for visualization. Electrical Simulations The demands made on a mesh are often different for process simulation than they are for device simulation. Once the process simulation has been executed, the structure is automatically exported into Victory Device for electrical simulation. During the export stage, a new mesh is created. Exporting the structure and creating a new mesh gives us the opportunity to define a mesh more suitable for device simulation. For example, in device simulation we would typically want a fine mesh underneath the MOS gate oxide to accurately capture the inversion channel, where as in process simulation, this region might not necessarily be a concern. Figure 19. Doping contours displayed for the structure of Figure 18. The device export algorithm is a unified, fully 3D, Delaunay approach for volume mesh generation. It uses the restricted Delaunay triangulation of the vertices with respect to the high resolution surface geometry produced during process simulation. The restricted Delaunay triangulation is a special subset of the triangles which compose the resulting 3D device mesh, it is those triangles whose dual Voronoi edges intersect the input surface geometry. By refining the 3D mesh using careful rules, these restricted Delaunay triangles can be made to capture the surface geometry with arbitrarily high fidelity. By construction, these surface remeshes are simultaneously embedded within a high-quality volumetric mesh. The meshing scheme is robust and feature rich, the user can refine on junctions, doping, distance to material interfaces, local refinement can also be added via means of boxes, spheres, cones and columns, to name a few of the options. Shown in Figure 18 is a sample exported structure. The same meshing refinement scheme was applied to all of the structures considered in this article. The scheme is as follows: a coarse base mesh was first defined, refinement on distance to interface was then added, the target interface was the Polysilicon / Oxide interface. This yields a fine mesh in the silicon adjacent to the thin oxide, where the distance to interface is small and a slightly coarser mesh in the silicon near the thick oxide where the distance to polysilicon / oxide interface is larger. Figure 18. Exported sample Right structure showing mesh for electrical simulations. Figure 20. Sample breakdown curves for 3 Cut structures and equivalent 2D structures. The Simulation Standard Page 6 April, May, June 2015

7 This is a perfect scheme to ensure accurate MOS channel and drift depletion prediction. Refinement on junction was then added so as to accurately capture the P-Base / N-Drift junction. Finally box refinement was applied to the step transition between the N-Drift / N+ Drain. The meshing coarsens with distance from the box to that of the base mesh. The starting density and distance are all user defined parameters. Shown in Figure 19 is the structure of Figure 18 but additionally with the doping displayed, highlighting the localised refinement on doping and junction. Figure 21c. Sample Cut (internal) corner showing impact ionisation failure at the P-Base / N-Drift junction in the silicon due to too high drift charge. Sample breakdown curves are shown in Figure 20. The data showed is a function of thick oxide trench depth for the external Cut corner design combined with equivalent 2D data. For the design considered here the effect on breakdown voltage is quite pronounced. Figure 21a. Sample Cut (internal) corner showing impact ionisation failure at the bottom of the trench corner in the silicon due to too low drift charge. The failure modes for the 3D structures are identical to the 2D failure modes discussed earlier. A sample is shown in Figure 21a, where the drift charge is too low hence thick oxide bottom corner failure, Figure 21b, with optimal drift charge, hence simultaneous failure at the P- Base / N-Drift junction and the trench corner and finally excessive drift charge hence breakdown at the P-Base / N-Drift junction, as shown in Figure 21c. Shown in Figure 22 is a BV trade-off curve against drift doping for the three different layout designs on an internal corner. There is a slight trend in design with the Round design giving a marginally higher breakdown voltage than the Cut which in-turn gives a slightly high breakdown voltage than the Right design. Figure 21b. Sample Cut (internal) corner showing impact ionisation failure simultaneously at the bottom of the trench corner in the silicon and at the P-Base / N-Drift junction due to optimized drift charge. Figure 22. Breakdown voltage as a function of N-Drift doping for a drift width of 0.6um and thick oxide trench depth of 5.5um for the three different (internal) corner designs. April, May, June 2015 Page 7 The Simulation Standard

8 Figure 23. Breakdown voltage as a function of N-Drift doping for a thick oxide trench depth of 5.5um for the Right corner design and three different drift region widths. Shown in Figure 23 is a breakdown voltage / N-Drift doping trade-off curve for the Right corner design and three different drift widths. Optimum N-Drift charge can either be achieve through a fixed width and variation in doping or a fixed doping and variation in width. For the doping range considered, a maximum BV of 110V is achieved here for a drift width of 0.6um and doping of 2E16cm -3. The curves imply that a further reduction in doping for a drift width of 0.8um might enable an increase in breakdown voltage but it must be born in mind that this will cause an increase in the on-state losses due to the increased drift resistance, the effect being a direct reference to the breakdown voltage / on-state trade-off curve discussed in the introduction. Shown in Figure 24 is the breakdown voltage / N-Drift doping trade-off curve for the three different corner designs. Similarly to the internal corner designs, a design layout trend can be seen with the Right design showing the optimum breakdown, followed by the Cut and then the Round. Interestingly, this is the opposite trend to the internal corner design. Overall for the designs considered there is a noticeable reduction in breakdown voltage. No peak in the trade-off is observed, the curve Figure 25. Breakdown voltage as a function of N-Drift doping for a thick oxide trench depth of 5.5um for the Right design and three different drift region widths. suggests that the doping can be further increased. For the external corner design, when considering this small layout, there is actually three depletion regions working on the N-Drift, the P-Base / Drift junction, as is standard, but this layout also has two thick oxide trenches perpendicular to one another, thus enhancing the depletion. Which in-turn means a high charge can be set in the N- drift region for an optimum BV. Shown in Figure 25 are the Breakdown Voltage / N-Drift trade-off curves for the Right external corner design as a function of drift width. This further highlights that due to the two perpendicular thick field trench oxide depletion regions operating on the drift region then the drift region can sustain a higher charge for optimum breakdown. Shown in Figure 26 are the Breakdown Voltage / N-Drift trade-off curves for the Round internal corner design and its equivalent 2D structure. It is quite clear from this plot that it is very important to consider the corner design in the layout. Below a certain N-Drift doping level, the corner design actually enhances the breakdown voltage. Increasing the N-Drift doping leads to a reduction in BV in comparison to the 2D designs, as would typically be considered. Figure 24. Breakdown voltage as a function of N-Drift doping for a drift width of 0.6um and thick oxide trench depth of 5.5um for the three different (external) corner designs. Figure 26. Breakdown voltage as a function of N-Drift doping for a thick oxide trench depth of 5.5um for the Round corner design and equivalent 2D structure. The Simulation Standard Page 8 April, May, June 2015

9 Figure 27. Breakdown voltage as a function of N-Drift doping for a thick oxide trench depth of 5.5um for the Round corner design and equivalent 2D structure. Figure 29. Large Area Round structure with polysilicon set to transparent showing the increased dimension in comparison to the devices used previously. Figure 28. Breakdown voltage as a function of N-Drift doping for a thick oxide trench depth of 5.5um for the Round corner design and equivalent 2D structure. Shown in Figure 27 are the Breakdown Voltage / N-Drift trade-off curves for the Round external corner design and its equivalent 2D structure. Similar observations can be made to the internal corner design, except in this instance the trend is reversed. It is found that with higher drift charge external corner design shows improved breakdown behaviour. Below a certain drift charge the external corner designs show reduced breakdown behaviour. structure (red curve). This is because when we move away from the corner, the corner effects no longer dominate and the 2D layout limits the BV. This is shown by the Large Area Round (blue) curve in Figure 28. For the Large Area Round structures, the 2D device length, as shown in Figure 29 was increased from 0.8um to 1.8um. Consequently the large area devices show breakdown closer to that of the equivalent 2D device as the corner effect is less dominant and the characteristics tend to that of the 2D device BV limit. When considering a small device segment, then corner effects can dominate the simulated characteristics. This is acceptable if the small segment wholly represents the practical device. However, this is not necessarily the case. A complete device is made up of several different corner regions (internal, external etc) and long stretches that are essentially 2D. The lowest breakdown voltage from each of these different areas will be the device s BV limit. This is shown in Figure 28. Consider the breakdown voltage at an N-Drift doping of 2E16cm-3, the Round structure actually shows a higher breakdown voltage than the 2D equivalent. This is because of the small device size, the corner effects dominating the behaviour. If this design is used in the chip with long, essentially 2D trenches running perpendicularly, away from the corner then the actual breakdown voltage will be lower and will be that of the 2D equivalent Figure 30. GDS layout of a quarter of a full chip. April, May, June 2015 Page 9 The Simulation Standard

10 Figure 31a. Large area physical simulation of a portion of the full cell design with two active trenches, surrounded by the termination trench. Large Area, High Speed Process Emulation for Layout Verification Once the optimised design is identified through rigorous physical simulation, the next phase is to design the layout. Although the engineer has design rules to follow, it is incredibly useful if the whole chip layout can be simulated. This helps the engineer visualize the layout, communicate the designs and to obtain feedback from colleagues. Shown in Figure 30 is a quarter cell layout of a complete VLOCOS chip design including termination and deep isolation trenches as seen in [4]. The active trenches can be seen on the right, running horizontally, they are surrounded by the termination and isolation trenches, running vertically on the left and continuing horizontally across the top. The quarter cell is approximately 35 x 35 um with 9 active device trenches approximately 25um long and encircling termination and deep isolation trenches. Figure 31b. As Figure 31a but with the polysilicon removed for clarity showing the grown active and termination oxides. Victory has two modes of operation: Process Mode and Cell Mode. Process Mode was used earlier in this article. Process Mode is optimised for accurate physical simulations whereas Cell Mode is optimised for high speed, large area simulations with focus more on emulation, rather than physical simulation. Deck structure and syntax is common between the two, all the user needs to do is initialise the deck to run in Process Mode or Cell Mode. Obviously physical steps such as oxidation must be suitably adjusted for. Having common syntax makes such a task easy for the engineer as there is no need to learn different tools, syntax or working environments. Call mode structures are not limited for just visualization use, they can also be exported and electrically simulated. The pseudo-realistic emulated process sequence used here only considers the layout geometry, included in this simulation were contact etches, one via and two metal masks. The quarter cell was simulated in 60 seconds on an aver- It is quite possible to undertake large area physical simulations, as shown in Figure 31a. Figure 31a shows a section of the full cell design with 2 active trenches, surrounded by a termination trench. Figure 31b shows the same structure but with the polysilicon removed showing the corners and oxide grown through physical simulations. The simulation domain for the example is 10um x 10um and uses the same process sequence as in the previous sections. However, for simple visualization, rigorous physical simulation is not required. Physical process steps can be replaced by steps that emulate the process step, where the step is defined by geometric parameters, such as thickness and coverage, oxidation can be simplified to an etch of the silicon (to approximate the silicon consumption during oxidation) and oxide deposit, to emulate the oxide growth. Figure 32 Quarter cell from the emulated process flow. The Simulation Standard Page 10 April, May, June 2015

11 Figure 33. Mirrored quarter cell, producing full emulated cell. Top metal layers set to transparent. Figure 34. Underside of the mirrored quarter cell, silicon set to transparent and isolation trench removed. age desktop machine, the speed coming from the large area, optimised meshing algorithms. The mesh in this instance is the minimum unstructured mesh needed to represent the geometry, no refinement was included. Shown in Figure 32 is the quarter cell produced from the from the emulated process flow in cell mode, the ends of the active trenches can be seen on the right, with the termination and isolations trenches surrounding. During export additional manipulation of the structure can be undertaken. For example: sections of the complete structure can be cropped off, material regions can be split and the structure can be mirrored. The latter is particularly useful if the user wishes to take advantage of structural symmetry, as is the case here. The quarter cell of the emulated process was mirrored on both axis during export to give a full cell, the resulting structure is shown in Figure 33, with the top metal layers set to transparent. Figure 34 shows the same structure but from the underside with the silicon set to transparent and the isolation trench removed for visualization, displaying the active and termination trenches. Acknowledgments The authors would like to acknowledge the support from the E2SG Energy to Smart Grid Project co-funded by the ENIAC Joint Undertaking under the SUB-PROGRAMME SP3 - Energy Efficiency ENIAC JU Grant Agreement n , for part of the effort that contributed to this article. References 1. C. Hu, IEEE Trans. on ED, Vol. 26, pp , M. Kodama et al., ISPSD 2004, pp P. Moens et al., IEDM Tech. Dig. 2007, pp /jul_aug_sep/a2/a2.html 5. J. Appels and H. Vaes, HV thin layer devices (RESURF devices), International Electron Devices Meeting Technical. Digest, 1979, pp T. Fujihira, Theory of Semiconductor Superjunction Devices, Japanese. Journal of Applied Physics, 36, 1997 pp Conclusions This article has shown that it is vital for the designer to undertake full three dimensional process and device simulations. Without such simulations, and limiting to 2D simulations, device characteristics can be critically overestimated. This article also demonstrated how high speed, large area, full chip process emulation can be achieved for visualization and design verification. April, May, June 2015 Page 11 The Simulation Standard

12 Optimizing Solar Cell Top Metal Contact Design Introduction Among the many design criteria for solar cells, the design of the top metal contact impacts the cell efficiency. The areal density of the top contact modifies the magnitude of the cell output power significantly. Solar cells suffer from optical losses. These limit the total number of photogenerated carriers. Add to that, carriers suffer from electronic (recombination) losses. Using numerical simulations these losses can be quantified and minimized. Photogenerated carriers experience bulk resistivities as well as surface sheet resistivity before collection at the top contacts. The contact design aims to maximise carrier collection against internal resistance and metal shadowing. For complex metal designs there are no simple analytical solutions for the optimum contact areal density. In this article, 3D TCAD software is used to maximise the cell output power as a function of contact areal density. Solar Cell Losses The design of the top contact aims to reduce the fractional power loss [1] which is defined as: ƒ ƒrac = P loss P gen ρ J mp V mp where ρ is the sheet resistivity, J mp is the maximum power current density and V mp is the maximum power voltage. High contact areal density reduces the impact of the surface sheet resistance but increases the shadowing. On the other hand a low contact density will reduce the shadowing effect boosting the generation power but increases the losses due to the sheet resistance. TCAD numerical modelling of the various metal coverage ratios helps to locate the optimum contact design density. while z was set with small spacing near the top and bottom surfaces and larger spacing in the middle. The idea is to capture the doping profile near the surface. In total 201 x 201 x 39 lines were generated. This generates a structure in excess of million points. Nevertheless, the simulations ran in less than 4 hours and 15 minutes on a single CPU. The main overhead was due to the diffusion steps. At the end of the process simulation, the export statement was used to generate a structure suitable for the device simulations. Users have a number of options here. In this study conformal and Delaunay mesh export were investigated. Since this is a large solar cell structure of 4 mm 2 or 4 million μm 2, careful device meshing of the final structure suitable for the Victory Device simulation was needed. The conformal meshing algorithm generated more than 1.2 million nodes and 70 million tetrahedral, while the Delaunay mesh algorithm produced 65k nodes and less than 300k tetrahedral. For the Delaunay mesh adaptive refinement based on the distance to the p-n junction was used. This leads to a significant speed up of the device calculations. This adaptive refined meshing algorithm ensures an optimal density to speed up the device carrier generation and recombination and transport calculations. A typical Delaunay based Victory Device calculations took 20 minutes using 3 CPUs on a 4 CPU machine. This represents a speed up of x100 compared to the calculation involving the equivalent conformal structures with no adaptive refinement on the same machine and resources. Although there was a difference of 15% between the Isc from the conformal and Delaunay mesh structures, the maximum obtained power was within 2%. Simulation Setup A simple silicon solar cell with top p-type contacts (cathode) and an n type bulk with back substrate contact is used. A cell of 4 mm 2 and 100 micron thick was created using Victory Process ( Cell Mode ) employing a mask set for the implants and metallization layer. A simple basic process flow involving two implants and anneal steps as well as the Aluminium metallization for the top contacts was used. The process simulation contain less than 20 steps. Following the init statement, line statements were used to control the volume data resolution. For this study, the x and y lines, which defined the surface plane, had uniform spacing, Figure 1. Showing the adaptive meshing used for the 4mm 2 solar cell. The Simulation Standard Page 12 April, May, June 2015

13 Figure 2. showing the acceptor 3.4e17 /cm 3 isosurface beneath the hexagon metal contacts. On the other hand, higher Delaunay mesh densities did not significantly impact the output data and produced short circuit currents I sc that were within 0.4% of the original values. This confirms that the Delaunay meshing density used did not significantly impact the precision of the final result. For the Aluminium top contact, a regular hexagonal grid mask was used. This shape which is characterized by six equal sides and internal angles of 120 o, provides uniform top surface coverage and a simple method to characterise the exposed silicon to metal area ratio as described below. No suggestion is made here that hexagon grid contacts are the optimum design for such cells. In fact many more complex designs have been referenced in the last few years in the open literature [2]. Once the mask set is created, this is invoked in the process simulator Victory Process on the init statement. To generate a valid simulation matrix all parameters were kept constant apart from the size (and hence areal density) of the hexagons covering the top surface. This can be achieved easily using MaskViews. Figure 4. showing how to rescale a mask set in MaskViews software. It is a trivial step to expand or shrink the size of the hexagons to facilitate this study using MaskViews software. Load the mask set (.lay format in this case) into MaskViews, then use options => rescale layout then save. This will change the area and density of the hexagon metal. However, associated with this action, the width of the Aluminium hexagon sides will also be modified. Since the aim here is to investigate the effect of the polygon areas on the cell efficiency, the metal finger widths need to be kept constant. To achieve this, the parameter deltacd was used on the mask statement in Victory Process. This critical dimension delta parameter offsets mask polygon edges by the defined number in micros. This made fixing the metal finger width a relatively trivial task. An alternative approach useful for regular geometrical shape contacts such as used has been added in Version V onwards. The new feature implemented on the specifymaskpoly statement allows users to convert circular shapes to regular polygons using npoints and radius to define the number of regular sides and the radius length. The device calculations were performed using the Victory Device paralyzed linear iterative solver PAM. Raytracing was used to propagate the light into the solar cell. This robust algorithm is valid since no complex coherence effects were anticipated in the structure used in here. To expedite the calculations, the incoming beam was limited to a monochromatic beam with a wavelength of 0.6 μm. A full solar spectrum could be used which might produce more representative results. Nevertheless, the methodological approach remains the same. Figure 3. showing the 2D (cut plane from the 3D structure) and 1D (cut line) doping profile underneath the top metal contacts. The extra doping helps to reduce the contact resistance. Apart from setting the bulk carrier lifetime, surface recombination rate for both holes and electrons was set for the top surface using the interface statement. April, May, June 2015 Page 13 The Simulation Standard

14 Data Analysis In order to compare the various cells used, the following coverage ratio was defined: R A si A al Where is the area of the exposed silicon within a hexagon calculated as 3 3 A si = 2 a 2 Here is the length of the side which is also the radius of the circumcircle that envelops the hexagon. On the other hand for the Aluminium, A al = 6ab + c Where A al represents half the aluminium metal area surrounding the regular hexagons. Here b is half width of the metal fingers and c is an additional correction triangular areas at the six apex angles. The ratio R values investigated in this study ranged from 40.3 to 4.3. This corresponded to the regular hexagon circumcircle radius of 935 μm to 104 μm. Although other data is available that confirm the trend shown in here, the three structures used in this article can be characterized in the following table: Parameter Circumcircle diameter or hexagon side (micron) Coverage ratio R Small (high density) hexagons Medium Large (low density hexagons) Plot color Red Green Blue Short Circuit current Isc (A) Fill Factor Maximum output power (mw) In Figure 6 the light IV characteristics show a variation in the short circuit current (I sc ) but similar open circuit voltage (V oc ) of 0.65 volt was obtained as expected. These cells produced similar open circuit voltage V oc of about 0.65 V. Although the largest hexagon solar cell produces 6% more short circuit current Isc the associated benefit is counteracted by 16% lower fill factor FF of 0.61 compared to a FF of 0.71 for the other two cells. Since the solar cell efficiency is defined as η = I SC V OC FF Pin Figure 5. showing the largest and smallest hexagon grid top contact for the 1mm2 Silicon solar cell investigated in this study. Figure 6. showing the solar cell IV with the red trace for the smallest hexagons (circumcircle radius or side length a of 104μm), green (a=225μm) and blue for the largest hexagon (a=945μm). The Simulation Standard Page 14 April, May, June 2015

15 Conclusion In conclusion, numerical simulations allow solar cell designers to discover the optimum metallization aerial density for complex designs. 3D process and device TCAD simulations have been used to achieve this. Adaptively refined Delaunay meshing produced significant speed up with the device simulations. This type of study can be easily driven via the Virtual wafer fab (VWF) design of experiment (DOE) matrix calculations. Finally, the new feature of the specifymaskpoly statement will allow users to automate the optimization of the top contact areal density. The size and in turn the aerial density of regular polygons can be defined in the deck for each iteration on the fly. Figure 7. showing the PV sweep of the three solar cells. As before red (a=104μm), green (a=225μm) and blue (a=945μm). This opens up the possibility of using the powerful Silvaco automation tools to locate optimal designs. It is clear that both factors carry the same influence on the overall conversion efficiency of the cell. This also explains how the maximum output power of the cells was greatest for the middle density cell with the coverage ratio of 9.5 as shown in Figure 7. The green trace above shows an increase in the maximum cell power of 8% with respect to the blue trace and 11% with respect to the red trace. Figure 8 is a plot of the cell output power as a function of the coverage ratio for the selected material and process flow used in this study. A clear maximum power peak is obtained for the silicon coverage ratio of 9.5. Acknowledgments The authors would like to acknowledge the support from the E2SG Energy to Smart Grid Project co-funded by the ENIAC Joint Undertaking under the SUB-PROGRAMME SP3 - Energy Efficiency ENIAC JU Grant Agreement n , for the effort to produce this work. References 1. C.M. Singal, Analytical expression for the series-resistance-dependent maximum power point and curve factor for solar cells, Solar Cells, Volume 3, Issue 2, March 1981, Pages M.N. van den Donker, P.A.M. Wijnen, S. Krantz, V. Siarheyeva, L. Janßen, M. Fleuster, I.G. Romijn, A.A. Mewe, M.W.P.E. Lamers, A.F. Stassen, E.E. Bende, A.W. Weeber, P. van Eijk, H. Kerp, K. Albertsen, 23rd European Photovoltaic Solar Energy Conference, 1-5 September 2008, Valencia, Spain Figure 8. Showing the relationship between the maximum output power and the metal coverage ration R. April, May, June 2015 Page 15 The Simulation Standard

16 Radiant: GUI-based Design Software for Performing Simulations of Optoelectronic Thin Film Devices Such as LED and OLED Introduction Device simulation helps users understand and depict the physical processes in a device and to make reliable predictions of the behavior of the next device generation. Device simulations with properly selected, calibrated models and an appropriate mesh structure are very useful for predictive analysis of novel device structures. This helps provide improved reliability and scalability, while also helping to increase development speed and reduce risks and uncertainties. In order to be even more efficient Silvaco releases Radiant an interactive tool to simulate LED and OLED devices. Radiant consists of a very easy to use and intuitive graphical user interface allowing the user to input key simulation parameters without having to know the syntax of the device simulator. Behind the scene and automatically an input deck is created and run. Results are displayed using TonyPlot. In this introduction to Radiant a one layer diode, with anode and cathode contacts, is created and simulated. Please see the Atlas manual for more information about Atlas commands. Creating the Device Radiant is started by typing radiant at the command prompt. The initial window appears (Figure 1). Figure 2. The initial Add Layer window. The two Air layers are the external medium the device will exist in. The device parameters are defined in the right hand panel. An image of the current device is shown in the left hand panel. The Name of the device, oled in this example, is used as the root of the files generated when simulating the device. To add a layer, ensure the Structure tab is selected in the right hand panel. and click on the Add button on the bottom right. The Add Layer window appears as show in Figure 2. The top layer is to be the anode contact, select the Layer Type drop-down list and choose Schottky Contact (Figure 3). Figure 1. The initial main window of Radiant. The Simulation Standard Page 16 April, May, June 2015

17 Click Continue. This will add the layer to the device and leave the Add Layer window open. The main window will show the anode has been added to the device as shown in Figure 5. Now add a doped Alq3 layer, which is the active layer of the diode. Choose a Semiconductor Layer Type, leave the Name blank, define a Material of Alq3, a y Del of 100 and a y NStep of 20. In the doping line select n-type from the drop-down list and set a concentration of 1e14. Figure 3. Select Schottky Contact for the Layer Type. Enter anode in the Name line ITO in the Material line 25 in the y Del line 5 in the y NStep line The Name is the name of the layer in the Atlas deck, a name is required for a contact, but is optional for the other types of layer. The Material is the material of the layer. y Del is the thickness of the layer, in nanometers. y NStep is the minimum number of mesh points Atlas will add to the layer. Figure 6. The definition of the Alq3 layer. And click Continue. Now add an aluminum cathode to the bottom of the device Figure 7. The definition of the cathode. Figure 4. The definition of the anode. And click on OK. OK will add the layer to the device and close the Add Layer window. Figure 5. The main window when the anode has been added to the device. April, May, June 2015 Page 17 The Simulation Standard

18 Figure 8. The main window with the complete device. Figure 9. The main window with the Material tab activated. The main window will show the device as shown in Figure 8. To define material parameters select the Material tab in the left hand panel (Figure 9). Select the ITO line, click on Edit and the Edit Material window opens. There are three columns next to each label. A Temporary column, a User Defined column, and a Default column. The data in the Default column is built into Radiant and cannot be changed by the user. Any data entered into the User Defined column will be automatically saved when exiting Radiant (on a per-user basis) and will be available the next time Radiant is run. Any data entered into the Temporary column are not automatically saved, but will be saved in the File->Save deck. The value used in a simulation is the right-most value in a particular row: Temporary data will be used in preference to User Defined data, which will be used in preference to the Default data. The Simulation Standard Page 18 April, May, June 2015

19 Figure 10. Defining the Work Function of the anode. Figure 12. Defining the Work Function of the cathode. Enter 5.4 in the Temporary column of the Work Function line (Figure 10), and click OK. Select the Alq3 line, click Edit, and enter 3.4 to the EG300 line, and 2.2 to the Affinity line, and click OK (Figure 11.) DC Simulation Select the Analysis tab, and click on Add DC. The Add DC window opens. Leave anode in the Contact dropdown box, this is the contact the bias will be applied to. Add a VStep of 0.1 and a VFinal of 10 (Figure 13). Figure 13. The Add DC window. Figure 11. Defining the band alignment of the Alq3 layer. Finally set the work function of the aluminum cathode to 3 as shown in Figure 12. And click OK. A single trial has been added to the Analysis table as shown in Figure 14. Click on the Models button, and ensure the pf.mob option is unchecked. If it were activated then the Poole- Frenkel mobility model would be used, but that model is not required for this simulation (Figure 15). Figure 14. The main window with the Analysis tab selected. April, May, June 2015 Page 19 The Simulation Standard

20 The oled.in file is the Atlas input deck generated by Radiant, the oled.in.out is the run-time output generated by Atlas when running the oled.in deck. oled_init.str is the structure of the device after the initial SOLVE INIT. These files are generated whenever Radiant runs. Figure 15. The Models window. Click on OK. Open the Run menu, and select Run. A dialog box will pop up to confirm whether to run the simulation. It will look similar to Figure 16. Figure 16. A confirmation dialog. Each trial also generates files, the types of files generated depend upon the trial. oled_0.log is the log file generated during this DC trial and oled_0.str is the structure file at the end of the trial. The contact current at the final bias is also extracted in the input deck with the lines extract init inf= oled_0.log extract name= i_tr0 y.val from curve(v. anode,i. anode ) where x.val=10. The result of this extract can be used by other tools. Double clicking on oled_0.log will open the file in Tony- Plot (Figure 19). The anode workfunction was 5.4 ev and the cathode workfunction was 3.0 ev and the diode turn-on is at the expected 2.4 V. The identity of the simulation will be different though. The first part is the date (YYYYMMDD), and the second part is the time (HHMMSS). Click on Yes to run the simulation. Radiant creates a unique directory and runs the simulation in that directory, so that any output files from this simulation do not overwrite the files from any other simulation. A DeckBuild is created to run the simulation, this will initially be minimized. Once DeckBuild has finished open the View menu, and select Current. Figure 19. The DC-IV curve of the forward biased diode. Figure 17. The View->View window. Click on View to see a list of the files generated by the simulation. Change the File type filter to All files (Figure 18). Saving and Loading Devices To save the current state of a device, its structure and analysis, open the File menu and select Save as. Enter the required file name in the File name box and click Save. The file that is saved is an Atlas deck (that can be run in Atlas) with some extra commands at the end that store additional information required by Radiant. Figure 18. The files generated by a DC trial. Figure 20. The File->Save As window. The Simulation Standard Page 20 April, May, June 2015

21 To close down Radiant open the File menu and select Exit. If there are any unsaved changes to the device a dialog box will open to check if these changes should be saved or discarded. To start Radiant with an existing device, the file can be given as a command line option radiant oled.in A deck can also be read in by opening the File menu and selecting Open. Calculate over the visible spectrum in 1 nm steps by adding 390, 700, and 311 to the boxes in the Lambda line (the step is automatically calculated and shown in the final column). Select emit.top, dipole, and norm.ang. Horizontal, Num Rays, and Angle Output can be left blank (they will take their default values). Set Angle to 0. The Angle is the angle used when extracting results from this trial (Figure 22). Optical Simulation Select the Analysis tab, and click on Add TM. The Add TM window opens (Figure 21). Figure 22. The Add TM window with the parameters for the trial. Figure 21. The Add TM window. The Alq3 layer is the active layer in this diode, so select Alq3 from the Layer drop-down list. The position of a dipole is defined relative to a layer. Define a dipole in the middle of the Alq3 layer by adding 0.5 to the Min column in the X and Y lines. Click on OK and the trial has been added to the analysis list. Once a dipole has been defined the Dipole On button is activated on the left-hand panel. Clicking on this will show the location of the dipoles in the device (Figure 23). The emission spectrum of dipoles in a layer can be specified on the Material tab. In this example the Alq3.spc file has been copied from the Atlas common/sspeclib directory. Select the Material tab, select the Alq3 line, and click on Edit (Figure 24). Figure 23. The main window showing the position of the dipole. April, May, June 2015 Page 21 The Simulation Standard

22 Click on Cancel to close this window. Open the Run menu and select Run. The trials are run in the order they are defined in the list on the Analysis tab, here the DC sweep will be performed first followed by the transfer-matrix optical simulation. To see the files generated by this simulation open the View menu, select Current, and click on View. Figure 24. Select a spectrum file for the Alq3 layer. Once a file has been selected the data can be viewed by selecting the bottom option in the drop-down list. Figure 27. The files generated by the DC and TM trials. The oled.in, oled.in.out, and oled_init.str are the standard files generated by any simulation. oled_0.log and oled_0. str were generated by the initial DC trial. Figure 25. Once the file has been selected the data can be viewed. The files oled_1_ap.log, oled_1_os.log, and oled_1_sa.log have been generated by the TM trial. The _ap file is from the ANGPOWER parameter on the Atlas SAVE command, the _os file is from the OUT.SPEC parameter, and the _sa file is from the SPECT.ANGLE parameter. The TM trial extracts CIE x, CIE y, the luminosity, the intensity, and the luminance at the given angle. The wavelength of the peak of the spectral power density is also extracted (Figure 27). Figure 26.The data in the Alq3 file. The Simulation Standard Page 22 April, May, June 2015

23 Figure 28. The results of the TM trial. Sweep The Run->Sweep option can be used to map the changes in the outputs to changes in the structure of the device. Open the Run menu and select Sweep and the sweep window appears. This is used to specify the parameter that will vary and the range they will vary over. Figure 30. The Add Variable window. Figure 29. The Sweep variables window. Click on Add and the Add Variable window opens as shown in Figure 30. Independent variables are associated with layers, select Alq3 from the Layer drop-down box. Within each layer the variables are grouped. The Alq3 layer has Layer and Trial Dipole groups. The Layer variables are parameters associated with the layer as a whole; the thickness and the doping. The Trial Dipole variables are parameters associated with the dipoles defined on the layer; the position, the output angle, the orientation of the dipoles. Select the Layer (Independent) Group and the Donors Variable. Enter 1e14 to Start, 1e17 to End, 7 to NPoint and choose the Logarithmic Scale. Linear variables sweep between the Start and End values in an arithmetic progression, Logarithmic variables sweep between the Start and End values in a geometric progression. April, May, June 2015 Page 23 The Simulation Standard

24 The files can now be viewed. A sweep generates more files than a single simulation. The files generated by each trial of each simulation are saved. Their names have _bd$ trial_id appended before the file extension to distinguish between them. The DC IV curves from the seven trials are shown in Figure 35. Figure 31. Sweep the doping in the Alq3 layer between 1e14 and 1e17. Click on OK to add the variable to the trial. Figure 35. The DC-IV curves for the different trials. Figure 32. The Sweep variables window with the doping variable added. DBInternal saves the results of the sweep, this contains the variables that have been swept, and the results of any EXTRACT statements in the trial deck. These results have been saved in the oled_db.log file. The anode current at Vanode=10V as a function of donor doping is shown. Click on OK and a dialog appears asking it the simulation should be run, click on Yes. A DeckBuild will open and use DBInternal to run the set of simulations. Open the View menu and select Current. The current simulation may have a status of Running.. Figure 33. The View->Current window while the sweep is running. Figure 36. The anode current as a function of donor concentration. Currently Radiant doesn t allow the files of a running simulation to be viewed. Wait until the simulation has finished and click Refresh (Figure 34). Conclusion Radiant is a GUI-based powerful design software for performing accurate simulations of optoelectronic thin film devices such as LED and OLED. Radiant provides a fully integrated and user-friendly environment including coupled electrical and optical device simulations, optimization and visualization based on state of the art Silvaco TCAD softwares. Figure 34. The View->Current window when the sweep has finished. Radiant enables faster time to market for the novel lighting devices. The Simulation Standard Page 24 April, May, June 2015

25 Hints, Tips and Solutions Introduction How can I Mirror 3D structures in Victory Process? Victory Process supports mesh generation for device simulation using many common algorithms. The primary two are conformal and delaunay. A simple process simulation followed by an export will result in a mesh modeling the device grown. If the device is a single array of a larger device, we can mirror at the export stage instead of creating a symmetrical structure during the process. This has the advantage of a faster process simulation. this would give one copy of the process mesh in the negative x-axis followed by another mirror in the positive x-axis before the device mesh is generated (Figure 2). Each operation in the mirroring string must be in the form [-+][0-9]*[xyz], so for example, we could also state +2x, or +2x+y etc. Example delaunay export (Figure 1) export victory(delaunay) name= structure \ max.size=0.1 \ distance.interface.materials=sio2 \ max.interface.size=0.025 \ max.interface.distance=0.5 Figure 2. Process mesh mirroring. Figure 1. Example Delaunay export (with interface refinement). Mirroring We support various forms of mirroring. The simplest is: export victory(delaunay) name= structure_a \ mirror.process= x+x \ max.size=0.1 \ distance.interface.materials=sio2 \ max.interface.size=0.025 \ max.interface.distance=0.5 If we wish to mirror the device mesh itself: export victory(delaunay) name= structure_b \ mirror.device= x+x \ max.size=0.1 \ distance.interface.materials=sio2 \ max.interface.size=0.025 \ max.interface.distance=0.5 would first generate the conformal mesh, then mirror it in the negative and then positive x-axis (Figure 3). The export is faster since the refinement is performed on the unmirrored mesh before the device mirroring occurs. Note that we now have symmetry in the exported device mesh. April, May, June 2015 Page 25 The Simulation Standard

26 Figure 3. Device mesh mirroring. Figure 4. Process followed by Device mirroring. The mirror.process and mirror.device strings can be used together. For example: export victory(delaunay)name= structure_c \ mirror.process= x mirror.device= +x \ max.size=0.1 \ distance.interface.materials=sio2 \ max.interface.size=0.025 \ max.interface.distance=0.5 will mirror the process mesh in the negative x-axis a single time, generate the conformal device mesh, and then mirror the device mesh in the positive x-axis. In this case we have four copies of the original structure (Figure 4), in a mesh which is symmetrical at x_max, where x_max is the x-axis bound of the input process mesh. Note that we only have a single line of mesh symmetry in this example.mirror.process mirrors the structure before the device mesh generation. will perform a crop-rectangle of the process mesh from the given points, mirror that, generate the device mesh, and then mirror that (Figure 5). Note: Cropping is currently only supported in cell mode. We can also change the order of the crop/mirror operations: export victory(delaunay) name= structure_e \ mirror.process= x mirror.device= +x \ crop.from = 0.75, 0.25 crop.to = 0.75, 0.75 \ process.ops.order = mirror crop \ max.size=0.1 \ distance.interface.materials=sio2 \ max.interface.size=0.025 \ max.interface.distance=0.5 The mirroring operations can also be combined with the crop/slice. For example: export victory(delaunay) name= structure_d \ mirror.process= x mirror.device= +x \ crop.from = 0.25, 0.25 \ crop.to = 0.75, 0.75 \ max.size=0.1 \ distance.interface.materials=sio2 \ max.interface.size=0.025 \ max.interface.distance=0.5 Figure 5. Crop then mirrored process mesh, followed by mirrored device. The Simulation Standard Page 26 April, May, June 2015

27 Figure 6. Process mesh mirror then crop followed by device mesh mirror. Figure 7. Process mirror, crop, mirror followed by device mirror. will mirror the process, crop from the mirrored process structure, generate the device export, and then mirror that (Figure 6). Note: If process.ops.order is not specified, we crop then mirror by default. We can also apply the mirroring string multiple times, for example: export victory(delaunay) name= structure_f \ mirror.process= x mirror.device= +x \ crop.from = 0.5, \ 0.25 crop.to = 0.5, 0.75 \ process.ops.order = \ mirror crop mirror \ max.size=0.1 \ distance.interface.materials=sio2 \ max.interface.size=0.025 \ max.interface.distance=0.5 Conclusions The mirroring operation can be used to mirror the process and/or device mesh. It is a powerful export operation that greatly minimizes the runtime of the process stage of a simulation. In cell mode, it can also be used in combination with the crop/slice operation to generate array type structures from smaller subsections of the process mesh. will mirror the process mesh, crop it, mirror it again, generate the device mesh, and then mirror it. The mirroring string used during the process will be -x, while that for the device is +x. Figure 7 shows an example. Call for Questions If you have hints, tips, solutions or questions to contribute, please contact our Applications and Support Department Phone: +1 (408) Fax: +1 (408) support@silvaco.com Hints, Tips and Solutions Archive Check out our Web Page to see more details of this example plus an archive of previous Hints, Tips, and Solutions April, May, June 2015 Page 27 The Simulation Standard

28 USA Headquarters: Silvaco, Inc Patrick Henry Drive, Bldg. 2 Santa Clara, CA USA Phone: Fax: sales@silvaco.com Worldwide Offices: Silvaco Japan jpsales@silvaco.com Silvaco Korea krsales@silvaco.com Silvaco Taiwan twsales@silvaco.com Silvaco Singapore sgsales@silvaco.com Silvaco Europe eusales@silvaco.com The Simulation Standard Page 28 April, May, June 2015