Run-Time Energy Estimation in System-On-a-Chip Designs *

Transcription

1 Run-Tme Energy Estmaton n System-On-a-Chp Desgns * J. Had, G. Kaefer, Ch. Steger, R. Wess Insttute for Techncal Informatcs Graz Unversty of Technology Graz, Austra Abstract - In ths paper, a co-processor for run-tme energy estmaton n system-on-a-chp desgns s proposed. The estmaton process s done by usng power macro-models, thus makng analogue measurement equpment obsolete to the software engneer once the system-on-a-chp (SOC) desgn s characterzed. Compared to samplng-based proflng systems [17], the performance overhead of energy proflng s less, because the energy estmaton s done completely parallel to the functonal unts resdng on the SOC. The proposed methodology can be used for run-tme power optmzaton and n-system energy proflng. The co-processor was evaluated on a SOC for MPEG layer III audo decodng and the expermental results show a maxmum relatve error of <5%. E Power Manager Int Start Energy Montorng Power Management Polcy Stop Energy Montorng Get Energy Profle I. Introducton Fast tme to market and low energy consumpton are major requrements for system-on-a-chp (SOC) desgns developed for use n moble applcatons as well as other embedded systems. The technologcal trends towards hgh-level ntegraton and ncreasng performance, combned wth the demand for energy-effcent system desgn, drve the development of energy estmaton schemes. In large VLSI crcuts, such as System-On-a-Chp (SOC), t s often dffcult to perform a run-tme energy estmaton of sngle functonal unts resdng on the chp. Several approaches exst for smulatng the energy consumpton by usng netlst smulators [9], nstructon set smulators [4], and emprcal methods [3]. In most cases these smulatons rely ether on an extensve pre-characterzaton effort or the need of hardware netlsts, mostly not avalable to applcaton engneers. The goal of the presented work s to support the development of () energy-effcent software and () power management polces wthout sufferng from a sgnfcant amount of performance. Ths wll lead to the desgn of more power-aware electronc systems meetng the tght constrants on energy consumpton of battery-powered moble systems, such as moble phones and PDAs. The major contrbutons of our work are: () development of a co-processor for energy proflng n embedded systems, () run-tme energy proflng wth mnmal mpact on the overall performance. The JouleDoc (JD) co-processor performs an energy estmaton of the entre SOC by energy accountng. In contrast to exstng estmaton schemes, the does the run-tme energy estmaton n parallel and makes any addtonal analogue measurement *Ths work was supported n part by austramcrosystems AG, Austra. Insttute for Techncal Informatcs Evaluaton of Polcy and Optmzaton t SOC Fg. 1. A scenaro usng the for run-tme optmzaton of the power management polcy. equpment obsolete after the one-tme characterzaton process s done. The energy estmaton s done n parallel to the other components of the SOC, and a few nstructons are requred to perform energy proflng. The provdes sngle nstructons for startng and stoppng the energy estmaton of the entre SOC whle a further sngle nstructon performs energy estmaton. Therefore the performance overhead of energy proflng s kept to a mnmum. Fg. 1 shows how a power manager s able to use the JD co-processor for optmzaton of ts polcy [1] by permanently trackng the mpacts of the power manger s decsons on the SOC. The remander s organzed as follows: n Secton 2, related work s descrbed. Secton 3 presents the methodology and mplementaton of the. In Secton 4 the evaluaton of the s done by nvestgatng an MPEG Layer III audo decoder. Secton 5 concludes and dscusses future work. II. Related Work Whle tradtonal proflng tools [17] gather program statstcs n order to ad the software developer n optmzng the performance of the program, new tools are requred to meet the needs of energy proflng systems [5] on electronc devces wth lmted energy resources. For effectve

2 proflng accurate and fast energy estmatons are necessary. Varous technques based on nstructon-level characterzaton and smulaton of the underlyng hardware have been proposed [8], [12]. Instructon-level power analyss, frst proposed by Twar et. al. [6], reles on a base-cost model. The base-cost model s determned by runnng each nstructon or short sequence of nstructons n a loop and measurng the current/power consumpton. Instructon-by-nstructon energy costs are pre-characterzed for each target processor. For energy estmaton on nstructon-level, nstructon-set-smulators (ISS) are extended wth energy models, as proposed n [4]. ISS have the dsadvantages that they can execute only a lmted number of nstructons per second and often cannot be used for smulatng complete SOC desgns, because of smulaton tme. HW/SW co-smulators have been proposed [9] to reduce smulaton tme. In [7] the authors present a run-tme power estmaton methodology whch makes use of on-chp hardware counters. Hardware counters for trackng events are already ntegrated n commercal processors [18] prmarly targeted for performance proflng [17]. The proflng process s based on system-wde samplng whch s done by stoppng the processor after a pre-specfed amount of tme or after a specfed number of processor events. Our approach dffers from [7] n three ponts: () the presented energy accountng hardware s not samplng-based and therefore does not nterrupt the software runnng on the SOC, () the co-processor estmates the energy consumpton n hardware savng overhead n terms of performance and code sze, () the co-processor s desgned for use n embedded systems wth no hgh performance processors avalable. A. Power Macro-Modelng III. JD Co-processor Modern SOC desgns offer a varous number of possbltes to reduce the energy consumpton durng run-tme. Energy estmaton s an mportant technque to evaluate the effectveness of the mplemented power aware features. As energy estmaton of a SOC at gate level or even below s not practcable, abstracton layers of the system are ntroduced, such as the nstructon-level of a processor. These abstracton levels allow the use of power macro-modelng as the fundamental theory for power estmaton. Macro-modelng has already been used for RT-level hardware power analyss [10], [13], [16], [19]. Macro-modelng refers to the pre-characterzaton of a comprehensve set of gates, and the computaton of ts power dsspaton and delay usng ether smulaton or emprcal methods. Power models for macro-blocks also utlze sgnal statstcs at the boundares of the macro-blocks, ncludng bt-level statstcs such as sgnal probabltes, transton probabltes, and spatal/temporal correlatons [9]. For a set of macro-blocks M buldng a system S, the power consumpton wll be gven by (1), where E SAVG denotes the average energy consumpton of S, and E k the average energy consumpton of the k-th macro-block as a functon of ts current state. Accurate E k are determned by analyss of the macro-block, as done for mcro-processors n [6], [7]. E SAVG = Ek sm ) k k ( (1) B. Power Macro-Models for Power Estmaton of SOC Desgns A system-on-a-chp s a large VLSI crcut bult of dfferent analogue and dgtal components. For energy proflng the software desgner s mostly nterested n the energy consumpton of each component on ts own. For processor macro-modelng the nstructon set s mostly used an abstracton layer, because ISS are avalable and can be extended wth energy values. Whle most energy estmaton tools, lke ISS, are mplemented by people not nvolved n the hardware desgn process, the more effectve way s to nclude the prncples of macro-modelng n the hardware desgn flow. The component s desgner mostly carres out numerous energy-related smulatons at desgn tme, leadng to a more sophstcated defnton of the energy-crtcal spots. Whle analogue smulaton on component-level s possble, t cannot be done for large SOC n a reasonable tme. Incorporatng the energy related nformaton at component-level leads to a bottom-up method contrary to other power estmaton tools whch flatten the desgn before analyss and re-structure the results after smulaton has fnshed. Furthermore, for the applcaton engneer ths granularty at component-level s comprehensble, and optmzatons can be done by reducng the energy consumpton component by component. C. Implementaton The (Fg. 2) wll be used for run-tme energy analyss, proflng and montorng of electronc systems. The co-processor s a sensor system wth a control logc block to allow confguraton and data transfer from/to the host controller. The prmary desgn goal s to provde a tool wth nearly no performance overhead. C.1 JD Energy Sensors The sensors wthn the are called JD energy sensors. Based on exstng macro-models, the sensors count the occurrence of pre-specfed operatng condtons. Wthn the power macro-model dfferent operatng states (see secton III.A) are assocated to certan energy consumpton values. Therefore, one can compare the JD energy sensors wth small energy meters avodng analogue crcuts.

3 event trgger Regster Set accumulator status regster Event Counter 0 ncrement value Event Counter 1 ncrement value Logc Interface confgurejdprocessor(); //done once at startup _startenergyestmaton; { //program to be energy estmated } _stopenergyestmaton; _calculateenergy; //estmaton s done n parallel and //requres 2*(number of JD energy sensors) cycles _readenergyvalue; event trgger event trgger Event Counter n ncrement value Fg. 2. Block dagram of the. The average energy consumpton E Mavg of a macro-block s gven by (2) where n denotes the number of occurrences of the operatng condton S, E the energy consumpton of the macro-block dependent on the operatng condton s, and s the number of dfferent operatng condtons for the macro-block M. E = n E( s ) (2) Mavg C.2 JD Logc The co-processor mplements a small nstructon set for data transfer and confguraton tasks. Startng and stoppng the energy estmaton process s done by sendng a sngle nstructon to the co-processor. The s equpped wth a general synchronous 32-bt nterface. For specfc host processors an nterface wrapper must be mplemented. Energy estmaton of the whole SOC can be performed by a dedcated read and accumulate nstructon, whch adds the values of all counters n an accumulaton regster. The program n pseudo-code (Fg. 3) shows the low overhead n lnes of code that s requred to perform run-tme energy estmaton. Except for the routne confgurecounters() all commands are sngle 16-bt nstructons. The calculaton of the energy s done n parallel and requres 2*(number of ntegrated sensors) cycles; therefore, the host controller needs no addtonal program code for calculatng the energy, compared to e.g. [7], and s able to run other tasks wthn ths tme. The current mplementaton of a JD energy sensor requres 2100 gates and the control logc 3200 gates on an average 0.35µ process. The gate-count s domnated by the number of regsters for storng adder values and accumulated data, whch may be avoded by mplementng an optmzed memory system storng confguraton and ntermedate data. Fg. 3. Pseudocode for run-tme estmaton. All commands are sngle nstructons except the confguraton routne confgurejdprocessor(). D. Energy Estmaton Usng FPGA-based Prototypng Whole system evaluaton s often done on prototype boards equpped wth large FPGAs. Emulaton wth FPGAs s often used to provde nearly at-speed verfcaton. However, emulaton has several problems. A major problem s that FPGA s technology energy characterstcs make t mpossble to gve accurate estmates of energy consumpton for the eventual system fabrcated n slcon. Other problems are long comple tmes, hgh costs, and performance. Nevertheless, FPGAs are ganng more and more mportance n the desgn flow. Once the desgner decdes to use FPGA technology for functonal verfcaton, the energy estmaton can also be done functonally. In many cases the macro-models of the components can be bult upon avalable nformaton from data sheets, testchps, or smulatons. Assumng the macro-models of the components exsts, the desgner must confgure the related JD energy sensors, denoted as E(s ) n (2), and s able to perform energy analyss of the SOC n the prototypng phase wthout havng the SOC avalable on slcon. IV. Results A. Power Macro-Models for a Multmeda SOC Desgn For evaluaton of the we use a SOC [21] that s thought to be an extenson of portable devces lke moble phones, electronc organzers, or standalone battery-powered musc players. The SOC (Fg. 4) conssts of an RISC processor by ARC [20], an audo-subsystem, a memory system, and several nterfaces. The processor s provded as a soft-macro n VHDL whch offers us a wde range of possbltes for defnng the processor s power-macro model. An audo subsystem s ncluded on the chp as well as several nterfaces to the PC, USB, SPI, and MultMedaCard.

4 Memory System ARC Core Interfaces (USB,SPI,...) Interface- System MMC Card IF MultMedaCard MP3 Data IF Σ s 18 Bt 18 Bt Audo Subsystem Audo AMPs Fg. 4. Block dagram of the multmeda SOC for evaluaton of the JD co-processor[21]. For energy estmaton we characterzed the ARC processor ncludng the dfferent memores (XY, RAM, I-cache) at dfferent avalable clock speeds of the on-chp PLL. Furthermore, the MultMedaCard and Audo-Subsystem were descrbed. The macro-model of the SOC conssts of the followng parameters: number of nstructon fetches cycles, cache msses, store and load operatons, ppelnes stalls (all of ARC core), MMC load and store accesses, and samplng rate and volume of the audo-subsystem. The energy consumpton s a functon of the systems operatng frequency f and the volume v of the audo subsystem. E S (f) = E CPU + memores (f) + E Audo (f,v) + E MMC (f) (4) The s mapped nto the memory space of the processor by usng the auxlary regster set (AUX regsters), provded by the ARC core. The AUX regsters are smple synchronous 32-bt regsters desgned for nterfacng the ARC to further components. B. Energy Analyss of MP3 Audo Decodng Usng an FPGA Prototypng System The dgtal part of the SOC ncludng the s syntheszed to a XILINX Vrtex [14] FPGA whle the analogue subsystem s avalable as a sngle testchp and connected to the FPGA (Fg. 5). The power values have been gathered by analyss of exstng testchps. Fg. 5. Expermental setup. The FPGA s used for emulaton of the dgtal part of the SOC ncludng the. The s evaluated by runnng the MPEG Layer III [15] audo decoder software on the SOC. The decodng algorthm conssts of three blocks: frame unpackng, reconstructon, and nverse mappng. The frst step s the synchronzaton and readng of the frame header followed by frame decodng. Requantzaton, stereo processng, f applcable, s done before applyng the nverse modfed cosne transformaton (IMDCT) and the polyphase synthess flterbank. The frames are loaded from the MMC va a FIFO. The PCM audo samples are also wrtten onto the audo subsystem usng a FIFO. The experments are done on audo fles wth 48kHz, 44kHz, and 32kHz samplng rate, usng a btrate of 128 kbts/sec. Fg. 6 shows the energy consumpton of the SOC whle playng 1 second of a MPEG Layer III fles kHz 44kHz 32kHz Audo MMC Proc.+Mem. Fg. 6. Estmated energy consumpton for playng 1 second of MPEG Layer III fle. Table 1 shows the results of the energy estmaton for each subroutne. Therefore the commands for startng and stoppng the JD energy sensors are placed nearby the subroutne calls. As these commands consst of only two assembler-code lnes the nfluence on the algorthm s mnmal. The MMC s and audo subsystem s energy consumpton s not taken nto account for ths analyss, because they do not drectly nfluence the subroutnes. TABLE 1 ENERGY ESTIMATIONS OF THE ARC CORE BY THE JD CO-PROCESSOR FOR SINGLE SUBROUTINES OF THE MP3 AUDIO DECODER. 48kHz 128 kbt/s 44kHz 32kHz GetScaleFactors 0,0141 0,0124 0,0139 Stereo 0,0250 0,0229 0,0242 Reorder 0,0366 0,0320 0,0335 Antalas 0,0604 0,0551 0,0577 HuffmanDecode 0,1025 0,0970 0,1023 DequantzeSample 0,1619 0,1478 0,1561 Hybrd 0,3723 0,3446 0,3588 SubBandSynthess 0,8708 0,8029 0,8470

5 TABLE 2 RELATIVE ERROR OF ESTIMATED ENERGY CONSUMPTION OF JD CO-PROCESSOR COMPARED TO TESTCHIP MEASUREMENTS. 48kHz 128 kbt/s 44kHz 32kHz GetScaleFactor -1,63-0,31-0,15 Stereo 1,09 2,47 3,77 Reorder 1,16 0,95 2,44 Antalas -0,22 1,96 2,10 HuffmanDecode -4,84-3,92-3,67 DequantzeSample 1,79 2,84 4,52 Hybrd -3,62-4,55-2,68 SubBandSynthess 2,28 4,33 3,52 The accuracy of the energy estmatons of the JD s determned by analyzng several subroutnes of the MP3 decoder. Table 2 shows the relatve error of the estmated energy consumpton compared to emprcal measurements done wth a multmeter (runnng the subroutnes n loops). The relatve error of the estmaton results s wthn a range of ±5% compared to the actual energy consumpton. In our opnon ths s accurate enough for the evaluaton of power management polcy strateges durng run-tme and source code optmzatons at the software development phase. An addtonal pont of nterest nvolves the overhead of the co-processor n terms of gate-count resp. area. Therefore, the co-processor has been syntheszed usng an avalable 0,35µm process [21]. The equpped wth 8 JD energy sensors requres about gates whch results n an area of approxmately 1mm 2 on the chp. A reducton of the area can be obtaned by usng an optmzed regster fle nstead of unstructured sequental logc. V. Concluson Tme-to-market constrants and the ncreasng number of SOC-based moble electronc devces requre new methodologes for energy estmaton. In ths paper we have presented the mplementaton of the delverng run-tme energy estmatons usng the macro-modelng approach. The can be used for supportng the power manager s decsons durng run-tme and offers the possblty to contnuously montor the energy consumpton wthout losng a sgnfcant amount of performance. The experments wth a SOC for audo decodng have shown a maxmum relatve error of 5% whch makes the applance and evaluaton of power-aware strateges [2] practcable. Future work wll nclude both mplementng power managers that explot the permanent nformaton of the energy consumpton for optmzng the polcy as well as nvestgatng possbltes to reduce the sze of the JD co-processor. VI. References [1] L. Benn, A. Boglolo, G.A. Paleologo and G. De Mchel, Polcy optmzaton for dynamc power management, IEEE Trans. on Computer-Aded Desgn, Vol. 18, No. 6 (1999), pages [2] L. Benn and G. de Mchel, System-Level power optmzaton: Technques and Tools, ACM Transactons on Desgn Automaton of Electrc Systems, Vol. 5, No. 2, Aprl [3] J. Flnn and M. Satyanarayanan, PowerScope:A Tool for Proflng the Energy Usage of Moble Applcatons, In Proc. 2nd IEEE Workshop on Moble Computng Systems and Applcatons, pp.23 30, [4] T. Smunc, L. Benn, G. De Mchel, Cycle-Accurate Smulaton of Energy Consumpton n Embedded Systems, In Proc. Desgn Automaton Conference, pp , [5] T. Smunc, Energy Effcent System Desgn and Utlzaton, PhD-Thess, Stanford Unversty, 2001 [6] V. Twar, S. Malk, A. Wolfe, Power Analyss of Embedded Software: A Frst Step Towards Software Power Mnmzaton, IEEE Transactons on VLSI Systems, vol. 2, no.4, pp , December [7] Russ J. and M. Martonos, Run-Tme Power Estmaton n Hgh Performance Mcroprocessor, In Proc. Internatonal Symposum on Low Power Electroncs and Desgn, pp , August [8] T. Sato, Y. Ootaguro, M. Nagamatsu, and H. Tago, Evaluaton of archtecture-level power estmaton for CMOS RISC processors, In Proc. Symp. Low Power Electroncs, pages 44 45, Oct [9] M. Lajolo, et.al., Effcent Power Estmaton Technques for HW/SW Systems, In Proc. Proc. Desgn Automaton and Test Europe (DATE), March [10] J. Rabaey and M. Pedram (Edtors). Low Power Desgn Methodologes. Kluwer Academc Publshers, Norwell, MA, [11] Snha A., et.al., JouleTrack - A Web Based Tool for Software Energy Proflng, In Proc. Desgn Automaton Conference, Las Vegas, Nevada, USA, June [12] C-T Hseh, L-S. Chen, and M. Pedram, Mcroprocessor power analyss by labeled smulaton, Proc. of Desgn Automaton and Test n Europe, Mar. 2001, pp [13] Q. Qu, Q. Wu, and M. Pedram, Cycle-Accurate MacroModels for RT-Level Power Analys, Proceedngs of 1997 Internatonal Symposum on Low Power Electroncs and Desgn, pp , August [14] XILINX Inc. [15] ISO/IEC JTC 1/SC 29/WG Informaton Technology Codng of movng pctures and assocated audo for dgtal storage meda up to 1.5 Mbt/s Part 3: Audo. Internatonal Organzaton for Standardzaton, November [16] Q. Wu, C. Dng, C. Hseh, and M. Pedram, Statstcal Desgn of Macro-models For RT-Level Power Evaluaton, In Proc. of the Asa and South Pacfc Desgn Automaton Conference, pp , January [17] VTUNE Performance Analyzer. Intel Corporaton, [18] The IA-32 Intel Archtecture Software Developer s Manual, Volume 3: System Programmng Gude. Intel Corporaton, [19] L. Benn, D. Brun, M. Chnos, C. Slvano, V. Zaccara, R. Zafalon, A Power Modelng and Estmaton Framework for VLIW-based Embedded Systems," In Proc. Int. Workshop on Power And Tmng Modelng, Optmzaton and Smulaton PATMOS, September [20] ARC Internatonal. [21] austramcrosystems AG.