System-on-Chip Design Analysis of Control Data Flow. Hao Zheng Comp Sci & Eng U of South Florida

Transcription

1 System-on-Chp Desgn Analyss of Control Data Flow Hao Zheng Comp Sc & Eng U of South Florda

2 Overvew DF models descrbe concurrent computa=on at a very hgh level Each actor descrbes non-trval computa=on. Each actor s oben descrbed n C. Can be mapped to ether HW or SW Wll look at ssues n mappng C to HW. 2

3 Data & Control Edges of C Programs C s used as a modelng as well as an mplementa=on language. Mappng C programs to HW s hard. HW s parallel whle C s sequen=al. need to understand the structure of C programs. Rela=ons between opera=ons n C programs Data edges: data moved from one op. to another. Control edge: no data xfer. 3

4 Control Flow Graph nt x(a, b) { nt r; 2 f (a > b) 3 r = a; else 4 r = b; 5 return r; } nt max(nt a, b) f (a > b) r = a return r; Control Edges r = b Control edges are oben labeled wth cond=ons whose sa=sfac=on dctates f a control can be taken. 4

5 Data Flow Graph Data Edges nt max(nt a, b) { nt r; 2 f (a > b) 3 r = a; else 4 r = b; 5 return r; } a, b a 2 (a>b) 3 4 r r 5 b Data edges are labeled wth varables upon whch one opera=on depends on another 5

6 Control/Data Edges A data edge => flow of nforma=on Must be mplemented. A control edge => result of seman=cs of program language Maybe gnore or changed f the behavor remans the same. 6

7 Control/Data Edges Control Edges Data Edges Hardware Implementaton nt sum(nt a, b, c) { nt v; v = a + b; // op 2 v2 = v + c; // op 3 return v2; } 2 3 a, b v v2 2 3 c a b c v adder adder 4 4 v2 Control edges are meanngless as HW s parallel. 7

8 Control/Data Edges Example nt sum(nt a, b, c, d) {// op nt v; v = a + b; // op 2 v2 = c + d; // op 3 return v + v2; // op 4 } 8

9 Basc Elements of CFG 2 3 for (=0; < 20; ++) { // body of the loop } entry 2 3 ext body 9

10 of CFG f(a < b) { // true branch } else { // false branch } entry true false ext 0

11 of CFG whle (a < b) { // loop body } entry ext body

12 of CFG do { // loop body } whle (a<b) entry body ext 2

13 of CFG: GCD : nt gcd(nt a, nt b) { 2: whle (a!= b) { 3: f (a > b) 4: a = a - b; else 5: b = b - a; } 6: return a; } A control path n CFG corresponds to a sequence of execu=ons of statements 3

14 of DFG: GCD : nt gcd(nt a, nt b) { 2: whle (a!= b) { 3: f (a > b) 4: a = a - b; else 5: b = b - a; } 6: return a; } 2 (a!=b) 3 a, b 6 CFG a (a>b) 4 5 b 4 5 Par=al DFG 4

15 of DFG: GCD : nt gcd(nt a, nt b) { 2: whle (a!= b) { 3: f (a > b) 4: a = a - b; else 5: b = b - a; } 6: return a; } a a, b a a b a a, b a a, b b b a, b b 6 a 5

16 of CFG/DFG 2a : nt L[3] = {0, 20, 30}; 2a 2b 2c 2: for (nt =; <3; ++) 3: L[] = L[] + L[-]; 2b ext How to treat ndexed varables n DFG construc=on? 3 2c CFG 6

17 of CFG/DFG a b 2a 2a 2b 2b L L[0], L[], L[2] 2c 3 2c 3 L L[] Treat L as a sngle monolthc varable Loca=ons of L are treated ndvdually 7

18 of CFG/DFG a b 2a 2a 2b 2b L L[0], L[], L[2] 2c 3 2c 3 L L[] L[2] Treat L as a sngle monolthc varable Loca=ons of L are treated ndvdually 8

19 DFG Analyss Loop Unrollng nt L[3] = {0, 20, 30}; L[] = L[] + L[0]; L[2] = L[2] + L[]; 9

20 C to HW Assump=ons: Scalar C programs no ponters and arrays Implement each statement n a clock cycle. Basc Idea Construct CFG and DFG CFG => controller (control edge -> control sg.) DFG => datapath (data edges -> comp conn.) Not very effcent exst many op=mza=on opportun=es 20

21 HW RTL Archtecture Control Inputs Control Sgnals Data Inputs Controller Datapath Control Outputs Status Sgnals Data Outputs 2

22 C to HW: Buldng Datapath Each varable => a regster MUX s used f a varable s updated n mul=ple statements. Each expresson => a combna=onal logc Cond=onal expressons => flags to controller Datapath crcuts and regsters are connected accordng to data edges n DFG. 22

23 C to HW: Buldng Datapath : nt gcd(nt a, nt b) { 2: whle (a!= b) { 3: f (a > b) 4: a = a - b; else 5: b = b - a; } 6: return a; } a-b - - a n_a upd_a upd_b!= n_b b b-a flag_whle > out_a flag_f 23

24 C to HW: Buldng Controller _ / run s s2! flag_whle / _ s6 Label CFG edges wth flags from datapath and ac=ons that DP should perform, and mplement CFG as FSM. _ / run4 flag_f / _ s4 s3 _ / run5 flag_whle / _! flag_f / _ s5 24

25 C to HW: Buldng Controller flag_whle flag_f state n_a n_b Next-state Logc Datapath flag_whle flag_f upd_a upd_b Lookup Table command {_, run, run4, run5} nstructon upd_a upd_b out_a _ run run4 run5 a a_n a - b a b b_n b b - a upd_a upd_b 25

26 Each varable mapped to a regster. A func=onal unt s allocated to every operator. Performance bojleneck as a sngle statement s executed n a sngle clock cycle. Processor s already dong ths. Can mul=ple statements be executed n a cycle? 26

27 C to HW: Sngle-Assgnment Form Each varable s assgned exactly once. To mprove effcency of the HW mplementa=on. a = a + ; a = a * 3; a = a 2; a2 = a + ; a3 = a2 * 3; a4 = a3 2; 27

28 C to HW: Sngle-Assgnment Form nt gcd(nt a, b) { whle (a!= b) { f (a > b) a = a b; else b = b a; } return a; } nt gcd(nt a, b) { whle (merge(a, a2)!= merge(b, b2)) { a3 = merge(a, a2); b3 = merge(b, b2); f (a3 > b3) a2 = a3 b3; else b2 = b3 a3; } return a; } 28

29 C to HW: Sngle-Assgnment Form a b nt gcd(nt a, b) { whle (merge(a, a2)!= merge(b, b2)) { a3 = merge(a, a2); b3 = merge(b, b2); f (a3 > b3) a2 = a3 b3; else b2 = b3 a3; } return a; } a3 > flag_whle!= flag_whle - - b3 a2 b2 29

30 Readng Gude Chapter 4, the CoDesgn book. 30