ABCD: Booleanizing Continuous Systems for Analog/Mixed-Signal Design, Simulation, and Verification

Transcription

1 ABCD: Booleanizing Continuous Systems for Analog/Mixed-Signal Design, Simulation, and Verification Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert Brayton, and Jaijeet Roychowdhury EECS Dept., The University of California, Berkeley TAU 2014, Santa Cruz 1/19

2 The Problem: AMS Verification Example: SERDES PLL CDR Analog parts I/O Surrounded by Digital Logic Want to verify complete system >1V e.g., eye opening height > 1V? Proof or counter-example needed 2/19

3 Our approach: Booleanize the analog parts Challenge: ABCD: AnalogBoolean models + Digital models (don't mix) approximation ALL Continuous Boolean BOOLEAN Best verification tools = all Boolean, no continuous SAR-ADC Boolean T/H approximation Analog components Boolean comparator approximation Boolean DAC approximation Digital components Verification tools accept Fast Formal verification, high-speed simulation, test pattern generation,... for the full combined system! 3/19

4 ABCD: Boolean, but Accurate What is accurate Booleanization? disc. o/p disc. i/p disc. time Boolean Logic discretized ckt. signals Boolean state More bits, better accuracy 4/19

5 Prior work: ABCD-L (DAC 2013) Linear Analog Circuit ABCD-L Purely Boolean Model Works only for linear systems! Example: Channel + Equalizer Linearize Bit Sequence 5/19

6 Introducing ABCD-NL Non-Linear Analog Circuit ABCD-NL Purely Boolean Model Rest of this talk 1 How ABCD-NL works 2 Results: Charge pump, ADC, DAC, etc. 3 End user applications High-speed simulation, formal verification, test pattern generation, etc. for non-linear AMS ckts. 6/19

7 ABCD-NL Models are FSMs Non-Linear Analog Circuit ABCD-NL Purely Boolean FSM Model Finite number of states Arcs denoting state transitions Each arc: ip/op pair Purely Boolean form /19

8 Key idea: DC, TRAN FSM states 1 0 DC TRAN Non-Linear Analog Circuit Eventually settles and never changes (DC input DC output) Starts at DC0 and eventually settles at DC1 1 DC FSM states w/ loops Multiple such DC states Capture different DCOPs DCOPs don't change instantly TRAN FSM states Between each pair of DC states Purely Boolean Model 8/19

9 Booleanizing a Charge Pump (1/3) 1 Do SPICE simulations Active Discretize Vup, Vdown using 1 bit each, Vout using 5 bits UP high DOWN low UP low DOWN high Exactly 1 high at any time Both high Both low Dormant 9/19

10 Booleanizing a Charge Pump (2/3) 2 Analyze SPICE waveforms Build Analog Transition Table TRAN path DC3 to DC2: up (down) goes 1 0 (0 1) Total time 20.63ns, o/p 31, becomes 213.6ps,. 10/19

11 Booleanizing a Charge Pump (3/3) 3 Analog Transition Table Boolean Model disc. o/p disc. i/p <ipbv> <cstbv> <opbv> <nstbv> Combinational Logic Registers disc. time Boolean state i/p: 2-bit encoding o/p: 5-bit encoding 32 levels in [0, Vdd] FSM state: 19 bits Lots of don't cares (75%) 11/19

12 ABCD-NL: The 3-Step Algorithm 1 Do SPICE simulations 2 Analyze SPICE waveforms Build Analog Transition Table 3 Analog Transition Table Boolean Model 12/19

13 Simulating the Boolean Model i/p waveform Discretize into FSM symbols Simulate FSM (Fast, Table-lookup) Map back to analog 13/19

14 Charge Pump: Long PRBS Non-linear analog dynamics accurately captured over long time-frame ~10x Speedup, even in Python 14/19

15 Circuits Successfully Booleanized Delay line Charge pump Equalizer Power grid I/O signaling system SAR-ADC 15/19

16 AMS Verification: The Flow AMS System to be verified Boolean Model via ABCD-NL Proof or Counter example ABC Property to be verified Booleanize (manually) Safety vs Liveness Booleanize (manually) Input Constraints 16/19

17 Example: Verifying a Signaling System What is the max bitrate that can be sustained? Ans: 2.56Gbps ABCD model ABC Specification verification engine (Bob Brayton's group) 17/19

18 Summary AMS modelling, verification a challenge: 20% bugs Our approach: Booleanize AMS Components ABCD-L: for linear AMS systems ABCD-NL: for non-linear systems Applied to A/D and D/A converters, delay lines, charge pumps, equalizers, filters, on-chip power grids, etc. Accurate and Scalable Applications High-speed simulation Formal verification (in conjunction with ABC) 18/19

19 Questions 19/19