FLAME, a new readout ASIC for the LumiCal detector

Transcription

1 FLAME, a new readout ASIC for the LumiCal detector Jakub Moroń AGH-UST M. Firlej, T. Fiutowski, M. Idzik, K. Świentek Students: Sz. Bugiel, R. Dasgupta, M. Kuczyńska, J. Murdzek On behalf of FCAL Collaboration Faculty of Physics and Applied Computer Science AGH University of Science and Technology, Krakow, Poland CLIC Workshop 2016, January 2016, CERN

2 Agenda 1. LumiCal dedicated luminosity calorimeter LumiCal readout chain 2. FLAME FcaL Asic for Multiplane readout Chip and channel architecture 3. FLAME blocks development in CMOS 130 nm Front-end Fast multichannel 10-bit SAR ADC 4. FLAME current development in CMOS 130 nm 8-channel FLAME v0 prototype (not yet complete) Fast serializer 5. Summary and future plans 2/16

3 LumiCal dedicated luminosity calorimeter Dedicated luminosity calorimeter LumiCal: Old readout board 4 x 8-channel ASICs 2 barrels on opposite sites of main detectors system Each barrel 30 layers of tungsted + silicon detectors Each layer 12 sensors with 4 sectors each Each sector divided into 64 radial pads 3072 channels on single layer channels on the entire barrel 3/16

4 LumiCal readout chain Existing (old) LumiCal detector readout comprises: 8 channel front-end ASIC with preamp & CR-RC shaper, Tpeak~60ns, ~9mW (AMS 0.35um) 8 channel pipeline ADC ASIC, Tsmp<=25MS/s, ~1.2mW/MHz (AMS 0.35um) FPGA based data concentrator and further readout New development for LumiCal detector readout: 16 channel FLAME ASIC comprising all functionalities Front-end & ADC in each channel + fast serializer + biasing DACs + slow control, etc. New FPGA based DAQ 4/16

5 FLAME FcaL Asic for Multiplane readout ASIC architecture Complete readout ASIC integrating whole functionality (biasing, calibration, etc.) 16 mix-mode channels comprising: Variable gain front-end 10-bit SAR ADC Data encapsulation and 8b/10b coding (according to the Xilinx MGT specification) DLL for clock alignment (for synchronous sampling) Multi-phase PLL based fast serializer (up to 10 Gbps) Fast SST driver (up to 10 Gbps) 5/16

6 FLAME FcaL Asic for Multiplane readout Channel architecture Analogue front-end comprising: Charge sensitive preamplifier with variable gain High gain MIP sensitivity for calibration Low gain for shower development (up to 6 pc) Differential CR-RC shaper with 50ns peaking time Krummenacher feedback and pedestal trim DAC 10-bit multichannel SAR ADC Sampling rate up to 40 MSps DNL, INL < 0.75 LSB ENOB > 9 Ultra low power consumption (below 1 mw per channel at 40 MSps) 6/16

7 FLAME blocks development in CMOS 130 nm Prototype front-end Design specs: Measurements: 8 channels Fully functional Cdet 5 50pF Tpeak 51 ns 1st order shaper (Tpeak 50 ns) Calibration gain 4.1 mv/fc Variable gain: linear range ~60 fc calibration mode - MIP sensitivity ENC 930 e physics mode - input charge up to ~6 pc Physics Power pulsing implemented gain 105 mv/pc Linear range ~2.7 pc (saturates >5pC) Power consumption ~1.5 mw/channel M. Firlej, T. Fiutowski, M. Idzik, J. Moroń, K. Swientek, P. Terlecki Development of front-end electronics for LumiCal detector in CMOS 130 nm technology, JINST 10 C01018, January /16

8 FLAME blocks development in CMOS 130 nm Fast multichannel 10-bit SAR ADC Design consideration: Technology CMOS 130 nm 8 SAR ADC channels Power scalable with sampling frequency (up to >40 MS/s) Power cons. <1mW@40MS/s Power pulsing (no clk=no power) Architecture of 10-bit SAR ADC Differential segmented/split DAC with MCS switching scheme ultra low power Dynamic comparator no static power consumption, power pulsing (no clk=no power) Asynchronous logic no clock tree, power saving, fast 146 μm 600 μm 8/16

9 FLAME blocks development in CMOS 130 nm Readout of multichannel ADC Specifications & main features: 10b Multimode multiplexer/serializer: Serial mode: one output per all channels (double serialization: 10-bit x 8 channels) Additional test modes, with counters / pseudorandom data instead of ADC output, to verify serialization / transmission PLL for data serialization SAR 0 SAR 6 SAR 7 adc_clk Power pulsing serializer 10b serializer pser_clk fser_clk fadc_clk = f pser_clk 8b 8b data 0 1b data 6 7 data 7 8 start frame = f SLVS 6 serializer 1 80 fser_clk 1b 10b 10b 8b High speed SLVS interface (>1GHz) 1b serializer Parallel mode: one output per channel (10-bit serialization with faster clock) Single ADC mode: single channnel output... 10b 10b 9 1b SLVS data 8 data 9 (start frame) M. Firlej, T. Fiutowski, M. Idzik, J. Moroń, K. Swientek, Development of scalable frequency and power Phase-Locked Loop in 130 nm CMOS technology, JINST 9 C02006, February /16

10 FLAME blocks development in CMOS 130 nm Measurements of 10-bit SAR ADC Static performance example at 10MS/s Dynamic performance scan over fsample for fin at 0.1 Nyquist Very good ADC performance: INL,DNL < 0.5LSB and ENOB ~ 9.3 M. Firlej, T. Fiutowski, M. Idzik, Sz. Kulis, J. Moron, K. Swientek. A fast, ultra-low and frequency-scalable power consumption, 10-bit SAR ADC for particle physics detectors, 2015 JINST 10 P /16

11 Current development in CMOS 130nm 8-channel FLAME v0 and serializer ASICs Prototype ASIC comprising 8 almost fully functional FLAME channels: Front-end with variable gain charge preamplifier and differential CR-RC shaper, Tpeak = 50ns 10-bit multichannel SAR ADC Old backend same as already presented for ADC prototype Prototypes submitted on November 2015, should arrive to AGH-UST within couple of weeks... Prototype serializer ASIC comprising: Fast, ultra low power, ultra low jitter multi-phase PLL Fast serializer 22b 1b Fast SST driver 11/16

12 Current development in CMOS 130nm 8-channel FLAME v0 8-channel FLAME v0 prototype: Charge sensitive preamplifier: Cdet 5 50 pf Variable gain (calibration and physic mode) ENC 950 e- at Cdet = 20 pf in calibration mode Differential first order shaper (Tpeak 50 ns) Front-end power consumption 1.2 mw per channel 10-bit SAR ADC INL, DNL < 0.5 ENOB > 9.5 Power consumption 660 μw at 40 MSps Testing backend from ADC prototype (already presented) 2600 μm x 2000 μm Design submitted on November 2015, we hope to start tests in next few weeks... 12/16

13 Current development in CMOS 130nm Fast serializer FLAME serializer prototype: Ultra low power, ultra low jitter multi-phase PLL Output frequency range MHz 22 phases for serializer 22b 1b serializer with fast SST driver ( Gbps) Power consumption < 15 mw at 9.9 Gbps Test data generator 22-bit pseudo-random counter for eye diagram analysis 220-bit preset pattern (via slow control) constant during transmission one complete FLAME package 1250 μm x 1250 μm Design submitted on November 2015, we hope to start tests in next few weeks... 13/16

14 Summary and future plans Summary Prototypes of key FLAME blocks: Front-end, ADC, PLL, DLL designed, fabricated and tested 8-channel simplified FLAME v0 (80% functionality) + separate fast serializer with SST driver designed and submitted The chips should arrive in couple of weeks Future plans In case of positive test verification we plan a complete 16-channel FLAME submission before the end of Thank you for attention 14/16

15 FLAME blocks development in CMOS 130 nm Prototype front-end Two gain modes in Front-End: Position calibration with muons sensitivity for MIP (~4fC) high gain Luminosity measurement high energy particle electromagnetic shower charge deposition up to few pc low gain Gain 4.61 mv/fc Gain 113 mv/pc 15/16

16 FLAME blocks development in CMOS 130 nm Measurements of multichannel 10-bit SAR ADC Without PLL ENOB vs fsample for fin=0.2 Nyquist First results are approximate because: Setup not optimized for precise measurements FPGA readout not yet tuned for fast transmission (>150MHz internal FPGA delays should be set). Positive visual scope inspection done up to ~450MHz. With PLL ENOB vs channel at 10MS/s All 8 channels work well in parallel readout mode! 16/16