Trends and Challenges

Transcription

1 Trends and Challenges High accuracy is required in characterization, verification & signoff Increasing design complexities: -scale design ( ) using nano-scale technologies ( ) Shrinking design margins Reduced supply voltage ( ) vs. increased process variations ( ) Design Margin Supply voltage V DD Random Variation Global/local variation BTI-induced reliability RTN noise Static Noise Accurate device modeling & accurate circuit simulation is difficult but must 1 Designing & manufacturing for good PPA & yield is challenging (SRAM as an example)

2 Is Hitting A Wall Traditionally, designers have to use for large block & fullchip simulation & verification For advanced designs where accuracy is key, is hitting a wall due to its inaccurate & unpredictable results! Approximations in model calculation and matrix solving Low confidence (unconverged DC) & inaccurate/wrong simulation results Kirchoff s current law (KCL) usually broken No current traceability (missing info) & IDDQ check failure Complicated options & no easy use models Low confidence (unpredictable results) & wasted time on tuning/setup 2

3 Why Spice? A new class of simulator for emerging design challenges SPICE accuracy & compatibility, giga-scale capacity & speed Spice replaces in characterization, verification & signoff flows for accurate power/leakage/timing/noise Accuracy (error) Example: power/leakage may require 5% or less error (vs. SPICE) 15% Switch Level Event Driven Connectivity Functional 5% 1% SPICE Spice High Accurate Mode Accurate Timing Accurate Power Accurate Leakage Accurate Analog 1M 3 1B Capacity

4 TM Highlights world s first and only Spice! Scalable Parallelization Efficient Memory Management Big Data Architecture Pure SPICE engine - NO approximations Faster than Scalable to 32+ threads -scale capacity (>10 9 elements) Pure SPICE Engine Guaranteed accuracy NO options DC always converges Current traceability & more 4

5 Guaranteed Accuracy Pure SPICE engine NO approximations! Single matrix solving + full analytical device models Foundry validated accuracy and compatibility TSMC Model Certification Share engine with BSIMProPlus TM golden modeling tool used by all foundries FinFET (16/14/10nm) and FD-SOI (28nm) ready Macro Model MOSFET: BSIM3 BSIM4 BSIM6 PSP HiSIM2 BSIM-CMG BSIM-IMG MOS11 MOS9 EKV BJT/HBT: Gummel-Poon Mextram HICUM VBIC BSIMProPlus TM SPICE Modeling Platform TM Reliability: AgeMOS User-defined Model HV Device: HiSIM_HV Level 101 CDN-LDMOS Level 66 User-defined Models RF Models SOI/TFT: UTSOI BSIMSOI BSIM-CMG BSIM-IMG BSIMPD BTASOI RPI a-si RPI p-si 5

6 Faster Than Same Accuracy For memory circuits, delivers 3X speedup on average vs. with <1% accuracy level can simulate 1 billion+ memory circuits which no SPICE simulators can handle (can t load or out of memory) 1673s Accuracy: 0.8% Speedup: 2.53X Accuracy: 0.27% Speedup: 3.66X Accuracy: 0.68% Speedup: 2.76X 661s 612s 815s SRAM (816K elements) Delay time simulation 167s SRAM (245K elements) Setup time simulation 295s Peripheral (884K elements) Average current simulation 6

7 Faster & Much More Accurate can run faster than (not in fast mode or functional or switch-level connectivity verifications) Performance specially optimized for BSIM-CMG and UTSOI models Case study full chip leakage verification A full chip SRAM with 495M elements (483M parasitic R&C) requires options and tuning very unreliable & unpredictable accurate mode significantly slows down the 24 cores 35.5hrs 173GB 173GB -21mA -25mA 11.37hrs 15.3hrs (accurate) 69.1GB (default) (accurate) -6mA (accurate) (default) (default) Simulation time Memory consuption Leakage current 7

8 Drop-in Replacement. NO Learning Drop-in replacement of SPICE/ in existing design flows Full SPICE analysis features, and standard input/output formats Input Netlist (Hspice/Spectre) Spice Models Stimulus files (vec, vcd, ) Parasitic files (SPEF) IBIS, S-para, transmission line DC AC tran noise tran noise info sweep alter Monte Carlo PVT Output FSDB, PSFASCII, SPICEASCII, ASCII, Replacing in design flows Characterization Power/leakage verification Timing verification Functional verification 8

9 Application Spaces Analog (PLL, ADC, PMIC, I/O, ) Digital (Std. cell, small block) Memory Block (Bitcell, sens. amp, driver, small block) Replacing Traditional applications Verification & Signoff Accurate Power/Leakage /Timing/Noise Large Block or Full Chip Characterization Custom Digital (clock tree, etc) DRAM, SRAM, Flash IC Embedded Memory IP SOC Full Chip 9

10 Key Takeaways Directly replace or use as the golden reference in your existing verification & signoff flows Superior Accuracy & Speed Faster than with true SPICE accuracy and DC convergence. Parallelization scalable to 32+ threads. -scale Capacity Handles real giga-scale full chip verification & signoff (>10 9 elements) for DRAM, SRAM, Flash, Custom Digital No Options Drop-in replacement of in design flows. No tuning, removes guesswork from 16/14/10nm FinFET & 28nm FD-SOI Foundry validated accuracy & compatibility. Performance specially optimized for BSIM-CMG & UTSOI 10