A Power Optimization Toolbox for Logic Synthesis and Mapping

Transcription

1 A Power Optmzaton Toolbox for Logc Synthess and Mappng Alan Mshchenko Robert Brayton Stephen Jang Kevn Chung Department of EECS, Unversty of Calforna, Berkeley LogcMll Technology Qualcom Innovatons {alanm, Abstract The paper descrbes several complementary algorthms for power-aware logc optmzaton: o SmSwtch s an effcent sequental smulator for estmatng swtchng actvty of sgnals n large sequental desgns. o PowerMap uses swtchng actvty to make better decsons durng power-aware technology mappng. o PowerDC s a resynthess algorthm that elmnates wres wth hgh swtchng actvty. The proposed smulator draws on new deas n logc representaton and s geared for speed, e.g. t can smulate a 1Mnode sequental desgn usng 1000 bt patterns for 100 cycles n about 10 seconds on a typcal one-core CPU. Ths s more than 85X faster than prevously publshed actvty estmators wth smlar accuracy. Experments show that, although each technque contrbutes to the fnal qualty, t s ther combnaton that gves the best results. When appled to large ndustral desgns n a hghly-optmzed ndustral flow, prevous work on sequental synthess and wre-aware technology mappng led to a 27.6% reducton n swtchng actvty, whle the technques of ths paper reduce t addtonally by 19.6% wthout a substantal ncrease n runtme or degradaton of other metrcs. 1 Introducton Wth the ncrease of the desgn sze and the reducton of feature sze, power mnmzaton becomes an mportant ssue. Accordng to current estmates, about 67% of power dsspaton n FPGA devces s due to dynamc power [3]. Ths hgh power consumpton s an ncreasng concern for FPGA vendors and ther customers. Reducng power s key to lowerng packagng and coolng costs, and mprovng devce relablty [13]. Total power n an FPGA (or any semconductor devce) conssts of statc power and dynamc power. Statc power results prmarly from transstor leakage current, whch s the small current that travels ether from source-to-dran or through the gate oxde when the transstor s logcally off [33]. Dynamc power dsspaton s caused by sgnal transtons n a crcut and comes from the clock and logc networks. These transtons can be part of normal operaton or can be due to gltchng. The dynamc power s characterzed by the equaton: 1 2 P = f V C dynamc s 2 sgnals where f s the clock frequency, V the supply voltage, C the capactance swtched by sgnal, and s s the probablty of sgnal makng a transton. An overvew of leakage reducton technques used n ASICs and mcroprocessor s descrbed n [30]. However, the focus of ths paper s on reducng the dynamc power consumpton due to sgnal swtchng n the logc network. Most power-aware technology mappng [3] and power-aware placement and routng [15] use swtchng actvty nformaton of the netlst to estmate dynamc power dsspaton. Technques for estmatng swtchng actvty can be smulatonbased or probablty-based (or vectorless). Ths work uses smulaton, whch s more accurate but slower [16]. Sequental smulaton s appled to a Boolean network consstng of logc gates and flp-flops whle keepng track of the transtons. Gatelevel smulaton s a well-studed problem and much effort has been placed on mprovng ts speed [17][30]. Despte many nnovatons, gate-level smulaton remans slow for large desgns. Logc synthess and technology mappng transform logc mplementaton by choosng among dfferent crcut structures. Gven the goal of reducng dynamc power dsspaton, t s natural to seek logc structures resultng n a reducton of the total swtchng actvty of ther consttuent nodes. Thus, t s mportant to develop a fast and accurate swtchng actvty estmator that can drve power-aware technology mappng and resynthess. The present paper contrbutes to these goals n several ways: It descrbes an mplementaton of an effcent sequental smulator, SmSwtch, for estmatng swtchng actvty of all sgnals n a sequental desgn. Ths estmaton s used to gude power-aware logc synthess by evaluatng dfferent restructurng and mappng choces. It descrbes two synergstc algorthms, PowerMap and PowerDC, performng power-aware technology mappng and restructurng of the crcut whle tryng to mnmze the total swtchng actvty. It offers an expermental evaluaton of these methods and demonstrates that a substantal reducton n the dynamc power s possble wthout ncreasng runtme and compromsng other parameters such as area and delay. The contrbutons of ths paper can be extended to work for standard-cell desgns. In partcular, the same sequental smulator can be used to estmate swtchng actvty of all sgnals. A cutbased standard-cell mapper [5] can be modfed to take swtchng actvty nto account, leadng to mappngs wth reduced power consumpton. Fnally, a don t-care-based optmzaton envronment for standard-cells can be developed based on the same methodology as [27]. Ths optmzaton wll rewre a standard-cell desgn whle replacng nets wth hgh swtchng actvty by nets wth low swtchng actvty. Although development of such an envronment s beyond the scope of ths work, our experence wth other optmzatons applcable to both standard-cell and LUT-based desgns suggests that powerreductons for standard-cells are lkely to be comparable to those for the LUT-based desgns presented n ths paper. The rest of the paper s organzed as follows. Secton 2 provdes necessary background on logc synthess and technology mappng. Secton 3 descrbes the sequental smulator for power estmaton. Secton 4 presents the power-aware logc optmzaton algorthms. Secton 5 shows expermental results. Fnally, Secton 6 concludes the paper and outlnes future work. 2 Background 2.1 Boolean Networks A Boolean network s a drected acyclc graph (DAG) wth nodes correspondng to logc gates and drected edges

2 correspondng to wres connectng the gates. The terms Boolean network and crcut are used nterchangeably n ths paper. If the network s sequental, the memory elements are assumed to be D-flp-flops wth ntal states. Terms memory elements, flopflops, and regsters are used nterchangeably n ths paper. A node n has zero or more fanns,.e. nodes that are drvng n, and zero or more fanouts,.e. nodes drven by n. The prmary nputs (PIs) are nodes wthout fanns n the current network. The prmary outputs (POs) are a subset of nodes of the network. If the network s sequental, t contans regsters whose nputs and output are treated as addtonal PIs/POs n combnatonal optmzaton and mappng. It s assumed that each node has a unque nteger called ts node ID. A cut C of node n, called root, s a set of nodes, called leaves, such that each path from a PI to n passes through at least one leaf. A cut s K-feasble f ts cardnalty does not exceed K. A cut s domnated f there s another cut of the same node, contaned, settheoretcally, n the gven cut. A fann (fanout) cone of node n s the subset of the nodes of the network reachable through the fann (fanout) edges from n. A maxmum fanout free cone (MFFC) of node n s a subset of the fann cone, such that every path from a node n the subset to the POs passes through n. Informally, the MFFC of a node contans all the logc used exclusvely to generate the output functon of the node. When a node s removed due to redundancy, the logc n ts MFFC can also be removed. 2.2 And-Inverter Graphs A combnatonal And-Inverter Graph (AIG) [22] s a drected acyclc graph (DAG), n whch a node has ether 0 or 2 ncomng edges. A node wth no ncomng edges s a prmary nput (PI). A node wth 2 ncomng edges s a two-nput AND gate. An edge s ether complemented or not. A complemented edge ndcates the nverson of the sgnal. Certan nodes are marked as prmary outputs (POs). The combnatonal logc of an arbtrary Boolean network can be factored [4] and transformed nto an AIG usng DeMorgan s rule. 2.3 Technology Mappng wth Structural Choces A typcal procedure for structural technology mappng conssts of the followng step: 1) cut enumeraton, 2) delay-optmal mappng, 3) area recovery usng heurstcs, 4) producng the resultng LUT network. A detaled descrpton of these steps s gven n [7]. The man drawback of the structural approaches to technology mappng s ther dependence on the crcut structure gven to the mapper (also known as the problem of structural bas ). If the structure s bad, nether heurstcs nor teratve recovery procedures wll lead to a good result of mappng. To overcome the bas of a sngle netlst structure, mappng wth structural choces (lossless synthess) s explored n [5] and [24]. The structural choces are constructed by recordng equvalent crcut structures at a subset of nodes (called choce nodes). These alternatve structures come from synthess transformatons, such as, AIG rewrtng/balancng or co-factorng. As the mapper traverses over these choce nodes n the subject graph, t can explore the multple alternatve mplementatons smultaneously. It s found that usng structural choces over multple passes of LUT mappng yelds sgnfcantly better results, compared to mappng wthout choces or runnng only a sngle teraton of mappng wth choces [24]. Mappng wth structural choces s used n the experments results secton. 3 Sequental Smulaton (SmSwtch) A sequental smulator apples sequences of values to the prmary nputs. It s assumed that the ntal state of the desgn s known and used to smulate the frst frame. In subsequent frames, the state derved at the prevous teraton s used. Input nformaton (such as the probablty of a transton occurrng) can be gven by the user or produced by another tool (for example, f an nput trace s known, t may be appled to smulate the desg. In ths work, sequental smulaton s used to estmate swtchng actvty of regsters and nternal nodes. Ths s used later to gude heurstc power-aware optmzaton. The desgn s sequentally smulated for a fxed number of tmeframes. The random nput patterns are generated to have a 0.5 probablty of the probablty of the node changng ts value (toggle rate) s fxed. Smulaton s performed from the ntal state for a fxed number of cycles (typcally, 64), of whch the frst few (typcally, 16) are skpped as not representatve of normal operaton; the remanng ones are used to accumulate the swtchng actvty. Prevous work [6][8][12][18] concluded that the man problem wth sequental smulaton for swtchng-actvty estmaton s the prohbtve runtme of the smulator. In ths work, we address ths problem wth SmSwtch, based on new logc representaton and manpulaton methods. The salent features of the new smulator are descrbed below. In general, the smaller the memory footprnt of the smulator, the faster t runs. Ths s due to a CPU havng typcally a local cache rangng n sze from 2Mb to 16Mb. If an applcaton requres more memory than fts nto the cache, repeated cache msses cause the runtme to degrade. Therefore, the challenge s to desgn the smulator that uses mnmalstc data-structures wthout compromsng the computaton speed. We found three orthogonal ways of reducng the memory requrements of the smulator, wthout mpactng ts performance. 4 Approaches to Power Mnmzaton In ths secton, two orthogonal ways of usng swtchng actvty are descrbed. The frst (PowerMap) uses swtchng actvty to make better decsons durng technology mappng whle the second (PowerDC) does power-aware re-synthess after mappng. 4.1 Technology Mappng (PowerMap) LUT-based mappers [7][19][23] have evolved from the frst technology mappng solutons for FPGAs [11][9], to those that have reduced runtme, mproved qualty of results, and allow users to select cost-functons employed durng decson makng, as n [21]. In partcular, a recent technology mapper [23] was successfully modfed to accommodate heurstcs for reducng wre-length and mprovng desgn routablty (WreMap) [12][14]. We propose a smlar modfcaton of the prorty-cut based mapper [23] geared towards reducng swtchng actvty, resultng n an algorthm called PowerMap. Snce the basc mappng algorthm s descrbed n detal n [23] and [14], here we only descrbe the changes n the new cost functon whch use swtchng actvty to prortze the cuts durng technology mappng. The ntuton behnd power-aware technology mappng s to try to cover the nodes wth hgh swtchng actvty (or hot nodes) so they are hdden nsde a LUT. Snce the capactance nsde a LUT s very small, power consumpton wll be reduced. The followng three metrcs are compared below: area flow [10][19][23], edge flow (WreMap) [14], swtchng flow (PowerMap) (ths paper).

3 Area flow (AF) s defned as: AF( Leaf ( ) AF( = Area(, (1) + NumFanout( Leaf ( ) where Area( s the area of the LUT used to map node n, Leaf ( s the -th leaf of the representatve cut of node n, and NumFanouts(Leaf () s the number of fanouts of node Leaf ( n the currently selected mappng. Edge flow (EF) s defned as: EF( Leaf ( ) EF( = Edge(, (2) + NumFanout( Leaf ( ) where Edge( s the total number of fann edges (or wres) of the LUT used to map the current representatve cut of node n, whle other notatons are the same as n (1). Swtchng flow s defned as: SwtchFlow( = Swtch( + SwtchFlow( Leaf ( ), (3) NumFanout( Leaf ( ) where Swtch( s the total swtchng actvty at the output of node n, computed usng sequental smulaton (from Secton 3). Intutvely, each of these flows s an estmate of a resource (area, wrng, swtchng) assocated wth the logc rooted at node n. The man dea s to compute for each cut three dfferent metrcs (flows) capturng the global vew of the netlst durng mappng: area flow, edge flow, and swtchng flow. When computng these metrcs, each cut s characterzed by 1) ts own resources used and 2) the resources used by ts fanns. The value of a resource of a fann s dvded by the number of the fann s fanouts. Consder node n1 n Fgure 1. The drect resources of n1 are: 1) the node tself; 2) the three nput edges; 3) the total resources for the three edges. For nodes n2 and n4, half of the resources s used by node n1 whle the other half s used by other fanouts. For node n3, all resources are used by node n1. Resources owned by the nodes n1 n5 Resources owned by the nodes Formulas (1)-(3) provde dfferent applcatons of the noton of a flow when appled to technology mappng. The cost functons measure ncreasngly complex netlst metrcs, startng from area (LUT count) to the number of fanns (routng wres) to the total swtchng actvty of fanns (power estmate), whle the noton of a flow captures the fact that each ncomng flow s shared by the fanouts of the fanns, whch gves a global vew of each cost functon durng technology mappng. 4.2 SAT-Based Resynthess (PowerDC) An effcent approach to resyntheszng logc networks after technology mappng s gven n [27]. Its features are lsted below: substantal optmzaton power, due to the use of nternal don t-cares; scalable local computaton, due to the use of wndowng; computaton speed, due to the use of Boolean satsfablty for functonal manpulaton, and ablty to accommodate varous optmzaton objectves. Resubsttuton s a logc restructurng technque that modfes the local space of a mapped node by addng or removng ts fanns. When appled to a Boolean network, resubsttuton can be teratvely appled, amng at mnmzng a gven cost functon, such as area, delay, wre-length, etc. The man dea of the power-aware flavor of the resynthess algorthm, called PowerDC, s summarzed below. For detals on the basc algorthm and ts mplementaton, refer to [20][27]. Gven a mapped network, t s frst transformed nto an AIG by applyng Boolean decomposton of the logcal functons of the LUTs nto two-nput gates. Then sequental smulaton s appled to the AIG, resultng n the transton probabltes for all the AIG nodes. Ths nformaton s back-annotated to the mapped network to provde the swtchng actvty for all nodes n the mappng. Next, a subset of wres, called hot wres, s dentfed. Based on the experments, f the toggle rate for prmary nputs s 0.5, hot wres are those wth swtchng probablty greater than 0.4. Note that swtchng computed as a transton probablty may be hgher than 0.5 (but cannot exceed 1.0). Another way of defnng hot wres mght be a fxed rato (say, 10%) of the wres wth the hghest swtchng actvty. n2 n3 n4 Power dstrbuton Fgure 1: Metrcs used n PowerMap. The use of the cost functon (3) durng power-aware technology mappng s smlar to that of ts use n (2) n wreaware mappng [14]. The man dfferences are as follows. When comparng two cuts, ther area flows are compared frst, whle ther swtchng flows are used as the frst te-breaker,.e. f the area flows of two cuts are equal up to a certan delta (say, 0.001), the decson of what cut to use s made based on the swtchng flow. Smlarly, edge flow s used as the second te-breaker. Smlarly, n the second phase of technology mappng when local areas of cuts are compared [14], local swtchng s used as the frst te-breaker and edge flow s used as the second tebreaker. The local area of a cut s the sum of the areas of the LUTs n the MFFC of the cut. Smlarly, the local swtchng of a cut s the sum of swtchng actvtes of the LUTs n the cut s MFFC. Percentage % 90.00% 80.00% 70.00% 60.00% 50.00% 40.00% 30.00% 20.00% 10.00% 0.00% T5 T4 T3 T2 T1 Nodes 5.25% 1.09% 0.64% 0.84% 92.16% Wre 13.90% 1.62% 0.91% 1.29% 82.27% Pwr 85.90% 7.36% 2.68% 2.32% 1.74% Swtchng frequency (T5 s hot and T1 s cool) Nodes Wre Pwr Fgure 2: Dstrbuton of wres and nodes by toggle rate. Based on an experment descrbed n Secton 5, about 13.9% of wres are hot and these contrbute about 86% of the total power % of wres are cool but these only contrbute 1.74% of the total power. A detaled dstrbuton of wres (and nodes) by swtchng actvty and ther power contrbuton are shown n

4 Fgure 2. Snce the vast majorty of dynamc power s dsspated n a small percentage of hot wres, power reducton technques targetng hot wres are very effectve. After hot nodes are found, SAT-based resubsttuton [27] s appled targetng hot nodes as fanns of other mapped nodes. The goal s to remove or replace them by cooler fanns. To save runtme, swtchng actvty s not updated after ndvdual steps of resubsttuton. Ths s reasonable because, although Boolean functons of the nodes after resynthess wth observablty don t-cares may be changed, ther swtchng actvty does not change substantally. Even when t changes, the percentage of nodes whose hot/cool status s modfed durng resynthess, s typcally neglgble. 5 Expermental Results The algorthms of ths paper were mplemented n ABC [1]. Expermental evaluaton targetng 6-LUT mplementatons were performed usng a sute of 20 large ndustral desgns rangng n sze from 12K to 165K 6-LUTs. The experments were run on an Intel Xeon 3GHz 2-CPU 4-core computer wth 8GB of RAM. The resultng networks were verfed usng combnatonal equvalence checker n ABC (command cec). The power consumpton of a crcut s the sum of the power consumed by each wre and the power consumed by each wre s the product of the capactance and swtchng actvty for the wre. Because the netlsts were not placed n ths experment, the capactance of each wre was not known. We assumed a untcapactance model for each wre n our dynamc power calculatons. Note that ths power model assumes that each fanout connecton has the same capactance for a multple fanout net. The sequental smulator for estmatng the swtchng actvty was based on a new AIG package, called ga. The followng commands n ABC were extended to be power-aware. In each case, new swtch -p enables swtchng actvty mnmzaton: Technology mappng for FPGAs [23] (command f p). SAT-based resubsttuton [27] (command mfs p). Swtchng actvty report (command ps p). Several other commands, ncludng sequental synthess and mappng wth structural choces, were used n ths experment: Structural sequental cleanup [26] (command scl). Parttoned regster-correspondence computaton usng smple nducton [26] (command lcorr). Parttoned sgnal-correspondence computaton usng k-step nducton [26] (command scorr). Computaton of structural choces [3] (command dch). 5.1 Smulaton Runtme As mentoned, one of the man ssues wth sequental smulaton s potentally long runtme. In ths secton, we performed two experments. In the frst experment we showed that runnng SmSwtch offers affordable runtme for large desgns. In the second experment, we showed that the runtme of SmSwtch s very fast compared wth ACE-2.0 [16], a fast swtchng estmaton tool that s avalable to the publc. In the frst experment, four ndustral desgns rangng from 304K to 1.3M AIG nodes were smulated wth dfferent numbers of smulaton patterns, rangng from 2,560 to 20,480. The nput toggle rate was assumed to be 0.5. The results are shown n Table 1. Columns AIG and FF show the number of AIG nodes and regsters. The runtmes for dfferent szes of nputs patterns are shown n the last columns. Note that the runtmes are qute affordable even for Desgn C4 wth 1.3M AIG nodes (about 160 K 6-LUT after mappng). In most cases, 2,560 patterns were suffcent for node swtchng actvty rates to converge. Table 1: Runtme of SmSwtch. Desgn AIG FF Runtme for nputs patterns (seconds) C1 304K C2 362K C3 842K C4 1306K In the second experment, we compared the runtme of SmSwtch vs. ACE-2.0 on 14 ndustry desgns and 12 large academc benchmarks. The nput toggle rate s assumed to be 0.5 for both tools. The number of nput patterns s assumed to be 5,000 for both runs. All crcuts are decomposed to AIG netlsts before performng swtchng estmaton. The results, not shown n ths paper, lead to the followng observatons. SmSwtch can fnsh all the desgns n very affordable tme but ACE-2.0 gets 4 tmeouts n ndustry desgns. For ndustry desgns, the runtme of SmSwtch s 146+ tmes faster than ACE-2.0. For large academc benchmarks, the runtme of SmSwtch s 85+ tmes faster than ACE Power-Aware Optmzatons To evaluate the contrbuton of power-aware mappng and resynthess, three experments were performed, denoted Baselne, FullOpt, and PowerMap. Baselne corresponds to two runs of (dch; f e). It performs prorty-cut based technology mappng wth structure choces. WreMap [14] s not used for Baselne because WreMap s known to reduce power dsspaton as a by-product of wre count mnmzaton. FullOpt s the complete flow ncludng hgh-effort sequental and combnatonal logc synthess. Sequental synthess (scl; lcorr; scorr) [26] s run frst to remove sequentally equvalent nodes and regsters. Then, two teratons of combnatonal synthess and mappng wth structural choces are performed (dch; f). WreMap s used n ths flow. It reduces 10% of the wres on top of Baselne [14]. In the PowerMap run, FullOpt s used as the nput netlst followed by two runs (dch; f p), whch s the power-aware technology mappng developed n ths paper. In the PowerDC run, the results of PowerMap are used as nput followed by two teratons of power-aware resynthess (mfs p). The sequental smulator SmSwtch s used to drve the poweraware logc synthess. In sequental smulaton, 2,560 random nput patterns wth a toggle rate of 0.5 were used. The results are reported n Table 4. (Detaled results for some desgns n the table are omtted due to page lmtaton, but the averages are computed over all desgns.) Columns PI, PO, FF, and LUT show the number of prmary nputs, prmary outputs, flp-flops, and 6- nput LUTs. Columns Lv and Pwr show the number of logc levels and the total swtchng actvty of the network. The expermental results lead to the followng observatons: FullOpt mproved on Baselne n the number of regsters, LUTs, and logc levels by 14.8%, 12.2%, and 3%, respectvely. Power s reduced by 27%.

5 FullOpt, PowerMap, and PowerDC have the same number of regsters because only combnatonal synthess s used n PowerMap and PowerDC. PowerMap produces an addtonal 10.5% power reducton on top of FullOpt. PowerDC produces an addtonal 10.1% power reducton on top of PowerMap. The overall power reducton for PowerDC vs. FullOpt s 19.6%. The overall power reducton for PowerDC vs. Baselne s 41.9%. Note that when runnng PowerMap and PowerDC, the LUT count and logc delay s reduced slghtly. The addtonal optmzatons reduce power wthout any effect on desgn speed. To nvestgate robustness of the algorthm, we performed the same experments and changed the toggle rate of the nputs from 0.5 to The results are summarzed n Table 2. PowerMap produces an addtonal 9.8% power reducton on top of FullOpt PowerDC produces an addtonal 8.7% power reducton on top of PowerMap. The power reducton for PowerDC vs. FullOpt s 17.7%. The power reducton for PowerDC vs. Baselne s 39.7% Table 2: Comparson of power-optmzaton algorthms (nputs toggle rate s 0.25). Power BaseLne FullOpt PwrMap PwrDC Geomean Rato Rato Rato Wre Dstrbuton Analyss For the same sute of 20 desgns, the changes n the dstrbuton of wres by ther swtchng actvty as a result of resynthess s analyzed. The results are reported Fgure 3. Column T5 s the total number of wres whose swtchng probablty exceeds 0.4. These hot wres are targeted by power reducton. Column T4 s the total number of wres whose swtchng probablty s between 0.3 and 0.4. Columns T3, T2, and T1 are defned smlarly. Thus the T1 wres are the cool wres. In general, they don t contrbute much to the power because ther swtchng probablty s less than 0.1. The results n Fgure 3 lead to the followng observatons: For PowerMap vs. FullOpt, hot (T5) wres are reduced by 13.22%, and T4 are ncreased by 4.96%. Ths ndcates that PowerMap reduces the number of hot wres. For PowerDC vs. PowerMap, total wres are reduced by 2.7% but power s reduced by 10.1%. Thus, the resynthess has removed the rght wres,.e., the hot wres. Hot wres are reduced by 11.04%. The cooler wres are reduced also but the reducton s smaller n ths case. In addton to wre count reducton for hot wres, the wre dstrbuton n terms of toggle rates s also mproved. Fgure 4 shows the power dstrbuton before and after optmzaton. Wre and Wre2 are the percentages of wres, whle Pwr and Pwr2 are the percentages of power contrbutons before and after optmzaton. The chart leads to the followng conclusons: After FullOpt, 13.9% (82.3%) of the wres are hot (cool). After PowerMap, 11.4% (84.6%) of wres are hot (cool). After FullOpt, 85.9% (1.7%) of the power s contrbuted by hot (cool) wres. After PowerMap, 82.6% (2.0%) of power s contrbuted by hot (cool) wres. The above observatons show that the power contrbuted by hot wres s less than Baselne whle the power contrbuted by cool wres s more than Baselne. The concluson s that the poweraware logc synthess was able to shft the peak of power consumpton to lower-swtchng wres. Reducton (negatve s go Percentage 10.00% 5.00% 0.00% -5.00% % % PowrMap vs FullOpt Wre Comparson T5 T4 T3 T2 T1 Total Wrs PowerDc vs. PowrMap Fgure 3: The changes n wre ratos after two power-aware transforms % 80.00% 60.00% 40.00% 20.00% 0.00% Power dstrbuton before/after optmzaton T5 T4 T3 T2 T1 Wre 13.90% 1.62% 0.91% 1.29% 82.27% Wre % 1.79% 0.93% 1.29% 84.55% Pwr 85.90% 7.36% 2.68% 2.32% 1.74% Pwr % 9.48% 3.19% 2.69% 2.02% Swtchng frequency (temperature) Wre Wre2 Pwr Pwr2 Fgure 4: Power dstrbuton before/after optmzaton. 6 Conclusons Ths paper descrbes a toolbox for power-aware logc synthess and mappng. Estmaton of power consumpton at the early stages of the desgn flow s based on calculatng the probabltes of sgnal transton durng sequental smulaton. The toolbox also ncludes two technques for optmzng the desgn durng synthess and mappng to reduce swtchng actvty and thereby mnmze dynamc power consumpton: PowerMap: a power-aware LUT mapper that extends [23] to prortze cuts based on swtchng actvty of the nodes. PowerDC: a SAT-based engne for resubsttuton wth don t-cares that extends [27] to remove sgnals wth hgh swtchng actvty (so called hot sgnals ). Estmaton of power dsspaton s effcently performed by a new sequental smulator, SmSwtch. The estmaton converges for most ndustral desgns after a reasonable number of smulaton cycles. Ths allows for makng targeted heurstc decsons durng logc synthess and technology mappng Future work wll nclude: Speedng up swtchng actvty estmaton (t s estmated that the current mplementaton can be made 50% faster). Extendng swtchng actvty computaton to nclude gltch estmaton.

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