Unified Generation of Analog Sizing and Placement Constraints

Transcription

1 Unified Generation of Analog Sizing and Placement Constraints Michael Eick and Helmut Graeb Institute for Prof. Dr.-Ing. Ulf Schlichtmann

2 Overview Analog constraints Unified constraint generation flow Universal constraint graph Sizing and placement constraint generation Experimental results Conclusion 2

3 Constraints in Design Flow specification structure structural analysis sizing placement routing sizing constraints placement constraints routing constraints universal constraints analog block process variations, parasitic devices etc. 3

4 Matching Constraints - Sizing minimal equal lengths fixed ratio (optional) current matching (optional) maximal moderate voltage matching (optional) limited V gs, V ds mismatch [Hastings, The Art of Analog Layout] 4

5 Matching Constraints - Placement minimal equal finger geometries equal orientation close proximity maximal moderate common centroid quadratic common centroid [Hastings, The Art of Analog Layout] 5

6 More Constraints Operating Point Constraints linear / saturation region Symmetric Place & Route Constraints 6

7 State of the Art Massier et al. TCAD 08 sizing constraints building block analysis symmetry analysis sensitivity analysis Eick et al. TCAD 11 Kole et al. ISCAS 94 Hao et al. ICCCS 04 Malavasi et al. TCAD 96 Chen et al. IEE Proc. G 92 placement constraints Abstract constraint management concepts [Jerke et al. ISPD 09] 7

8 Structural Analysis Building Block Analysis [Massier et al. TCAD 08] Symmetry Analysis [Eick et al. TCAD 11] current mirror differential pair comparison with library ambiguity resolution Structural Signal Flow Graph propagation of symmetry pairs 8

9 Unified Constraint Generation Flow netlist sizing constraints building blocks universal constraint graph placement constraints symmetrical devices 9

10 Overview Analog constraints Unified constraint generation flow Universal constraint graph Sizing and placement constraint generation Experimental results Conclusion 10

11 Universal Constraint Graph (UCG) Undirected Graph Nodes: Devices Edges: Edge Constraint Attributes proximity operating point robust operation matching symmetry region: linear, saturation grade: minimal, moderate, maximal type: undefined, voltage, i current ratio: variable, fixed(value) 11

12 UCG Generation - Overview netlist building blocks symmetrical devices Edge Constraint proximity op. point / robust op. matching symmetry 12

13 UCG Generation - Netlist netlist building blocks symmetrical devices Edge Constraint proximity op. point / robust op. matching symmetry 13

14 UCG Generation Building Blocks netlist building blocks symmetrical devices Edge Constraint proximity op. point / robust op. matching symmetry s s s s min,i,v s max,v,f(1) min,i,v s 14

15 UCG Generation - Symmetry netlist building blocks symmetrical devices Edge Constraint proximity op. point / robust op. matching symmetry mod,u,f(1) mod,u,f(1) mod,u,f(1) 15

16 Unified Constraint Generation Flow netlist sizing constraints building blocks universal constraint graph placement constraints symmetrical devices 16

17 Sizing Constraint Generation Edge Constraint proximity op. point / robust op. matching symmetry operating point linear saturation robust operation general matching general minimal moderate maximal current voltage variable ratio fixed ratio 17

18 Sizing Constraint Examples operating point linear saturation robust operation general matching general minimal moderate maximal current variable ratio voltage fixed ratio (q=1) 18

19 Placement Constraint Generation Edge Constraint proximity op. point / robust op. matching symmetry proximity general matching general minimal moderate perfect variable ratio fixed ratio symmetric placement general 19

20 Placement Constraint Examples proximity general matching general minimal moderate maximal variable ratio fixed ratio (q=1) symmetric placement general 20

21 Overview Analog constraints Unified constraint generation flow Universal constraint graph Sizing and placement constraint generation Experimental results Conclusion 21

22 Experimental Results - Placement Schematic Layout A 0 [db] 72 db 72 db f T [MHz] 12.9 MHz 12.6 MHz CMRR [db] 138 db 144 db V offset [mv] mv 0.3 mv Yield [%] 99.0 % 98.8 % 22

23 Conclusion Knowledge of constraints necessary for (automatic) design of analog circuits Unified constraint generation flow Structural analysis Universal constraint graph Generation of sizing and placement constraints 23