Introduction to Layout design

Transcription

1 Introduction to Layout design Note: some figures are taken from Ref. B. Razavi, Design of Analog CMOS integrated circuits, Mc Graw-Hill, 001, and MOSIS web site: 1

2 Introduction to layout design Layout consist in: Draw geometrical objects of different layers, Make arrays of geometrical objects, Make blocks of arrays for the core, interface, and padframe. Interconnect blocks and interfaces to the padframe, All the layout must satisfy design rules Patterns for the fabrication the masks Why design rules?

3 Layers for designs masks used by L-Edit Default SCNA CMOS Layers Physical layer Name Color N-well N-WELL TAN dashed SiN ACTIVE GREEN filled Polysilicon 1 POLY1 RED filled Polysilicon POLY BLACK filled Contact to poly POLY CONTACT BLACK filled P+ Ion implant PSELECT RED dashed N+ Ion implant NSELECT TAN dashed Contact to N+/P+ ACTIVE CONTACT BLACK filled Metal 1 METAL 1 BLUE filled Metal METAL GREY filled Via oxide cuts VIA WHITE filled Pad contacts OVERGLASS Purple crosshatch

4 Considerations in layout of CMOS D G S Basic layout of a MOSFET 4

5 Considerations in layout of CMOS Changes in W due to tolerances in the fabrication process oxide encroachment D G FOX FOX Drawn Width S p-substrate FOX FOX bird s beak gate oxide FOX FOX FOX W DW/ W p-substrate ideal real 5

6 Considerations in layout of CMOS Changes in L due to tolerances in the fabrication process: Lateral diffusion Drawn Length FOX p + FOX p + n-well L D G S ideal FOX p + FOX p + L DL/ real 6

7 Considerations in layout of CMOS Minimize unwanted diffusion Use minimum poly width (λ) 7

8 Consideration in layout of CMOS Compensating encroachment oxide and lateral diffusion: Due to oxide encroachment, the effective channel width of MOSFETs is smaller than the drawn width. The BSIM SPICE model gives the DW to consider oxide encroachment W eff = W M DW where W M is the drawn width, DW is twice the oxide encroachment. Similarly, due to lateral diffusion, the effective channel length is smaller than the drawn length. The BSIM SPICE model gives the LD and DL parameters to consider lateral diffusion and the changes due to lithography. L eff = L M LD DL Where L M is the drawn length, LD is the interdiffusion and DL is the reduction because of lithography. 8

9 Considerations in layout of CMOS Changes in W due to tolerances in the fabrication process: shadow effect D & S Asymmetry: tilted implant beam to avoid channeling shadowed region Drawn Length D G S asymmetry 9

10 Considerations in layout of CMOS Compensating the shadow effect The asymmetry caused by the shadowing can be ameliorated: assume that transistors are placed parallel as indicated in the Fig. a; if the shadowed terminal is D (or S), then the two devices sustain no asymmetry resulting from shadowing. D if transistor are placed as in the Fig. b; one can add dummy transistors to the two sides of transistors, so that T1 and T see approximately the same environment. D D S D S Fig.b T1 T S Fig.a S Dummy D T1 S D T S Dummy 10

11 Considerations in layout of CMOS Antenna Effect: During the etching of metal1 layer, the metal area acts as an antenna, collecting ions and then rising in potential, therefore the gate voltage can increase so much that the gate oxide breaks down during fabrication. layout susceptible to antenna effect (MOSFET tied to a metal 1 layer having a large area) Antenna Effect Compensation: If large area are inevitable (Fig. a), then a discontinuity can be created as indicated in Fig. b discontinuity in metal 1 layer to avoid antenna effect 11

12 Considerations in layout of CMOS Parasitic Bipolar transistors in CMOS technology NPN NPNP S G PNP S G D B B D N+ N+ P+ N+ P+ P+ n-well p-substrate CMOS Latch-Up When a transient disturbance turns-on either parasitic Q the current flowing through this device will turn on the other parasitic as well. Each Q supplies the other s Base current. Once both Qs begin to conduct they will continue to do so even if the transient disturbance that initiated conduction is removed. The circuit has latched up and it will remain in this state until power is removed. The integrated circuit can actually conduct so much current that it overheats and selfdestructs. Even if this does not occur, latch up causes circuit malfunction and excessive supply current consumption. 1

13 Considerations in layout of CMOS Minimizing Latch-Up Some approaches to reduce latch up Eliminate the forward biased junctions that cause the problem; simple but difficult to achieve Increase the spacing between components. Separate potential injectors from sensitive circuitry, i.e. place power transistors far away of sensitive input circuitry. Increase doping concentrations. CMOS and BiCMOS processes often employ P + substrates to reduce the gain of parasitic Qs. Provide alternate collectors to remove unwanted minority carriers. Use a heavily doped isolation or Bondpad add suitable guard rings. Sensitive analog circuit shielded by the guard ring Guard ring 1

14 Considerations in layout of CMOS Minimizing Latch-Up B contact B contact PMoat guard ring (hole collecting) NMoat guard ring (electron collecting) 14

15 Design Rules for Layout 15

16 Design rules The Design Rules are related to manufacturing constraints and tolerances. There are two systems of rules: Specific values (usually in microns, although there are other possibilities; mils, millimeters, centimeters or inches). Scalable (multiples of some metric λ, typically ½ of the technology) for maximum flexibility. There are five types of Design Rules Minimum width Exact Width Minimum space Surrounding Overlap and Extend 16

17 Basic Design Rules Some SCMOS layout Rules (MOSIS um) Physical layer Meaning Value N-well Minimum well size 10λ N-well spacing Between wells 6λ Poly overlap Minimum extension over ACTIVE λ Poly-Active Minimum spacing 1λ MOSFET Width Minimum N+/P+ MOSFET W λ Active Contact Exact size λxλ Active Contact Minimum space to active edge λ Poly Contact Exact size λxλ Poly Contact Minimum space to poly edge λ Via Exact Size λ Refer: J. P. Uyemura /Physical design of CMOS integrated circuits using L-EDIT 17

18 Minimum width: Design rules The width and (lengths) of the geometries defined on a mask must exceed a minimum value imposed by both lithographic and processing capabilities of the technology. For example if a poly rectangle is excessively narrow, then owing to fabrication tolerances it may break or at least suffer from a large local resistance. 18

19 Exact size: Design rules Certain objects are only permitted to have exact dimensions of (AxB) units as shown in the figure below. This rule apply specifically to contacts and vias to enhance the yield process. A B 19

20 Minimum spacing: Design rules The geometries built in the same mask (or different mask) must be separated by minimum spacing. For example if two poly lines are placed too close to each other, they may be shorted. 0

21 Minimum enclosure: Design rules For example, the active, n+ implant and p+ implant must surround the transistor with sufficient margin to guarantee that the device is contained by these geometries despite fabrication tolerances. 1

22 Minimum extend: Design rules The width and (lengths) of the geometries defined on a mask must exceed a minimum value imposed by both lithographic and processing capabilities of the technology. This is because some geometries must extend beyond the edge of others by a minimum value: For example, for the scheme shown in the figure, the Gate poly rectangle must have a minimum extension beyond the active area to ensure proper transistor action at the edge. Active After implant Poly gate Poly gate Short circuit

23 Design Rules set for standard CMOS processes See for a complete set of design rules for various process: IBM, AMIS, TSMC processes at:

24 Design Rules: Well Lambda Rule Description SCM O S SUBM DEEP 1.1 Minimum width Minimum spacing between wells at different potential Minimum spacing between wells at same potential Minimum spacing between wells of different type (if both are drawn) Exceptions for AMIS C0 0.5 micron process: 1 Use lambda=16 for rule 1. only when using SCN4M or SCN4ME Use lambda=1 for rule 1. only when using SCN4M_SUBM or SCN4ME_SUBM Use lambda=8 for rule 1. only when using SCN4M or SCN4ME 4 Use lambda=11 for rule 1. only when using SCN4M_SUBM or SCN4ME_SUBM 4

25 Design Rules: Active Rule Description SCMOS Lambda SUBM DEEP.1 Minimum width * *. Minimum spacing. Source/d ain active to well edge Substrate/well contact active to well edge.5 Minimum spacing between non-abutting active of different implant * Note: For analog and critical digital designs, MOSIS recommends the following minimum MOS channel widths (active under poly) for AMIS designs. Narrower devices, down to design rule minimum, will be functional, but their electrical characteristics will not scale, and their performance is not predictable from MOSIS SPICE parameters. Process DesignTechnology Design Lambda (microme) Minimum Width (lambda) AMI_ABN SCNA, SCNE AMI_C5F/N SCNM,SCNME AMI_C5F/N SCNM_SUBM,ME_SUBM

26 Design Rules: Poly Rule Description SCMOS Lambda SUBM DEEP.1 Minimum width. Minimum spacing over field..a Minimum spacing over active 4. Minimum gate extension of active.5.4 Minimum active extension of poly 4.5 Minimum field poly to active

27 Design Rules: P & N Select Rule Description SCMOS Lambda SUBM DEEP 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width 4. Minimum select overlap of active 4. Minimum select overlap of contact Minimum select width and spacing (Note: P-select and N- select may be coincident, but must not overlap) (not illustrated) 1 4 Exception for AMIS C0 0.5 micron process: 1 Use lambda= for rule 4.4 only when using SCN4M_SUBM or SCN4ME_SUBM 7

28 Rule Design Rules: Contact to Poly Simple contact to Poly Alternative contact to Poly Lambda Description Rule Description SCMOS SUBM DEEP SCMOS Lambda SUB M DEEP 5.1 Exact contact size x x x 5..b Minimum poly overlap Minimum poly overlap Minimum contact spacing Minimum spacing to gate of transistor b 5.6.b 5.7.b Minimum spacing to other poly Minimum spacing to active (one contact) Minimum spacing to active (many contacts)

29 Rule Minimum spacing to gate of transistor Design Rules: Contact to Active Simple contact to Active Description Exact contact size Minimum active overlap Minimum contact spacing SCMOS x 1.5 Lambda SUBM x 1.5 DEEP x Rule 6..b 6.5.b 6.6.b 6.7.b 6.8.b Alternative contact to Active Description Minimum active overlap Minimum spacing to diffusion active Minimum spacing to field poly (one contact) Minimum spacing to field poly (many contacts) Minimum spacing to poly contact SCM OS Lambda SU BM DE EP

30 Design Rules: Metal1 Rule Description SCMOS Lambda SUBM DEEP 7.1 Minimum width 7. Minimum spacing 7. Minimum overlap of any contact Minimum spacing when either metal line is wider than 10 lambda

31 Design Rules: Via Lambda Rule Description Metal Process + Metal Process SCMOS SUBM DEEP SCMOS SUBM DEEP 8.1 Exact size x n/a n/a x x x 8. Minimum via1 spacing n/a n/a 8. Minimum overlap by metal1 1 n/a n/a Minimum spacing to contact for technology codes mapped to processes that do not allow stacked vias (SCNA, SCNE, SCNM, SCNMLC) n/a n/a n/a 8.5 Minimum spacing to poly or active edge for technology codes mapped to processes that do not allow stacked vias (NOTE: list is not same as for 8.4) n/a n/a n/a 1

32 Design Rules: Via (cont.)

33 Design Rules: Overglass Rule Description Microns 10.1 Minimum bonding passivation opening Minimum probe passivation opening Pad metal overlap of passivation Minimum pad spacing to unrelated metal Minimum pad spacing to active, poly or poly 15

34 Design Rule Checker 4

35 Design verification Design rules are contained within technology file that defines the screen in the L-EDIT buffer. Any other technology file may be loaded using SETUP command. DRC examines the dimensions and spacing for every geometrical object in the layout, and looks for violations of the design rules. DRC allows to check the design before it is submitted for fabrication. 5

36 Full chip DRC: Design verification: options This option checks the entire layout for design rule violations. The DRC divides the layout into a grid of square bins, and then analyses each bin for adherence to the layout rules. Separating the layout in this manner speeds up the analysis, since only local objects are compared. Region-only chip DRC: When this option is selected, the region to be checked is defined by drawing a box with the mouse. All objects that are contained in, or touch the boundary of, this box will be checked. This particularly useful when a small section of layout is modified. 6

37 Design verification: error reporting Design rule violations are reported in ways: 1. Placing error ports at the location where a violation exists,. Placing error markers at the location where the violation exists,. Writing the violation to a text. Since the errors are shown on the layout, they can be identified and corrected. To remove error layer, use the Clear Error Layer command. A typical report in a text file use the following format: <Rule Name>=<Distance><Unit Name>; (<x1>,<y1>) -> (<x><y>) <Rule Name> is the rule that was violated <distance> is the required value of the rule <Unit Name> specifies the units used (λ or um) (<x1>,<y1>) -> (<x>,<y>) specifies the coordinates where violation was found. 7

38 Example: checking design rules The layout in the figure, shows violations of some design rules λ=1um 8

39 Example: checking design rules The layout in the figure, shows no violations of design rules 9