Non-standard geometry scaling effects in SiGe HBTs

Transcription

1 Non-standard geometry scaling effects in SiGe HBTs M. Schröter 1),2), S. Lehmann 1), D. Celi 3) 1) Chair for Electron Devices and Integr. Circuits, Univ. of Technol. Dresden, Germany 2) ECE Dept., University of California San Diego, La Jolla, CA, USA 3) ST Microelectronics, Crolles, France HICUM Workshop, Dresden, June 2007 MS 1

2 OUTLINE Introduction Device structures and investigated effects Simulation Results Discussion Experimental Results Conclusions MS 2

3 Introduction Introduction Circuit Design Compact Modeling circuit optimization device characterization sizing: find optimal device configuration measure few devices extract "specific" par s apply scaling equations compact models for a large variation of device configurations also: predictive and statistical modeling and design accurate physics-based modeling of geometry scaling effects MS 3

4 Introduction Geometry scaling behavior existing geometry scalable models are based on "standard" scaling equation in advanced SiGe HBT process technologies: deviations are observed X A X = X A A+ X p P + 4X C X P peak f T X C X A X A 0 larger devices P/A longer devices accurate modeling of non-standard scaling requires quantification of impact understanding of origin suitable scaling equations l E0 MS 4

5 Device structures and investigated effects Device structures and investigated effects device simulation of 50GHz production process Emitter width: = (0.25, 0.45, 0.65, 1.05, 1.45) µm, unit E length reference ("") structure: doping and Ge profile do not vary with E width x [μm] 0 B log( D ), N122C128 Field oxide y [μm] E D [cm -3 ] 1e+020 1e+019 1e+018 1e+017 1e+016 1e+015 => reference structure characteristics obey standard scaling rules B B E E C x [µm] MS 5

6 Device structures and investigated effects Doping profile of reference structure based on SIMS 1D Profiles under emitter (y = 0.4μm) and external base (y = 0μm) 1e20 1e19 cut at y=0.4µm 0.25 D [1/cm 3 ] 1e18 1e Ge [100%] 1e16 Ge 1e15 cut at y=0µm SIMS DEVICE x [μm] MS 6

7 Device structures and investigated effects DEVICE simulator calibration (reference structure) based on measurements, comparison also with DESSIS J C [ma/μm 2 ] Gummel plot V BC /V = 0.5, 0, symbols: measurements solid lines: DEVICE dashed lines: DESSIS V BC excellent agreement for low and medium injection at high injection: self-heating not included DESSIS with lumped emitter series resistance similar agreement also for other characteristics: C-V, f T (incl. parasitics) V BE [V] acceptable agreement with experimental data over large bias range MS 7

8 Simulator calibration (cont d) f T (GHz) Simulator calibration (cont d) transit frequency: comparison DEVICE, measurements, DESSIS A E0 =0.65x12.65μm 2 symbols: measurements solid lines: DEVICE dashed lines: DESSIS V CB I C /A E0 (ma/μm 2 ) device simulations are missing parasitics => deviation at low J C f t peak reasonably well approximated DEVICE - DESSIS differences caused by mobility differences (mostly Ge dependence description) collector voltages: meas: V BC =0.5; 0; -1.24V DESSIS V BC =0.4; 0; -1.72V DEVICE V BC =0.4; 0.5; 0; -1.24; -1.72V acceptable agreement with experimental data over large bias range MS 8

9 Simulator calibration (cont d) Scaling effects investigated reference width, = 0.65 μm EJD EJI b b x y CWI SIC doping CDQ CDL, Δb/2 b SIC b BCx N C 1 < 2 y PED selected parameters for comparison: mostly process control monitors MS 9

10 Simulation Results Simulation Results low-injection collector current I C /A E0 [na/μm 2 ] EJI Ref EJI EJD CDL PED V =0V, V =0.6V BC BE PED EJD PED, : only different slope N N EJI: non-standard sc. x EJD: non-standard sc. b b P /A [1/μm] E0 E0 x detection possible for junction depth variation (EJI, EJD) MS 10

11 Simulation Results Geometry effects zero-bias BE depletion capacitance C je0 /A E0 [ff/μm 2 ] Ref EJI EJD PED V BC =0V, V BE =0.0V P /A [1/μm] E0 E0 PED EJD EJI behavior similar to I C : negative slope and non-linear scaling detection possible for EJI, EJD, and MS 11

12 Simulation Results Geometry effects zero-bias base resistance (from tetrode structures) R [kω*μm] Ref EJI EJD PED V BC =0V EJI [μm] standard scaling: R B0 = r SBi0 + 2( r Ss b s + R x ) observed with slightly different slope (rsbi) intercept (rss) non-standard scaling: EJI variations within process tolerances overall: fairly small variation in HBTs (as opposed to BJTs) MS 12

13 Simulation Results Geometry effects zero-bias BC depletion capacitance standard scaling according to: ((, PED, EJI, EJD) = ) C jc = C jci A, ( + b SIC ) + 2C jcx A, b BCx V BC =0V, V BE =0.0V b SIC b BCx C jc0 /l E0 [ff/μm] Ref CDL CDL non-standard scaling b N E01 2 C CDL y [μm] is hardly detectable from BC depletion capacitance! N C y MS 13

14 Discussion Δb/2 Discussion consider 2D case (long transistor) I = I A ( Δb) + I Ae Δb + 2I P PED for < Δb: I = I Ae ( ) + 2I P I A I Ae I P X/b 0 b > Δb b < Δb 2/b X -- b in general for X (= I, Q, C) and b (=,b BC,...): = X A ( X Ae X A ) Δb X 2 P --, b > Δb b 2 X Ae ( b) + X P --, b Δb b standard scaling (with different slope) for b > Δb MS 14

15 Discussion Generic equation for describing non-standard scaling C je0 /A E0 [ff/μm 2 ] V BC =0V, V BE =0.0V Ref; X w =0.00fF/μm 3, X A =5.09fF/μm 2, X P =0.15fF/μm EJI; X w =5.77fF/μm 3, X A =2.90fF/μm 2, X P =0.24fF/μm EJD; X w = 2.51fF/μm 3, X A =5.46fF/μm 2, X P =0.29fF/μm ; X w =0.02fF/μm 3, X A =5.09fF/μm 2, X P = 0.11fF/μm P /A [1/μm] E0 E0 X -- A = X w ( P A) X X P P X A P A n -- A 2, l >> b EJD EJI standard scaling equation: P X A + X P -- A wide emitter effects: X w narrow emitter effects: X n user-defined scaling with TRADICA "poly" function: - set X A # - set X P # = = X A X P X w P A P + X n -- A accurate approximation MS 15

16 Experimental Results Experimental Results transit frequency V BC =0V avalanche multiplication factor f T,peak [GHz] CDL M M Ref measured 45 CDL measured [μm] V CE [V] trend follows trend follows not detectable from BC depletion capacitance MS 16

17 Conclusions Conclusions many effects can lead to deviations from standard geometry scaling behavior non-standard scaling cannot be detected from cases with just different slopes need to look at sufficiently large set of characteristics to detect profile variations and most likely cause non-standard geometry scaling can be modeled analytically directly in "specific electrical" parameter calculation preferable: in technology parameters (e.g. average doping) => to be derived yet Acknowledgments financial support from German Ministry of Research and Technology (DFG project SCHR695/2-1) ST Microelectronics, Crolles, France MS 17