Simple Emitter and Collector Scaling Approach with VBIC for Low-cost SiGe:C HBT s

Transcription

1 Simple Emitter and Collector Scaling Approach with VBIC for Low-cost SiGe:C HBT s René F. Scholz *, B. Senapati*, A. Chakravorty #, D. Knoll *, C.K. Maiti # * IHP, Frankfurt (Oder), Germany # IIT, Kharagpur, India Bipolar Arbeitskreis Unterpremstätten October 23-24, 2003

2 Outline Technology and layout for scaling Test structures - general approach Scaling equations - implementation in IC-CAP Measurement setup Results Conclusion

3 SiGe:C Technology - HBT features SIC Coll. Well Deep P Implant (SC) Emitter Emitter SIC Coll. Well n-well MV-HBT MV-HBT n + S/D n-well LV-HBT LV-HBT n + S/D 19 mask BiCMOS process Gate poly used for the external base CMP applied for separating the emitter from the external base 3 types of HBTs by different superpositions of the MOS n-well and isolation (SC) implants with the HBT collector well and SIC implants: Emitter SIC Coll. Well HV-HBT HV-HBT n + S/D n-well BV CEO f T MV-HBT 4V 50GHz LV-HBT 2.4V 75GHz HV-HBT >7V 30GHz Details: D. Knoll et al., IEDM Tech. Dig., p.783, Dec

4 Layout for scaling Scaling approach is demonstrated for the LV device e (SC) LE Drawn Nx Ny Design Kit: 3 values can be accessed in PCell Drawn emitter length (LE Drawn ) Number of emitters by No. of columns (Nx): No. of rows (Ny): 1, 2 Scaling with emitter and collector area

5 Test-structures used for scaling Nx Ny 16 used for scaling T8 used for verification used for plots 12 8 emitter collector T4 (base) T5 T6 T7 LE Drawn scaling : 4 Nx, Ny scaling : 4 verification : 2 total : 9 4 T3 T2 T1 Not optimum choice!!! Emitter length [µm]

6 Scaling approach for model parameter 1. Determine parameters of basic transistor (PAR B ) including temperature behavior and 1/f noise Only one full parameter extraction and optimization! 2. Combining data from different geometries in one IC-CAP setup 3. Determine model parameter for scaled model (PAR S ) by optimization on curves from different geometries Scaled model parameters (PAR S ) are function of basic parameters (PAR B ) and scaling factors (F PAR_SKF )

7 Scaling equations A E = f(le Real ), P E = f(le Real ) real emitter area and perimeter, A C = f(le Real,Nx,Ny), P C = f(le Real,Nx,Ny) real collector area and perimeter Lx Nx A = Lx Nx Ly Ny P C C Ly = = 2( Lx Nx + Ly Ny ) f ( LE Real ) Lx = const Values are normalized to the base device Ly Ny For the base device: CJE S = CJE B A E, P E

8 Scaling with emitter area/perimeter CJE S = CJE B ((1- F CBE_SKF )A E + F CBE_SKF P E ) NX NY Similar: CJC, IS, IKF, IBEI, IBEN, RE, RBI, RCI CJEP (base area) F CBE_SKF = 0.2 fit in this example ITF = f(a E ) i.e. no scaling factor same for other currents

9 Collector scaling and fitting 2. Scaling with collector area CJCP S = CJCP B ((1- F CJCP_SKF )A C + F CJCP_SKF P C ) Similar: RCX, IBEIP, IBENP, RS 3. Scaling with fitting factor RTH 1 RTH = B S RTH_SKF ( Nx Ny ) A E 0.5 < RTH_SKF < 1 Similar: AVC2, RBX (2) Total 18 scaling factors

10 Measurement setup Single setup for DC and RF measurements DC-measurements (4142B) Kelvin probes CV measurements (4284A) RF measurements (PNA E8364A) 45 MHz - 50 GHz Temperature range: -55 C C

11 Results: 5 devices are plotted 16 T8 used for plots 12 collector Nx Ny 8 emitter T4 (base) T5 T6 T7 4 T3 T2 T Emitter length [µm]

12 Results: CV Scaling Base-Collector Capacitance [F] 1x x10-14 Measurement VBIC Model F CBC_SKF and F CJEP_SKF T8 T7 T4 T2 Collector-Substrate Capacitance [F] 1x10-14 Measurement VBIC Model F CJCP_SKF T8 T7 T4 T2 Base-Emitter Voltage [V] Base-Collector Voltage [V] Base-Collector capacitance Collector-Substrate capacitance

13 Results: DC Scaling In all figures curves from transistors with different geometries are plotted Collector Current [A] Measurement VBIC Model T Base-Emitter Voltage [V] 1x10-3 1x10-7 Base Current [A] Collector Current [A] V BE =0.85 V Measurement VBIC Model Contact Resistance Collector-Emitter Voltage [V] T8 T7 T4 T2 Gummel V CB = 0V Output V BE = const.

14 Results: RF Scaling Measurement VBIC Model T2 T4 T7 T Measurement VBIC Model T2 T4 T7T8 60 f T (GHz) f Max [Hz] RBX x10-5 1x Collector Current [A] x10-5 1x Collector Current [A] f T extracted at 5GHz, VCE 1.5V f Max extracted at 24GHz, VCE 1.5V

15 Conclusion Simple scaling approach implemented in IC-CAP Emitter length variation only over a limited range Special layout for multi emitter structures Test structures generated with Pcells We use only RF-Pads, no special test structures DC and RF model accuracy better than 10%